coreboot-gerrit December 2018

coreboot-gerrit@coreboot.org

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1832 discussions

Change in ...coreboot[master]: Documentation/../../kblrvp11: Add RVP11 documentation
by PraveenX Hodagatta Pranesh (Code Review) 04 Dec '18

04 Dec '18

PraveenX Hodagatta Pranesh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29859 ) Change subject: Documentation/../../kblrvp11: Add RVP11 documentation ...................................................................... Patch Set 2: Hi Patrick , please can you approve this patch if no issues ? -- To view, visit https://review.coreboot.org/c/coreboot/+/29859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01509c2fa2c127b77ae72b8b0aaac0f826b0bedd Gerrit-Change-Number: 29859 Gerrit-PatchSet: 2 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 04 Dec 2018 14:59:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src: Get rid of device_t
by build bot (Jenkins) (Code Review) 04 Dec '18

04 Dec '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30004 ) Change subject: src: Get rid of device_t ...................................................................... Patch Set 6: (2 comments) https://review.coreboot.org/#/c/30004/6/src/northbridge/amd/amdmct/mct_ddr3… File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c: https://review.coreboot.org/#/c/30004/6/src/northbridge/amd/amdmct/mct_ddr3… PS6, Line 130: uint32_t index_ctl_reg, uint32_t index) line over 80 characters https://review.coreboot.org/#/c/30004/6/src/northbridge/amd/amdmct/mct_ddr3… PS6, Line 133: uint32_t index_ctl_reg, uint32_t index) line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/30004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic29891d78514db3b7eed48414a14e4ff579436c0 Gerrit-Change-Number: 30004 Gerrit-PatchSet: 6 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 04 Dec 2018 14:48:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/kahlee: the backlight doesn't be enabled if only update RW
by chris wang (Code Review) 04 Dec '18

04 Dec '18

Hello Chris Wang, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30033 to look at the new patch set (#2). Change subject: mb/google/kahlee: the backlight doesn't be enabled if only update RW ...................................................................... mb/google/kahlee: the backlight doesn't be enabled if only update RW Since the initial for APU_EDP_BKLTEN_L was moved to early init. If only update RW section, this GPIO will never be initialized. To uses gpio_output() instead gpio_set(), then the GPIO will be programmed in mainboard_smi_apmc(). BUG=b:120436919 TEST=Build/Verify on Careena and the backlight works normally. Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Ie6606d14bdc91a7f42bf235f64c3d23103cf5915 --- M src/mainboard/google/kahlee/OemCustomize.c M src/mainboard/google/kahlee/smihandler.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/30033/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6606d14bdc91a7f42bf235f64c3d23103cf5915 Gerrit-Change-Number: 30033 Gerrit-PatchSet: 2 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/kahlee: the backlight doesn't be enabled if only update RW
by chris wang (Code Review) 04 Dec '18

04 Dec '18

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30033 to review the following change. Change subject: mb/google/kahlee: the backlight doesn't be enabled if only update RW ...................................................................... mb/google/kahlee: the backlight doesn't be enabled if only update RW Since the initial for APU_EDP_BKLTEN_L was moved to early init. If only update RW section, this GPIO will never be initialized. To uses gpio_output() instead gpio_set(), then the GPIO will be programmed in mainboard_smi_apmc(). Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Ie6606d14bdc91a7f42bf235f64c3d23103cf5915 --- M src/mainboard/google/kahlee/OemCustomize.c M src/mainboard/google/kahlee/smihandler.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/30033/1 diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index fc8ff32..5b2221e 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -90,7 +90,7 @@ * GPIO 133 - Backlight enable (active low) * Pass control of the backlight to the video BIOS */ - gpio_set(GPIO_133, 0); + gpio_output(GPIO_133, 0); printk(BIOS_INFO, "Change panel init timing\n"); params->LvdsPowerOnSeqVaryBlToBlon = cfg->lvds_poseq_varybl_to_blon; diff --git a/src/mainboard/google/kahlee/smihandler.c b/src/mainboard/google/kahlee/smihandler.c index 83757a8..f5decda 100644 --- a/src/mainboard/google/kahlee/smihandler.c +++ b/src/mainboard/google/kahlee/smihandler.c @@ -43,7 +43,7 @@ MAINBOARD_EC_SMI_EVENTS); /* Enable backlight - GPIO active low */ - gpio_set(GPIO_133, 0); + gpio_output(GPIO_133, 0); return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/30033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6606d14bdc91a7f42bf235f64c3d23103cf5915 Gerrit-Change-Number: 30033 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/soc/intel/braswell/cpu.c: Setup local APIC
by Michał Żygowski (Code Review) 04 Dec '18

04 Dec '18

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29290 ) Change subject: src/soc/intel/braswell/cpu.c: Setup local APIC ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1da5b1bf235f34b957142e86c70a9dbfa3ded1d Gerrit-Change-Number: 29290 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 04 Dec 2018 12:33:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mainboard/lenovo/t430s: Add ThinkPad T431s as a variant
by Bill XIE (Code Review) 04 Dec '18

04 Dec '18

Hello Alexander Couzens, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30021 to look at the new patch set (#10). Change subject: mainboard/lenovo/t430s: Add ThinkPad T431s as a variant ...................................................................... mainboard/lenovo/t430s: Add ThinkPad T431s as a variant The code is based on autoport and that for T430s Tested: - CPU i5-3337U - Slotted DIMM 2GiB - Soldered RAM 4GiB from samsung (There may be more models here) - Camera - pci-e and usb2 on M.2 slot with A key for wlan - sata and usb2 (no superspeed components) on M.2 slot with B key for wwan - On board SDHCI connected to pci-e - USB3 ports - libgfxinit-based graphic init - NVRAM options for North and South bridges - Sound - Thinkpad EC - S3 - TPM1 on LPC - EHCI debug on SSP2 (USB3 port on the left) - Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from Linux payload (Heads), Seabios may also work. Not tested: - Fingerprint reader on USB2 (not present on mine) - Keyboard backlight (not present on mine) - "sticky_fn" flag in nvram Not implemented yet: - Fn locking in nvram (may not be identical to "sticky_fn") - C-based native graphic init (since T431s has eDP instead of LVDS) - Detecting the model of Soldered RAM at runtime, and loading the corresponding SPD datum (3 observed) from CBFS (the mechanism may be similar to that on x1_carbon_gen1 and s230u, but I do not know how to find gpio ports for that, and SPD data stored in vendor firmware.) Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a Signed-off-by: Bill XIE <persmule(a)gmail.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/t431s.md A Documentation/mainboard/lenovo/t431s_bc_removed.jpg A Documentation/mainboard/lenovo/t431s_flash_chip.jpg A Documentation/mainboard/lenovo/t431s_programming.jpg M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t430s/Kconfig.name M src/mainboard/lenovo/t430s/Makefile.inc M src/mainboard/lenovo/t430s/board_info.txt M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t430s/hda_verb.c M src/mainboard/lenovo/t430s/romstage.c M src/mainboard/lenovo/t430s/smihandler.c A src/mainboard/lenovo/t430s/variants/t430s/board_info.txt R src/mainboard/lenovo/t430s/variants/t430s/gpio.c A src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c A src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb A src/mainboard/lenovo/t430s/variants/t430s/romstage.c A src/mainboard/lenovo/t430s/variants/t431s/board_info.txt A src/mainboard/lenovo/t430s/variants/t431s/gpio.c A src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c A src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb A src/mainboard/lenovo/t430s/variants/t431s/romstage.c A src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc A src/mainboard/lenovo/t430s/variants/t431s/spd/samsung_4gb.spd.hex 25 files changed, 794 insertions(+), 205 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/30021/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/30021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a Gerrit-Change-Number: 30021 Gerrit-PatchSet: 10 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mainboard/lenovo/t430s: Add ThinkPad T431s as a variant
by Bill XIE (Code Review) 04 Dec '18

04 Dec '18

Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30021 ) Change subject: mainboard/lenovo/t430s: Add ThinkPad T431s as a variant ...................................................................... Patch Set 9: (3 comments) https://review.coreboot.org/#/c/30021/8//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/30021/8//COMMIT_MSG@38 PS8, Line 38: - Detecting the model of Soldered RAM at runtime, and loading the > That should be mentioned in the Documentation ! Ack https://review.coreboot.org/#/c/30021/8/src/mainboard/lenovo/t430s/variants… File src/mainboard/lenovo/t430s/variants/t431s/romstage.c: https://review.coreboot.org/#/c/30021/8/src/mainboard/lenovo/t430s/variants… PS8, Line 37: pci > No need to write it here, only if you want to access io range 0x6a0 in romstage. Ack https://review.coreboot.org/#/c/30021/8/src/mainboard/lenovo/t430s/variants… File src/mainboard/lenovo/t430s/variants/t431s/smihandler.c: https://review.coreboot.org/#/c/30021/8/src/mainboard/lenovo/t430s/variants… PS8, Line 25: > Ack Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/30021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a Gerrit-Change-Number: 30021 Gerrit-PatchSet: 9 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Tue, 04 Dec 2018 11:46:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Bill XIE <persmule(a)gmail.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mainboard/lenovo/t430s: Add ThinkPad T431s as a variant
by Patrick Rudolph (Code Review) 04 Dec '18

04 Dec '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30021 ) Change subject: mainboard/lenovo/t430s: Add ThinkPad T431s as a variant ...................................................................... Patch Set 9: (2 comments) > Patch Set 8: > > (2 comments) > > > Patch Set 8: > > > > (4 comments) > > > > Do you want to add a data.vbt file ? > > How? Can it be dumped someway? Currently using that for T430s seems working. You can use intelvbttool to extract it from VGA Option Rom. https://review.coreboot.org/#/c/30021/8/src/mainboard/lenovo/t430s/variants… File src/mainboard/lenovo/t430s/variants/t431s/romstage.c: https://review.coreboot.org/#/c/30021/8/src/mainboard/lenovo/t430s/variants… PS8, Line 37: pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); > They are different in the last line of this function. There's no COM1 or COM2, so setting IO_DEC is a bit pointless. IMHO this should always be done in chipset code. https://review.coreboot.org/#/c/30021/8/src/mainboard/lenovo/t430s/variants… PS8, Line 37: pci No need to write it here, only if you want to access io range 0x6a0 in romstage. -- To view, visit https://review.coreboot.org/c/coreboot/+/30021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a Gerrit-Change-Number: 30021 Gerrit-PatchSet: 9 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Tue, 04 Dec 2018 10:33:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Bill XIE <persmule(a)gmail.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: Documentation: Clarify minor detail on preparing a layout file
by Patrick Georgi (Code Review) 04 Dec '18

04 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30024 ) Change subject: Documentation: Clarify minor detail on preparing a layout file ...................................................................... Documentation: Clarify minor detail on preparing a layout file The user needs to pass the original firmware image to create a layout file, not the newly compiled coreboot image. Signed-off-by: Michael Bacarella <michael.bacarella(a)gmail.com> Change-Id: If47a88f06076da12d8da7a873c3e5ef64fc1f877 Reviewed-on: https://review.coreboot.org/c/30024 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/flash_tutorial/index.md 1 file changed, 3 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/Documentation/flash_tutorial/index.md b/Documentation/flash_tutorial/index.md index 1a29137..eb74ad0 100644 --- a/Documentation/flash_tutorial/index.md +++ b/Documentation/flash_tutorial/index.md @@ -68,10 +68,11 @@ to write only a part of the flash IC. On Intel for example there are IFD, ME and GBE which don't need to be updated to install coreboot. To make [flashrom] only write the *bios* region, leaving Intel ME and Intel IFD -untouched, you can use a layout file, which can be created using ifdtool +untouched, you can use a layout file, which can be created with ifdtool and a backup +of the original firmware. ```bash -ifdtool -f rom.layout coreboot.rom +ifdtool -f rom.layout backup.rom ``` and looks similar to: -- To view, visit https://review.coreboot.org/c/coreboot/+/30024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If47a88f06076da12d8da7a873c3e5ef64fc1f877 Gerrit-Change-Number: 30024 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Bacarella <michael.bacarella(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: Documentation: Clarify minor detail on preparing a layout file
by Patrick Georgi (Code Review) 04 Dec '18

04 Dec '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30024 ) Change subject: Documentation: Clarify minor detail on preparing a layout file ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If47a88f06076da12d8da7a873c3e5ef64fc1f877 Gerrit-Change-Number: 30024 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Bacarella <michael.bacarella(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 04 Dec 2018 10:25:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2018