coreboot-gerrit December 2018

coreboot-gerrit@coreboot.org

1 participants
1832 discussions

Change in ...coreboot[master]: mainboard/lenovo/t430s: Add ThinkPad T431s as a variant
by build bot (Jenkins) (Code Review) 04 Dec '18

04 Dec '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30021 ) Change subject: mainboard/lenovo/t430s: Add ThinkPad T431s as a variant ...................................................................... Patch Set 6: (6 comments) https://review.coreboot.org/#/c/30021/6/src/mainboard/lenovo/t430s/variants… File src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c: https://review.coreboot.org/#/c/30021/6/src/mainboard/lenovo/t430s/variants… PS6, Line 92: combo Jack code indent should use tabs where possible https://review.coreboot.org/#/c/30021/6/src/mainboard/lenovo/t430s/variants… PS6, Line 93: Master Port - Port B used for Jack Presence Detect code indent should use tabs where possible https://review.coreboot.org/#/c/30021/6/src/mainboard/lenovo/t430s/variants… PS6, Line 94: Enable Combo Jack Detection */ code indent should use tabs where possible https://review.coreboot.org/#/c/30021/6/src/mainboard/lenovo/t430s/variants… PS6, Line 124: 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ line over 80 characters https://review.coreboot.org/#/c/30021/6/src/mainboard/lenovo/t430s/variants… File src/mainboard/lenovo/t430s/variants/t430s/romstage.c: https://review.coreboot.org/#/c/30021/6/src/mainboard/lenovo/t430s/variants… PS6, Line 57: void mainboard_get_spd(spd_raw_data *spd, bool id_only) { open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/30021/6/src/mainboard/lenovo/t430s/variants… PS6, Line 62: void mainboard_early_init(int s3resume) { open brace '{' following function definitions go on the next line -- To view, visit https://review.coreboot.org/c/coreboot/+/30021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a Gerrit-Change-Number: 30021 Gerrit-PatchSet: 6 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Tue, 04 Dec 2018 07:38:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mainboard/lenovo/t430s: Add ThinkPad T431s as a variant
by Bill XIE (Code Review) 04 Dec '18

04 Dec '18

Hello Alexander Couzens, Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30021 to look at the new patch set (#6). Change subject: mainboard/lenovo/t430s: Add ThinkPad T431s as a variant ...................................................................... mainboard/lenovo/t430s: Add ThinkPad T431s as a variant The code is based on autoport and that for T430s Tested: - CPU i5-3337U - Slotted DIMM 2GiB - Soldered RAM 4GiB from samsung (There may be more models here) - Camera - pci-e and usb2 on M.2 slot with A key for wlan - sata and usb2 (no superspeed components) on M.2 slot with B key for wwan - On board SDHCI connected to pci-e - USB3 ports - libgfxinit-based graphic init - NVRAM options for North and South bridges - Sound - Thinkpad EC - S3 - TPM1 on LPC - EHCI debug on SSP2 (USB3 port on the left) - Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from Linux payload (Heads), Seabios may also work. Not tested: - Fingerprint reader on USB2 (not present on mine) - Keyboard backlight (not present on mine) - "sticky_fn" flag in nvram Not implemented yet: - Fn locking in nvram (may not be identical to "sticky_fn") - C-based native graphic init (since T431s has eDP instead of LVDS) - Detecting the model of Soldered RAM at runtime, and loading the corresponding SPD datum (3 observed) from CBFS (the mechanism may be similar to that on x1_carbon_gen1 and s230u, but I do not know how to find gpio ports for that, and SPD data stored in vendor firmware.) Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a Signed-off-by: Bill XIE <persmule(a)gmail.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/t431s.md A Documentation/mainboard/lenovo/t431s_bc_removed.jpg A Documentation/mainboard/lenovo/t431s_flash_chip.jpg A Documentation/mainboard/lenovo/t431s_programming.jpg M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t430s/Kconfig.name M src/mainboard/lenovo/t430s/Makefile.inc M src/mainboard/lenovo/t430s/board_info.txt M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t430s/hda_verb.c M src/mainboard/lenovo/t430s/romstage.c M src/mainboard/lenovo/t430s/smihandler.c A src/mainboard/lenovo/t430s/variants/t430s/board_info.txt R src/mainboard/lenovo/t430s/variants/t430s/gpio.c A src/mainboard/lenovo/t430s/variants/t430s/hda_verb.c A src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb A src/mainboard/lenovo/t430s/variants/t430s/romstage.c A src/mainboard/lenovo/t430s/variants/t430s/smihandler.c A src/mainboard/lenovo/t430s/variants/t431s/board_info.txt A src/mainboard/lenovo/t430s/variants/t431s/gpio.c A src/mainboard/lenovo/t430s/variants/t431s/hda_verb.c A src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb A src/mainboard/lenovo/t430s/variants/t431s/romstage.c A src/mainboard/lenovo/t430s/variants/t431s/smihandler.c A src/mainboard/lenovo/t430s/variants/t431s/spd/Makefile.inc A src/mainboard/lenovo/t430s/variants/t431s/spd/samsung_4gb.spd.hex 27 files changed, 865 insertions(+), 219 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/30021/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/30021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8062cacf5e8232405bb5757e1b1d063541f354a Gerrit-Change-Number: 30021 Gerrit-PatchSet: 6 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: [TESTME]soc/intel/fsp_baytrail: Implement postcar stage
by Werner Zeh (Code Review) 04 Dec '18

04 Dec '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29909 ) Change subject: [TESTME]soc/intel/fsp_baytrail: Implement postcar stage ...................................................................... Patch Set 2: Code-Review-1 Board does not boot at all. Could be a similar issue as fsp_broadwell_de but I have not investigated it further to be sure. Let me know if I can do further tests. -- To view, visit https://review.coreboot.org/c/coreboot/+/29909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I692bbffe9c37367430191266023ce4e2cf1342a9 Gerrit-Change-Number: 29909 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 04 Dec 2018 07:18:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/opencellular/elgon: Enable write protection
by Philipp Deppenwiese (Code Review) 04 Dec '18

04 Dec '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29532 ) Change subject: mb/opencellular/elgon: Enable write protection ...................................................................... mb/opencellular/elgon: Enable write protection * Verify the flash write protection on each boot * Program non-volatile write protection on first boot Tested using I715791b8ae5d1db1ef587321ae5c9daa10eb7dbc. The bootblock is write-protected as long as the #WP pin is asserted low: * Reprogramming of the status register fails. * Trying to write to WP_RO region fails. Programming the WP_RO is only possible if #WP pin is high. Change-Id: I6a940c69ecb1dfd9704b2101c263570bebc5540e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/29532 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/mainboard/opencellular/elgon/bootblock.c 1 file changed, 44 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/src/mainboard/opencellular/elgon/bootblock.c b/src/mainboard/opencellular/elgon/bootblock.c index e6109f1..9dfd1b8 100644 --- a/src/mainboard/opencellular/elgon/bootblock.c +++ b/src/mainboard/opencellular/elgon/bootblock.c @@ -18,6 +18,9 @@ #include <soc/spi.h> #include <soc/uart.h> #include <soc/gpio.h> +#include <spi_flash.h> +#include <console/console.h> +#include <fmap.h> #include "mainboard.h" void bootblock_mainboard_early_init(void) @@ -49,8 +52,48 @@ gpio_output(ELGON_GPIO_SPI_MUX, 1); } +/** + * Handle flash write protection. + * This code verifies the write-protection on each boot. + * Enabling the write protection does only run on the first boot. + * An error is fatal as it breaks the Chain Of Trust. + */ +static void protect_ro_rgn_spi_flash(void) +{ + const struct spi_flash *flash = boot_device_spi_flash(); + const char *fmapname = "WP_RO"; + struct region ro_rgn; + + if (fmap_locate_area(fmapname, &ro_rgn)) { + printk(BIOS_ERR, "%s: No %s FMAP section.\n", __func__, + fmapname); + die("Can't verify flash protections!"); + } + + u8 reg8 = 0; + spi_flash_status(flash, &reg8); + + /* Check if SRP0 is set and RO region is protected */ + if (!(reg8 & 0x80) || + spi_flash_is_write_protected(flash, &ro_rgn) != 1) { + printk(BIOS_WARNING, "%s: FMAP section %s is not write-protected\n", + __func__, fmapname); + + /* + * Need to protect flash region : + * WP_RO read only and use /WP pin + * non-volatile programming + */ + if (spi_flash_set_write_protected(flash, &ro_rgn, 1, + SPI_WRITE_PROTECTION_PIN) != 0) + die("Failed to write-protect WP_RO region!"); + } + printk(BIOS_INFO, "%s: FMAP section %s is write-protected\n", + __func__, fmapname); +} + void bootblock_mainboard_init(void) { configure_spi_flash(); - // FIXME: Check SPI flash WP bits + protect_ro_rgn_spi_flash(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/29532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a940c69ecb1dfd9704b2101c263570bebc5540e Gerrit-Change-Number: 29532 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: drivers/spi/winbond: Fix TB bit
by Philipp Deppenwiese (Code Review) 04 Dec '18

04 Dec '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30014 ) Change subject: drivers/spi/winbond: Fix TB bit ...................................................................... drivers/spi/winbond: Fix TB bit The TB has to be inverted to actually protected the correct region. Tested on elgon using I67eb4ee8e0ad297a8d1984d55102146688c291fc. Change-Id: I715791b8ae5d1db1ef587321ae5c9daa10eb7dbc Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/30014 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/drivers/spi/winbond.c 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified David Hendricks: Looks good to me, approved Philipp Deppenwiese: Looks good to me, approved Julius Werner: Looks good to me, approved diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 9eb3352..f8ea247 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -303,7 +303,7 @@ tb = !tb; } - out->offset = tb ? flash_size - protected_size : 0; + out->offset = tb ? 0 : flash_size - protected_size; out->size = protected_size; } @@ -519,9 +519,9 @@ wp_region = *region; if (region_offset(&wp_region) == 0) - tb = 0; - else tb = 1; + else + tb = 0; if (region_sz(&wp_region) > flash->size / 2) { cmp = 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/30014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I715791b8ae5d1db1ef587321ae5c9daa10eb7dbc Gerrit-Change-Number: 30014 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: libpayload: Remove purin/cygnus
by Philipp Deppenwiese (Code Review) 04 Dec '18

04 Dec '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30029 ) Change subject: libpayload: Remove purin/cygnus ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I589ca7f1a3b479f1c2b1b668a175a71583441ac9 Gerrit-Change-Number: 30029 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 04 Dec 2018 07:10:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: Documentation/mainboard/lenovo/t420.md: add pic of chip
by Angel Pons (Code Review) 04 Dec '18

04 Dec '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30027 ) Change subject: Documentation/mainboard/lenovo/t420.md: add pic of chip ...................................................................... Patch Set 1: Code-Review+1 IMHO, it's worth to mention that GND is connected to various points such as mounting holes and connector shells. That way, to know where GND is on the chip, one could just measure the resistance from the pins to GND with an ohmeter. The correct pin would show minimal resistance. Other than that, and what Patrick mentioned, this looks good to me. (other than my OCD complaining about how dirty the mainboard is :P) -- To view, visit https://review.coreboot.org/c/coreboot/+/30027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9046fa63dcd4d192836417efac68ca7587ac1c91 Gerrit-Change-Number: 30027 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Bacarella <michael.bacarella(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 04 Dec 2018 07:08:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: Documentation/flash_tutorial/index.md: warn about dots painted on ICs
by Angel Pons (Code Review) 04 Dec '18

04 Dec '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30028 ) Change subject: Documentation/flash_tutorial/index.md: warn about dots painted on ICs ...................................................................... Patch Set 1: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/30028/1/Documentation/flash_tutorial/index.… File Documentation/flash_tutorial/index.md: https://review.coreboot.org/#/c/30028/1/Documentation/flash_tutorial/index.… PS1, Line 66: Although you may find dots on data sheet diagrams, they often do not correspond to dots painted on the flash IC. I believe there is an 80-character limit in documentation files. Please adjust this. -- To view, visit https://review.coreboot.org/c/coreboot/+/30028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib634589aaa11f75bde2ef2e13d2cacc4cae19a3f Gerrit-Change-Number: 30028 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Bacarella <michael.bacarella(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 04 Dec 2018 07:01:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: libpayload: Remove purin/cygnus
by Angel Pons (Code Review) 04 Dec '18

04 Dec '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30029 ) Change subject: libpayload: Remove purin/cygnus ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/30029/1/payloads/libpayload/drivers/timer/K… File payloads/libpayload/drivers/timer/Kconfig: https://review.coreboot.org/#/c/30029/1/payloads/libpayload/drivers/timer/K… PS1, Line 87: : : : : I thought this doesn't exist? CB:27965 -- To view, visit https://review.coreboot.org/c/coreboot/+/30029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I589ca7f1a3b479f1c2b1b668a175a71583441ac9 Gerrit-Change-Number: 30029 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 04 Dec 2018 06:57:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: [TESTME]soc/intel/fsp_broadwell_de: Implement postcar stage
by Werner Zeh (Code Review) 04 Dec '18

04 Dec '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29908 ) Change subject: [TESTME]soc/intel/fsp_broadwell_de: Implement postcar stage ...................................................................... Patch Set 2: Code-Review-1 This patch leads to a non booting board. It hangs somewhere in imd_create_empty() which is called form romstage_main_continue() by the line cbmem_was_initted = !cbmem_recovery(0); in romstage.c (last postcode is 0x4d). I haven't dug that deep due to time constraints but it looks like the cache-as-ram memory space is not available anymore (which is the case for broadwell-de in romstage_main_continue) while it is still used by the cbmem-code. Let me know if you need further tests. -- To view, visit https://review.coreboot.org/c/coreboot/+/29908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic31702514cf84e3480b622c28cd2857e613869d9 Gerrit-Change-Number: 29908 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 04 Dec 2018 06:36:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit December 2018