coreboot-gerrit December 2018

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: Documentation: Clarify workflow for cloning coreboot from Gerrit.
by Patrick Georgi (Code Review) 04 Dec '18

04 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30025 ) Change subject: Documentation: Clarify workflow for cloning coreboot from Gerrit. ...................................................................... Documentation: Clarify workflow for cloning coreboot from Gerrit. Documentation that was there seems to reference and older version. Signed-off-by: Michael Bacarella <michael.bacarella(a)gmail.com> Change-Id: I3709613ae065153123d00801ea1b4ff86b100264 Reviewed-on: https://review.coreboot.org/c/30025 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/lessons/lesson2.md 1 file changed, 7 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/Documentation/lessons/lesson2.md b/Documentation/lessons/lesson2.md index 2693bac..a95dd80 100644 --- a/Documentation/lessons/lesson2.md +++ b/Documentation/lessons/lesson2.md @@ -60,12 +60,13 @@ ## Part 3: Clone coreboot and configure it for submitting patches -Go to the **Projects** tab in the upper left corner and select **List**. -From the dropdown menu that appears, select "coreboot". +On Gerrit, click on the **Browse** tab in the upper left corner and select +**Repositories**. From the listing, select the "coreboot" repo. You may have +to click the next page arrow at the bottom a few times to find it. -If you are using SSH keys, select **ssh** from the tabs under "Project coreboot" -and run the command that appears. This should prompt you for your id_rsa passphrase, -if you previously set one. +If you are using SSH keys, select **ssh** from the tabs under "Project +coreboot" and run the clone with commit-msg hook command that's provided. This +should prompt you for your id_rsa passphrase, if you previously set one. If you are using HTTP, instead, select **http** from the tabs under "Project coreboot" and run the command that appears @@ -278,4 +279,4 @@ command in your coreboot repository. Now, the last commit should be the most recent commit to that patch; to update it, make your desired changes, stage the files, then amend and push the commit using the instructions in the above -paragraph. \ No newline at end of file +paragraph. -- To view, visit https://review.coreboot.org/c/coreboot/+/30025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3709613ae065153123d00801ea1b4ff86b100264 Gerrit-Change-Number: 30025 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Bacarella <michael.bacarella(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: Documentation: Clarify workflow for cloning coreboot from Gerrit.
by Patrick Georgi (Code Review) 04 Dec '18

04 Dec '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30025 ) Change subject: Documentation: Clarify workflow for cloning coreboot from Gerrit. ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3709613ae065153123d00801ea1b4ff86b100264 Gerrit-Change-Number: 30025 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Bacarella <michael.bacarella(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 04 Dec 2018 10:24:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: Documentation: s/My/Your/ in getting started with Gerrit docs
by Patrick Georgi (Code Review) 04 Dec '18

04 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30026 ) Change subject: Documentation: s/My/Your/ in getting started with Gerrit docs ...................................................................... Documentation: s/My/Your/ in getting started with Gerrit docs Signed-off-by: Michael Bacarella <michael.bacarella(a)gmail.com> Change-Id: I781e2d78c0525da74dd77f572839d746d3eeb3ce Signed-off-by: Michael Bacarella <michael.bacarella(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/30026 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M Documentation/lessons/lesson2.md 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/Documentation/lessons/lesson2.md b/Documentation/lessons/lesson2.md index ec929c8..2693bac 100644 --- a/Documentation/lessons/lesson2.md +++ b/Documentation/lessons/lesson2.md @@ -209,7 +209,7 @@ ## Part 5: Getting your commit reviewed -Your commits can now be seen on review.coreboot.org if you select “My” +Your commits can now be seen on review.coreboot.org if you select “Your” and click on “Changes” and can be reviewed by others. Your code will first be reviewed by build bot (Jenkins), which will either give you a warning or verify a successful build; if so, your commit will receive a +1. Other -- To view, visit https://review.coreboot.org/c/coreboot/+/30026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I781e2d78c0525da74dd77f572839d746d3eeb3ce Gerrit-Change-Number: 30026 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Bacarella <michael.bacarella(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: Documentation: s/My/Your/ in getting started with Gerrit docs
by Patrick Georgi (Code Review) 04 Dec '18

04 Dec '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30026 ) Change subject: Documentation: s/My/Your/ in getting started with Gerrit docs ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I781e2d78c0525da74dd77f572839d746d3eeb3ce Gerrit-Change-Number: 30026 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Bacarella <michael.bacarella(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 04 Dec 2018 10:23:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: ec/google/wilco/acpi: Fix issues and clean up
by Patrick Georgi (Code Review) 04 Dec '18

04 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29760 ) Change subject: ec/google/wilco/acpi: Fix issues and clean up ...................................................................... ec/google/wilco/acpi: Fix issues and clean up - Disable debug output from read/write methods by default - Use argument to _REG to disable SCI when EC is unregistered - Change read/write macros to sync level 2 so they can be called when a mutex is already held - Define some missing events Change-Id: Ic65ebbb6a6151444c47b4aeff7429e186856c49a Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/c/29760 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/google/wilco/acpi/ec.asl M src/ec/google/wilco/acpi/ec_ram.asl 2 files changed, 14 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index cddfe3f..67a698f 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -20,6 +20,7 @@ Name (_UID, 1) Name (_GPE, EC_SCI_GPI) Name (_STA, 0xf) + Name (DBUG, Zero) Name (_CRS, ResourceTemplate() { IO (Decode16, @@ -44,7 +45,7 @@ ECPR = R (APWR) /* Indicate to EC that OS is ready for queries */ - W (ERDY, One) + W (ERDY, Arg1) /* Tell EC to stop emulating PS/2 mouse */ W (PS2M, Zero) @@ -71,7 +72,7 @@ * Arg0 = EC field structure * Arg1 = Value to write */ - Method (ECRW, 2, Serialized) + Method (ECRW, 2, Serialized, 2) { If (!EREG) { Return (Zero) @@ -101,11 +102,15 @@ } Local5 = EBIT (Arg0, Local3) - Printf ("ECRD %o = %o", Local0, Local5) + If (DBUG) { + Printf ("ECRD %o = %o", Local0, Local5) + } Return (Local5) } ElseIf (Local2 == WR) { /* Write byte */ - Printf ("ECWR %o = %o", Local0, Arg1) + If (DBUG) { + Printf ("ECWR %o = %o", Local0, Arg1) + } BYT1 = Arg1 } Return (Zero) @@ -115,7 +120,7 @@ * Read a field from EC * Arg0 = EC field structure */ - Method (R, 1, Serialized) + Method (R, 1, Serialized, 2) { Return (ECRW (Arg0, Zero)) } @@ -125,7 +130,7 @@ * Arg0 = EC field structure * Arg1 = Value to write */ - Method (W, 2, Serialized) + Method (W, 2, Serialized, 2) { Return (ECRW (Arg0, Arg1)) } diff --git a/src/ec/google/wilco/acpi/ec_ram.asl b/src/ec/google/wilco/acpi/ec_ram.asl index e2b6a93..6ea2366 100644 --- a/src/ec/google/wilco/acpi/ec_ram.asl +++ b/src/ec/google/wilco/acpi/ec_ram.asl @@ -81,6 +81,9 @@ Name (WBAT, Package () { 0x09, 0x80, RD }) /* Wake: Low Battery */ Name (EVT3, Package () { 0x0b, 0xff, RD }) /* Event 3 */ +Name (E3CP, Package () { 0x0b, 0x08, RD }) /* CS Power Button */ +Name (E3TH, Package () { 0x0b, 0x10, RD }) /* Thermal Event */ + Name (EVT4, Package () { 0x0c, 0xff, RD }) /* Event 4 */ Name (BCST, Package () { 0x10, 0xff, RD }) /* BCACHE: BST */ -- To view, visit https://review.coreboot.org/c/coreboot/+/29760 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic65ebbb6a6151444c47b4aeff7429e186856c49a Gerrit-Change-Number: 29760 Gerrit-PatchSet: 3 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/intel/cannonlake: Add DPTF ACPI code
by Patrick Georgi (Code Review) 04 Dec '18

04 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29759 ) Change subject: soc/intel/cannonlake: Add DPTF ACPI code ...................................................................... soc/intel/cannonlake: Add DPTF ACPI code Define the constants that DPTF expects from the SOC in order to use the common DPTF ACPI code. For cannonlake this indicates the CPU device is called B0D4 and is at PCI address 00:04.0. Change-Id: I43c2f8dd7281d3e9f791ab01478ee7823fd6b128 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/c/29759 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/soc/intel/cannonlake/acpi/dptf.asl 1 file changed, 45 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/acpi/dptf.asl b/src/soc/intel/cannonlake/acpi/dptf.asl new file mode 100644 index 0000000..098a61c --- /dev/null +++ b/src/soc/intel/cannonlake/acpi/dptf.asl @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_DEVICE B0D4 +#define DPTF_CPU_ADDR 0x00040000 + +#ifndef DPTF_CPU_PASSIVE +#define DPTF_CPU_PASSIVE 80 +#endif + +#ifndef DPTF_CPU_CRITICAL +#define DPTF_CPU_CRITICAL 90 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC0 +#define DPTF_CPU_ACTIVE_AC0 90 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC1 +#define DPTF_CPU_ACTIVE_AC1 80 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC2 +#define DPTF_CPU_ACTIVE_AC2 70 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC3 +#define DPTF_CPU_ACTIVE_AC3 60 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC4 +#define DPTF_CPU_ACTIVE_AC4 50 +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/29759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43c2f8dd7281d3e9f791ab01478ee7823fd6b128 Gerrit-Change-Number: 29759 Gerrit-PatchSet: 3 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/intel/common/dptf: Add method for temp conversion
by Patrick Georgi (Code Review) 04 Dec '18

04 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29758 ) Change subject: soc/intel/common/dptf: Add method for temp conversion ...................................................................... soc/intel/common/dptf: Add method for temp conversion Add a method to convert from 1/10 Kelvin to Celsius. This is useful for EC devices where the sensor temperature are stored in Celsius instead of Kelvin. Change-Id: I6b1154f5ba13416131a029966d6d5c1598904881 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/c/29758 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/acpi/dptf/dptf.asl 1 file changed, 15 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/common/acpi/dptf/dptf.asl b/src/soc/intel/common/acpi/dptf/dptf.asl index beb41e2..1dd57c0 100644 --- a/src/soc/intel/common/acpi/dptf/dptf.asl +++ b/src/soc/intel/common/acpi/dptf/dptf.asl @@ -95,6 +95,21 @@ Return (Local0) } + /* Convert from 1/10 Kelvin to Degrees C for ACPI */ + Method (KTOC, 1) { + If (LLessEqual (Arg0, 2732)) { + Return (0) + } + + /* Convert to Celsius */ + Subtract (Arg0, 2732, Local0) + + /* Convert from 10th of degrees */ + Divide (Local0, 10,, Local0) + + Return (Local0) + } + /* Include Thermal Participants */ #include "thermal.asl" -- To view, visit https://review.coreboot.org/c/coreboot/+/29758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b1154f5ba13416131a029966d6d5c1598904881 Gerrit-Change-Number: 29758 Gerrit-PatchSet: 3 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/intel/common/dptf: Make CPU address a define
by Patrick Georgi (Code Review) 04 Dec '18

04 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29757 ) Change subject: soc/intel/common/dptf: Make CPU address a define ...................................................................... soc/intel/common/dptf: Make CPU address a define In order to support using the common ACPI code on more platforms than just Apollo Lake the DPTF code needs to be told what the PCI address is for the CPU thermal device. Change-Id: I638f2387330bbc42f64eb0fb676ee32c5df6572e Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/c/29757 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/apollolake/acpi/dptf.asl M src/soc/intel/common/acpi/dptf/cpu.asl 2 files changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/apollolake/acpi/dptf.asl b/src/soc/intel/apollolake/acpi/dptf.asl index b9ba9c3..f34725f 100644 --- a/src/soc/intel/apollolake/acpi/dptf.asl +++ b/src/soc/intel/apollolake/acpi/dptf.asl @@ -14,6 +14,7 @@ */ #define DPTF_CPU_DEVICE TCPU +#define DPTF_CPU_ADDR 0x00000001 #ifndef DPTF_CPU_PASSIVE #define DPTF_CPU_PASSIVE 80 diff --git a/src/soc/intel/common/acpi/dptf/cpu.asl b/src/soc/intel/common/acpi/dptf/cpu.asl index c28c0cc..9414e25 100644 --- a/src/soc/intel/common/acpi/dptf/cpu.asl +++ b/src/soc/intel/common/acpi/dptf/cpu.asl @@ -23,7 +23,7 @@ Device (DPTF_CPU_DEVICE) { - Name(_ADR, 0x00000001) + Name(_ADR, DPTF_CPU_ADDR) Method (_STA) { -- To view, visit https://review.coreboot.org/c/coreboot/+/29757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I638f2387330bbc42f64eb0fb676ee32c5df6572e Gerrit-Change-Number: 29757 Gerrit-PatchSet: 3 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: ec/google/wilco: Fix extended event handling
by Patrick Georgi (Code Review) 04 Dec '18

04 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29674 ) Change subject: ec/google/wilco: Fix extended event handling ...................................................................... ec/google/wilco: Fix extended event handling Extended events will be handled by the OS kernel driver, but that driver needs a method exposed by ACPI to read the event data from the EC and into a buffer. Tested by generating a hotkey event and reading the buffer from the Linux kernel driver with acpi_evaluate_object(). Change-Id: Ic8510e38d777a5dd31a5237867313efefeb2b48e Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/c/29674 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/google/wilco/acpi/ec_ram.asl M src/ec/google/wilco/acpi/event.asl 2 files changed, 20 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/ec/google/wilco/acpi/ec_ram.asl b/src/ec/google/wilco/acpi/ec_ram.asl index ffa0c9f..e2b6a93 100644 --- a/src/ec/google/wilco/acpi/ec_ram.asl +++ b/src/ec/google/wilco/acpi/ec_ram.asl @@ -67,7 +67,7 @@ Name (EVT2, Package () { 0x08, 0xff, RD }) /* Event 2 */ Name (E2BS, Package () { 0x08, 0x02, RD }) /* BSS */ Name (E2OR, Package () { 0x08, 0x04, RD }) /* Orientation */ -Name (E2QS, Package () { 0x08, 0x08, RD }) /* Quickset */ +Name (E2QS, Package () { 0x08, 0x08, RD }) /* QS Event */ Name (E2PN, Package () { 0x08, 0x20, RD }) /* Panel */ Name (E2DP, Package () { 0x08, 0x40, RD }) /* Display Port */ Name (E2VT, Package () { 0x08, 0x80, RD }) /* Video Throttle */ @@ -100,8 +100,8 @@ Name (BSDC, Package () { 0x29, 0xff, RD }) /* BSTATIC: Device Chemistry */ Name (BSBS, Package () { 0x2a, 0xff, RD }) /* BSTATIC: Battery String */ -Name (QSEC, Package () { 0x2b, 0xff, RD }) /* QuickSet Event Count */ -Name (QSEB, Package () { 0x2c, 0xff, RD }) /* QuickSet Event Byte */ +Name (QSEC, Package () { 0x2b, 0xff, RD }) /* QS Event Count */ +Name (QSEB, Package () { 0x2c, 0xff, RD }) /* QS Event Byte */ Name (ORST, Package () { 0x39, 0xff, RD }) /* Orientation State */ Name (OREV, Package () { 0x3a, 0xff, RD }) /* Orientation Events */ diff --git a/src/ec/google/wilco/acpi/event.asl b/src/ec/google/wilco/acpi/event.asl index b43086c..4d796b5 100644 --- a/src/ec/google/wilco/acpi/event.asl +++ b/src/ec/google/wilco/acpi/event.asl @@ -76,6 +76,11 @@ Method (ECQ2, 1, Serialized) { Printf ("EVT2: %o", Arg0) + + If (EBIT (E2QS, Arg0)) { + Printf ("QS EVENT") + Notify (^WLCO, 0x90) + } } /* Handle events in PmEv3 */ @@ -90,12 +95,6 @@ Printf ("EVT4: %o", Arg0) } -/* Handle QuickSet events */ -Method (ECQS, 1, Serialized) -{ - Printf ("QS EVENT %o", Arg0) -} - /* Process all events */ Method (_Q66, 0, Serialized) { @@ -118,9 +117,20 @@ If (Local0) { ECQ4 (Local0) } +} +/* Get Event Buffer */ +Method (QSET, 0, Serialized) +{ + /* Get count of event bytes */ Local0 = R (QSEC) + Name (QBUF, Buffer (Local0) {}) + + /* Fill QS event buffer with Local0 bytes */ For (Local1 = 0, Local1 < Local0, Local1++) { - ECQS (R (QSEB)) + QBUF[Local1] = R (QSEB) } + + Printf ("QS = %o", QBUF) + Return (QBUF) } -- To view, visit https://review.coreboot.org/c/coreboot/+/29674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8510e38d777a5dd31a5237867313efefeb2b48e Gerrit-Change-Number: 29674 Gerrit-PatchSet: 4 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: ec/google/wilco: Enable WiFi radio
by Patrick Georgi (Code Review) 04 Dec '18

04 Dec '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29673 ) Change subject: ec/google/wilco: Enable WiFi radio ...................................................................... ec/google/wilco: Enable WiFi radio Add EC command to enable WiFi radio and send that command at startup. Tested to ensure WiFi is functional on a sarien board. Change-Id: Iac46895c7118567e1eb55ea33051a1662103b563 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/c/29673 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/ec/google/wilco/chip.c M src/ec/google/wilco/commands.c M src/ec/google/wilco/commands.h 3 files changed, 26 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index 0cd0048..e1f468d 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -66,6 +66,9 @@ /* Unmute speakers */ wilco_ec_send(KB_HW_MUTE_CONTROL, AUDIO_UNMUTE_125MS); + + /* Enable WiFi radio */ + wilco_ec_radio_control(RADIO_WIFI, 1); } static void wilco_ec_resource(struct device *dev, int index, diff --git a/src/ec/google/wilco/commands.c b/src/ec/google/wilco/commands.c index 1767a01..c42699d 100644 --- a/src/ec/google/wilco/commands.c +++ b/src/ec/google/wilco/commands.c @@ -149,3 +149,12 @@ KB_POWER_OFF, &reason, 1, NULL, 0) < 0) printk(BIOS_ERR, "%s: command failed\n", __func__); } + +int wilco_ec_radio_control(enum ec_radio radio, uint8_t state) +{ + uint8_t radio_control[3] = { 0, radio, state }; + + return wilco_ec_mailbox(WILCO_EC_MSG_DEFAULT, KB_RADIO_CONTROL, + radio_control, ARRAY_SIZE(radio_control), + NULL, 0); +} diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h index 4a19030..0989b20 100644 --- a/src/ec/google/wilco/commands.h +++ b/src/ec/google/wilco/commands.h @@ -26,6 +26,8 @@ KB_POWER_STATUS = 0x05, /* Inform the EC aboout the reason host is turning off */ KB_POWER_OFF = 0x08, + /* Control wireless radios */ + KB_RADIO_CONTROL = 0x2b, /* Save PS/2 data before S3 suspend */ KB_SAVE = 0x2f, /* Restore PS/2 data after S3 resume */ @@ -61,6 +63,18 @@ AUDIO_UNMUTE_125MS, /* Unmute in 125ms */ }; +enum ec_radio { + RADIO_WIFI = 0x02, +}; + +/** + * wilco_ec_radio_control() - Control wireless radios. + * @ec_radio: Wireless radio type. + * @state: Turn radio on or off. + * Return: 0 if successful or negative error code on failure. + */ +int wilco_ec_radio_control(enum ec_radio radio, uint8_t state); + /* * EC Information */ -- To view, visit https://review.coreboot.org/c/coreboot/+/29673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac46895c7118567e1eb55ea33051a1662103b563 Gerrit-Change-Number: 29673 Gerrit-PatchSet: 4 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit December 2018