coreboot-gerrit December 2018

coreboot-gerrit@coreboot.org

1 participants
1832 discussions

Change in ...coreboot[master]: soc/amd/stoneyridge: Name IO061 in ASL appropriately
by Marshall Dawson (Code Review) 04 Dec '18

04 Dec '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30037 Change subject: soc/amd/stoneyridge: Name IO061 in ASL appropriately ...................................................................... soc/amd/stoneyridge: Name IO061 in ASL appropriately AMD traditionally claims the resource at I/O port 61 for the onboard PC-AT speaker. In later designs, the speaker may be omitted in favor of routing the SPKR signal to the codec. Some systems implement neither, and for those it is not correct to identify the resource as a speaker. Modify the EISAID reported to the OS depending on the system design. The default is that port 61 is reported as reserved. In order to report a speaker, add #define in mainboard//dsdt.asl. TEST=check /proc/ioports and iasl -d for both ways using a Grunt BUG=b:117818432 Change-Id: I33aafb187f9fea7b38aae43c399292c7521fcfc4 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/amd/gardenia/dsdt.asl M src/soc/amd/stoneyridge/acpi/lpc.asl 2 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/30037/1 diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl index f190b4e..52bd90b 100644 --- a/src/mainboard/amd/gardenia/dsdt.asl +++ b/src/mainboard/amd/gardenia/dsdt.asl @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#define MAINBOARD_HAS_SPEAKER 1 + /* DefinitionBlock Statement */ #include <arch/acpi.h> DefinitionBlock ( diff --git a/src/soc/amd/stoneyridge/acpi/lpc.asl b/src/soc/amd/stoneyridge/acpi/lpc.asl index a41357a..390d3b6 100644 --- a/src/soc/amd/stoneyridge/acpi/lpc.asl +++ b/src/soc/amd/stoneyridge/acpi/lpc.asl @@ -13,6 +13,12 @@ * GNU General Public License for more details. */ +#if IS_ENABLED(MAINBOARD_HAS_SPEAKER) +#define IO61_HID "PNP0800" /* AT style speaker */ +#else +#define IO61_HID "PNP0C02" /* reserved resource */ +#endif + /* 0:14.3 - LPC */ Device(LPCB) { Name(_ADR, 0x00140003) @@ -66,7 +72,7 @@ } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ Device(SPKR) { /* Speaker */ - Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_HID,EISAID(IO61_HID)) /* AT style speaker */ Name(_CRS, ResourceTemplate() { IO(Decode16, 0x0061, 0x0061, 0, 1) }) -- To view, visit https://review.coreboot.org/c/coreboot/+/30037 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33aafb187f9fea7b38aae43c399292c7521fcfc4 Gerrit-Change-Number: 30037 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: ec/google/wilco: Guard DTPF with ifdef
by Duncan Laurie (Code Review) 04 Dec '18

04 Dec '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30036 Change subject: ec/google/wilco: Guard DTPF with ifdef ...................................................................... ec/google/wilco: Guard DTPF with ifdef There is a dependency issue with the EC DPTF code accessing methods that are external, but once the mainboard includes the relevant code they become internal and the current version of IASL used by jenkins will fail to compile it. Until the new IASL is deployed everywhere wrap the EC DPTF code and expect that the mainboard will explicitly enable it. Change-Id: I612ad8f86d424060ca0303d267d7c2915c760173 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/ec/google/wilco/acpi/dptf.asl M src/ec/google/wilco/acpi/ec.asl M src/ec/google/wilco/acpi/event.asl 3 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/30036/1 diff --git a/src/ec/google/wilco/acpi/dptf.asl b/src/ec/google/wilco/acpi/dptf.asl index f5545d0..0f1663f 100644 --- a/src/ec/google/wilco/acpi/dptf.asl +++ b/src/ec/google/wilco/acpi/dptf.asl @@ -18,10 +18,6 @@ * Dynamic Platform Thermal Framework support */ -External (\_SB.DPTF.CTOK, MethodObj) -External (\_SB.DPTF.KTOC, MethodObj) -External (\_SB.DPTF.TEVT, MethodObj) - /* Mutex for EC PAT interface */ Mutex (PATM, 1) diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index ff8fccc..f9b16b5 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -147,5 +147,7 @@ #include "event.asl" #include "lid.asl" #include "platform.asl" +#ifdef EC_ENABLE_DPTF #include "dptf.asl" +#endif } diff --git a/src/ec/google/wilco/acpi/event.asl b/src/ec/google/wilco/acpi/event.asl index 21721f2..4a3394f 100644 --- a/src/ec/google/wilco/acpi/event.asl +++ b/src/ec/google/wilco/acpi/event.asl @@ -88,10 +88,12 @@ { Printf ("EVT3: %o", Arg0) +#ifdef EC_ENABLE_DPTF /* Theraml Events */ If (EBIT (E3TH, Arg0)) { ^PATX () } +#endif } /* Handle events in PmEv4 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I612ad8f86d424060ca0303d267d7c2915c760173 Gerrit-Change-Number: 30036 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mb/google/sarien: Enable DPTF
by Duncan Laurie (Code Review) 04 Dec '18

04 Dec '18

Hello build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29762 to look at the new patch set (#5). Change subject: mb/google/sarien: Enable DPTF ...................................................................... mb/google/sarien: Enable DPTF Enable DPTF support for sarien/arcada boards. This is currently using placeholder values that are identical that will be updated after thermal tuning is done. Change-Id: I7d51c3b38068fc25927c8dafc0bd9069b29d77f5 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/dsdt.asl M src/mainboard/google/sarien/variants/arcada/devicetree.cb A src/mainboard/google/sarien/variants/arcada/include/variant/acpi/dptf.asl M src/mainboard/google/sarien/variants/arcada/include/variant/ec.h M src/mainboard/google/sarien/variants/sarien/devicetree.cb A src/mainboard/google/sarien/variants/sarien/include/variant/acpi/dptf.asl M src/mainboard/google/sarien/variants/sarien/include/variant/ec.h 7 files changed, 137 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/29762/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/29762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d51c3b38068fc25927c8dafc0bd9069b29d77f5 Gerrit-Change-Number: 29762 Gerrit-PatchSet: 5 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: Documentation/mainboard/lenovo/t420.md: add pic of chip
by Michael Bacarella (Code Review) 04 Dec '18

04 Dec '18

Michael Bacarella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30035 Change subject: Documentation/mainboard/lenovo/t420.md: add pic of chip ...................................................................... Documentation/mainboard/lenovo/t420.md: add pic of chip Provide pic of the flash IC with pinouts labeled, as well as additional text about the chip. Signed-off-by: Michael Bacarella <michael.bacarella(a)gmail.com> Change-Id: I22a424db580abbcf3298b3f41baaab1fa422720f --- M Documentation/mainboard/lenovo/t420.md A Documentation/mainboard/lenovo/t420_chip_location.jpg D Documentation/mainboard/lenovo/t420_chip_location.png 3 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/30035/1 diff --git a/Documentation/mainboard/lenovo/t420.md b/Documentation/mainboard/lenovo/t420.md index 9516a4c..6ebff0e 100644 --- a/Documentation/mainboard/lenovo/t420.md +++ b/Documentation/mainboard/lenovo/t420.md @@ -7,7 +7,7 @@ Below is a picture of IC on the mainboard, with the pinouts labeled. -[t420_chip_location]: t420_chip_location.png +[t420_chip_location]: t420_chip_location.jpg The chip will either be a Macronix MX25L6404E (shown above) or a Winbond W25Q64CVSIG. Do not rely on dots painted in the corner of the chip (such as diff --git a/Documentation/mainboard/lenovo/t420_chip_location.jpg b/Documentation/mainboard/lenovo/t420_chip_location.jpg new file mode 100644 index 0000000..e385165 --- /dev/null +++ b/Documentation/mainboard/lenovo/t420_chip_location.jpg Binary files differ diff --git a/Documentation/mainboard/lenovo/t420_chip_location.png b/Documentation/mainboard/lenovo/t420_chip_location.png deleted file mode 100644 index b9172ac..0000000 --- a/Documentation/mainboard/lenovo/t420_chip_location.png +++ /dev/null Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/30035 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22a424db580abbcf3298b3f41baaab1fa422720f Gerrit-Change-Number: 30035 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Bacarella <michael.bacarella(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: mb/google/sarien: Enable DPTF
by Duncan Laurie (Code Review) 04 Dec '18

04 Dec '18

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29762 ) Change subject: mb/google/sarien: Enable DPTF ...................................................................... Patch Set 4: Need the updated iasl again.. I guess I need to isolate the DPTF code with a Kconfig instead. -- To view, visit https://review.coreboot.org/c/coreboot/+/29762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d51c3b38068fc25927c8dafc0bd9069b29d77f5 Gerrit-Change-Number: 29762 Gerrit-PatchSet: 4 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 04 Dec 2018 17:36:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: ec/google/wilco/acpi: Add DPTF support
by Duncan Laurie (Code Review) 04 Dec '18

04 Dec '18

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29761 ) Change subject: ec/google/wilco/acpi: Add DPTF support ...................................................................... ec/google/wilco/acpi: Add DPTF support Add the support needed for DPTF. This includes the methods to write trip point values, read temperatures, and handle events. This was tested on a sarien board by inspecting AML debug output with the kernel while monitoring temperatures and trip points in sysfs and controlling temperatures with a fan to ensure that when a trip point is crossed an SCI is generated and the event is handled properly. Change-Id: I8d8570d176c0896fa709a6c782b319f58d3c1e52 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/c/29761 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/ec/google/wilco/acpi/dptf.asl M src/ec/google/wilco/acpi/ec.asl M src/ec/google/wilco/acpi/ec_ram.asl M src/ec/google/wilco/acpi/event.asl 4 files changed, 159 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/ec/google/wilco/acpi/dptf.asl b/src/ec/google/wilco/acpi/dptf.asl new file mode 100644 index 0000000..f5545d0 --- /dev/null +++ b/src/ec/google/wilco/acpi/dptf.asl @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Dynamic Platform Thermal Framework support + */ + +External (\_SB.DPTF.CTOK, MethodObj) +External (\_SB.DPTF.KTOC, MethodObj) +External (\_SB.DPTF.TEVT, MethodObj) + +/* Mutex for EC PAT interface */ +Mutex (PATM, 1) + +/* Read requested temperature sensor */ +Method (TSRD, 1, Serialized) +{ + If (Acquire (^PATM, 1000)) { + Return (0) + } + + /* Set sensor ID */ + W (DWTI, ToInteger (Arg0)) + + Local0 = R (DRTV) + + Release (^PATM) + Return (\_SB.DPTF.CTOK (Local0)) +} + +/* + * Set Aux Trip Point 0 + * Arg0 = Temp Sensor ID + * Arg1 = Value to set + */ +Method (PAT0, 2, Serialized) +{ + If (Acquire (^PATM, 1000)) { + Return (0) + } + + /* Set sensor ID */ + W (DWTI, ToInteger (Arg0)) + + /* Set LOW trip point for this sensor */ + W (DWTL, \_SB.DPTF.KTOC (Arg1)) + + Release (^PATM) + Return (1) +} + +/* + * Set Aux Trip Point 1 + * Arg0 = Temp Sensor ID + * Arg1 = Value to set + */ +Method (PAT1, 2, Serialized) +{ + If (Acquire (^PATM, 1000)) { + Return (0) + } + + /* Set sensor ID */ + W (DWTI, ToInteger (Arg0)) + + /* Set HIGH trip point for this sensor */ + W (DWTH, \_SB.DPTF.KTOC (Arg1)) + + Release (^PATM) + Return (1) +} + +/* + * Disable Aux Trip Points + * Arg0 = Temp Sensor ID + */ +Method (PATD, 1, Serialized) +{ + If (Acquire (^PATM, 1000)) { + Return (0) + } + + /* Set sensor ID */ + W (DWTI, ToInteger (Arg0)) + + /* Disable LOW and HIGH trip points */ + W (DWTL, 0xff) + W (DWTH, 0xff) + + Release (^PATM) + Return (1) +} + +/* + * Handle sensor trip events + */ +Method (PATX, 0, Serialized) +{ + Local0 = R (DRTQ) + Local1 = Local0 + + Printf ("Sensor trip mask: %o", Local0) + + If (LNot (Acquire (^PATM, 1000))) { + + /* Handle bits that are set */ + While (FindSetRightBit (Local1, Local2)) + { + /* DPTF will Notify sensor devices */ + \_SB.DPTF.TEVT (Local2) + + /* Clear current sensor number */ + Local1 &= ~(1 << (Local2 - 1)) + } + + Release (^PATM) + } + + /* Clear sensor events */ + W (DWTQ, Local0) +} diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index 67a698f..ff8fccc 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -49,6 +49,11 @@ /* Tell EC to stop emulating PS/2 mouse */ W (PS2M, Zero) + + /* Enable DPTF support if enabled in devicetree */ + If (\DPTE == One) { + W (DWST, Arg1) + } } /* @@ -142,4 +147,5 @@ #include "event.asl" #include "lid.asl" #include "platform.asl" + #include "dptf.asl" } diff --git a/src/ec/google/wilco/acpi/ec_ram.asl b/src/ec/google/wilco/acpi/ec_ram.asl index 6ea2366..1563a3c 100644 --- a/src/ec/google/wilco/acpi/ec_ram.asl +++ b/src/ec/google/wilco/acpi/ec_ram.asl @@ -106,6 +106,14 @@ Name (QSEC, Package () { 0x2b, 0xff, RD }) /* QS Event Count */ Name (QSEB, Package () { 0x2c, 0xff, RD }) /* QS Event Byte */ +Name (DRST, Package () { 0x32, 0xff, RD }) /* DPTF: Read State */ +Name (DRTI, Package () { 0x33, 0xff, RD }) /* DPTF: Read Thermal Index */ +Name (DRTV, Package () { 0x34, 0xff, RD }) /* DPTF: Read Thermal Value */ +Name (DRTL, Package () { 0x35, 0xff, RD }) /* DPTF: Read Trip Low */ +Name (DRTH, Package () { 0x36, 0xff, RD }) /* DPTF: Read Trip High */ +Name (DRHY, Package () { 0x37, 0xff, RD }) /* DPTF: Read Hysteresis */ +Name (DRTQ, Package () { 0x38, 0xff, RD }) /* DPTF: Read Trip Query */ + Name (ORST, Package () { 0x39, 0xff, RD }) /* Orientation State */ Name (OREV, Package () { 0x3a, 0xff, RD }) /* Orientation Events */ Name (OECH, Package () { 0x3a, 0x01, RD }) /* Event: Orientation */ @@ -128,3 +136,9 @@ Name (ERDY, Package () { 0x05, 0xff, WR }) /* EC Ready */ Name (FWAK, Package () { 0x06, 0xff, WR }) /* EC _WAK */ Name (PS2M, Package () { 0x20, 0xff, WR }) /* EC PS/2 Mouse Emulation */ +Name (DWST, Package () { 0x32, 0xff, WR }) /* DPTF: Write State */ +Name (DWTI, Package () { 0x33, 0xff, WR }) /* DPTF: Write Thermal Index */ +Name (DWTL, Package () { 0x35, 0xff, WR }) /* DPTF: Write Trip Low */ +Name (DWTH, Package () { 0x36, 0xff, WR }) /* DPTF: Write Trip High */ +Name (DWHY, Package () { 0x37, 0xff, WR }) /* DPTF: Write Hysteresis */ +Name (DWTQ, Package () { 0x38, 0xff, WR }) /* DPTF: Write Trip Query */ diff --git a/src/ec/google/wilco/acpi/event.asl b/src/ec/google/wilco/acpi/event.asl index 4d796b5..21721f2 100644 --- a/src/ec/google/wilco/acpi/event.asl +++ b/src/ec/google/wilco/acpi/event.asl @@ -87,6 +87,11 @@ Method (ECQ3, 1, Serialized) { Printf ("EVT3: %o", Arg0) + + /* Theraml Events */ + If (EBIT (E3TH, Arg0)) { + ^PATX () + } } /* Handle events in PmEv4 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/29761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d8570d176c0896fa709a6c782b319f58d3c1e52 Gerrit-Change-Number: 29761 Gerrit-PatchSet: 5 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: mb/google/sarien: Enable ISH
by Jett Rink (Code Review) 04 Dec '18

04 Dec '18

Jett Rink has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30034 Change subject: mb/google/sarien: Enable ISH ...................................................................... mb/google/sarien: Enable ISH Turn on the ISH in the device tree. BUG=b:120295222 Change-Id: I0ba08c245d050aebc6eb06055690c422ab9b51c6 Signed-off-by: Jett Rink <jettrink(a)chromium.org> --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/30034/1 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index b33c923..d0b78f7 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -108,6 +108,7 @@ device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 + device pci 13.0 on end # Integrated Sensor Hub device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) chip drivers/intel/wifi -- To view, visit https://review.coreboot.org/c/coreboot/+/30034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ba08c245d050aebc6eb06055690c422ab9b51c6 Gerrit-Change-Number: 30034 Gerrit-PatchSet: 1 Gerrit-Owner: Jett Rink <jettrink(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in ...coreboot[master]: ec/google/wilco/acpi: Add DPTF support
by Furquan Shaikh (Code Review) 04 Dec '18

04 Dec '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29761 ) Change subject: ec/google/wilco/acpi: Add DPTF support ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d8570d176c0896fa709a6c782b319f58d3c1e52 Gerrit-Change-Number: 29761 Gerrit-PatchSet: 4 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 04 Dec 2018 16:59:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: ec/google/wilco/acpi: Add DPTF support
by Duncan Laurie (Code Review) 04 Dec '18

04 Dec '18

Hello build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29761 to look at the new patch set (#4). Change subject: ec/google/wilco/acpi: Add DPTF support ...................................................................... ec/google/wilco/acpi: Add DPTF support Add the support needed for DPTF. This includes the methods to write trip point values, read temperatures, and handle events. This was tested on a sarien board by inspecting AML debug output with the kernel while monitoring temperatures and trip points in sysfs and controlling temperatures with a fan to ensure that when a trip point is crossed an SCI is generated and the event is handled properly. Change-Id: I8d8570d176c0896fa709a6c782b319f58d3c1e52 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- A src/ec/google/wilco/acpi/dptf.asl M src/ec/google/wilco/acpi/ec.asl M src/ec/google/wilco/acpi/ec_ram.asl M src/ec/google/wilco/acpi/event.asl 4 files changed, 159 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/29761/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/29761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d8570d176c0896fa709a6c782b319f58d3c1e52 Gerrit-Change-Number: 29761 Gerrit-PatchSet: 4 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: Documentation/../../kblrvp11: Add RVP11 documentation
by Patrick Rudolph (Code Review) 04 Dec '18

04 Dec '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29859 ) Change subject: Documentation/../../kblrvp11: Add RVP11 documentation ...................................................................... Patch Set 2: Code-Review+1 (3 comments) https://review.coreboot.org/#/c/29859/2/Documentation/mainboard/intel/kblrv… File Documentation/mainboard/intel/kblrvp11.md: https://review.coreboot.org/#/c/29859/2/Documentation/mainboard/intel/kblrv… PS2, Line 48: 1. Dediprog SF600 with adapter B is used. Not everyboard has a dediprog, I'd recommend to just reference https://doc.coreboot.org/flash_tutorial/index.html https://review.coreboot.org/#/c/29859/2/Documentation/mainboard/intel/kblrv… PS2, Line 50: 3. Connect Dediprog SF600 to header at J7H1. That's the important part here. Knowing that there's a programming header compatible to dediprog pinout. https://review.coreboot.org/#/c/29859/2/Documentation/mainboard/intel/kblrv… PS2, Line 52: 5. Go to "file" and select the .rom file (16 MB) to program chip1. That seems to describe some Windows UI ? -- To view, visit https://review.coreboot.org/c/coreboot/+/29859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01509c2fa2c127b77ae72b8b0aaac0f826b0bedd Gerrit-Change-Number: 29859 Gerrit-PatchSet: 2 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 04 Dec 2018 15:34:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2018