coreboot-gerrit December 2018

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Change in ...coreboot[master]: mb/google/sarien: Enable ISH
by Duncan Laurie (Code Review) 04 Dec '18

04 Dec '18

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30034 ) Change subject: mb/google/sarien: Enable ISH ...................................................................... Patch Set 1: I think you'll have to rebase this as I just submitted some changes that affected devicetree.cb -- To view, visit https://review.coreboot.org/c/coreboot/+/30034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ba08c245d050aebc6eb06055690c422ab9b51c6 Gerrit-Change-Number: 30034 Gerrit-PatchSet: 1 Gerrit-Owner: Jett Rink <jettrink(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Jett Rink <jettrink(a)chromium.org> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 04 Dec 2018 22:53:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Enable ISH
by Duncan Laurie (Code Review) 04 Dec '18

04 Dec '18

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30034 ) Change subject: mb/google/sarien: Enable ISH ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ba08c245d050aebc6eb06055690c422ab9b51c6 Gerrit-Change-Number: 30034 Gerrit-PatchSet: 1 Gerrit-Owner: Jett Rink <jettrink(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Jett Rink <jettrink(a)chromium.org> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Tue, 04 Dec 2018 22:53:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/poppy/variant/nocturne: adjust RcompTarget to fix DRAM corr...
by Duncan Laurie (Code Review) 04 Dec '18

04 Dec '18

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29361 ) Change subject: mb/google/poppy/variant/nocturne: adjust RcompTarget to fix DRAM corruption ...................................................................... mb/google/poppy/variant/nocturne: adjust RcompTarget to fix DRAM corruption BUG=b:111812662 TEST=flash to nocturne, boot nocturne, run "memtester 1g" and verify it passes. Change-Id: Iefc3957f915a39a47ad6018459e65b70d1b34091 Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-on: https://review.coreboot.org/c/29361 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/mainboard/google/poppy/variants/nocturne/memory.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Furquan Shaikh: Looks good to me, approved Nick Vaccaro: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/poppy/variants/nocturne/memory.c b/src/mainboard/google/poppy/variants/nocturne/memory.c index 0b34e72..b6c77a3 100644 --- a/src/mainboard/google/poppy/variants/nocturne/memory.c +++ b/src/mainboard/google/poppy/variants/nocturne/memory.c @@ -33,7 +33,7 @@ static const u16 rcomp_resistor[] = { 200, 81, 162 }; /* Rcomp target */ -static const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; +static const u16 rcomp_target[] = { 100, 30, 40, 23, 40 }; void variant_memory_params(struct memory_params *p) { -- To view, visit https://review.coreboot.org/c/coreboot/+/29361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefc3957f915a39a47ad6018459e65b70d1b34091 Gerrit-Change-Number: 29361 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-CC: caveh jalali <caveh(a)chromium.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/poppy/variant/nocturne: adjust RcompTarget to fix DRAM corr...
by Duncan Laurie (Code Review) 04 Dec '18

04 Dec '18

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29361 ) Change subject: mb/google/poppy/variant/nocturne: adjust RcompTarget to fix DRAM corruption ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefc3957f915a39a47ad6018459e65b70d1b34091 Gerrit-Change-Number: 29361 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-CC: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Tue, 04 Dec 2018 22:52:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: Define USB devices for ACPI
by Duncan Laurie (Code Review) 04 Dec '18

04 Dec '18

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30000 ) Change subject: mb/google/sarien: Define USB devices for ACPI ...................................................................... mb/google/sarien: Define USB devices for ACPI Add the USB device information for the sarien/arcada variants. This includes the ACPI _PLD group definitions for the external ports that indicate which USB2 and USB3 ports share the same physical interface. Change-Id: I0b936127954ba09c61ccb871bfc62ee7d99da263 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/c/30000 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/sarien/Kconfig M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 3 files changed, 181 insertions(+), 22 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 9b4696b..c9e4c0b 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -6,6 +6,7 @@ select DRIVERS_I2C_HID select DRIVERS_SPI_ACPI select DRIVERS_PS2_KEYBOARD + select DRIVERS_USB_ACPI select EC_GOOGLE_WILCO select GENERIC_SPD_BIN select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 4bd2d90..f487979 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -33,21 +33,21 @@ register "dptf_enable" = "1" # Intel Common SoC Config - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C - register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Ext USB2 Port 3 - register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Ext USB2 Port 4 + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port + register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Left Type-A Port + register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port register "usb2_ports[3]" = "USB2_PORT_EMPTY" register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WWAN register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # FPR in PB - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 2230 (BT) + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Ext USB3 Port 3 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Ext USB3 Port 4 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 3042 (WWAN) + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Left Type-A Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN register "usb3_ports[4]" = "USB3_PORT_EMPTY" register "usb3_ports[5]" = "USB3_PORT_EMPTY" @@ -109,7 +109,80 @@ device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 - device pci 14.0 on end # USB xHCI + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""USH"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.7 on end + end + chip drivers/usb/acpi + register "desc" = ""Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.8 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.9 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.3 on end + end + end + end + end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) chip drivers/intel/wifi register "wake" = "PME_B0_EN_BIT" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 66f1711..4696d7f 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -33,22 +33,22 @@ register "dptf_enable" = "1" # Intel Common SoC Config - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C - register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Ext USB2 Port 1 Charge - register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Ext USB2 Port 2 - register "usb2_ports[3]" = "USB2_PORT_LONG(OC2)" # Ext USB2 Port 3 + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port + register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Right Type-A Port 1 + register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Left Type-A Port + register "usb2_ports[3]" = "USB2_PORT_LONG(OC2)" # Right Type-A Port 2 register "usb2_ports[4]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WWAN register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # FPR in PB - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 2230 (BT) + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Ext USB3 Port 1 Charge - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Ext USB3 Port 2 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Ext USB3 Port 3 - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 3042 (WWAN) + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Right Type-A Port 1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Left Type-A Port + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)" # Right Type-A Port 2 + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Intel Common SoC Config @@ -109,7 +109,92 @@ device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 - device pci 14.0 on end # USB xHCI + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port 1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port 2"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.5 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.6 on end + end + chip drivers/usb/acpi + register "desc" = ""USH"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.7 on end + end + chip drivers/usb/acpi + register "desc" = ""Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.8 on end + end + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.9 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port 1"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.2 on end + end + chip drivers/usb/acpi + register "desc" = ""Right Type-A Port 2"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 3.4 on end + end + end + end + end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) chip drivers/intel/wifi register "wake" = "PME_B0_EN_BIT" -- To view, visit https://review.coreboot.org/c/coreboot/+/30000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b936127954ba09c61ccb871bfc62ee7d99da263 Gerrit-Change-Number: 30000 Gerrit-PatchSet: 6 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/eve: Define USB port peers
by Duncan Laurie (Code Review) 04 Dec '18

04 Dec '18

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29999 ) Change subject: mb/google/eve: Define USB port peers ...................................................................... mb/google/eve: Define USB port peers Add ACPI _PLD group definitions for the external ports that indicate which USB2 and USB3 ports share the same physical interface. Change-Id: I7f85720a878a3774d453a9adb82518722f7ba23d Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/c/29999 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/eve/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index e0ef3b0..44449a5 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -260,6 +260,7 @@ chip drivers/usb/acpi register "desc" = ""USB2 Type-C Left"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" device usb 2.0 on end end chip drivers/usb/acpi @@ -275,6 +276,7 @@ chip drivers/usb/acpi register "desc" = ""USB2 Type-C Right"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" device usb 2.4 on end end chip drivers/usb/acpi @@ -285,11 +287,13 @@ chip drivers/usb/acpi register "desc" = ""USB3 Type-C Left"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" device usb 3.0 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Right"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" device usb 3.1 on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/29999 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f85720a878a3774d453a9adb82518722f7ba23d Gerrit-Change-Number: 29999 Gerrit-PatchSet: 6 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: acpi_pld: Make it easier to define the ACPI USB device groups
by Duncan Laurie (Code Review) 04 Dec '18

04 Dec '18

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29998 ) Change subject: acpi_pld: Make it easier to define the ACPI USB device groups ...................................................................... acpi_pld: Make it easier to define the ACPI USB device groups The Linux kernel can use the ACPI _PLD group information to determine peer ports. Currently to define the group information the devicetree must provide a complete _PLD structure. This change pulls the group information into a separate structure that can be defined in devicetree. This makes it easier to set for USB devices in devicetree that do not need a full custom PLD. This was tested on a sarien board with the USB devices defined by verifying that the USB 2/3 ports are correctly identified with their peer in sysfs. Change-Id: Ifd4cadf0f6c901eb3832ad4e1395904f99c2f5a0 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/c/29998 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/arch/x86/acpi_pld.c M src/arch/x86/include/arch/acpi_pld.h M src/drivers/usb/acpi/chip.h M src/drivers/usb/acpi/usb_acpi.c 4 files changed, 33 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/arch/x86/acpi_pld.c b/src/arch/x86/acpi_pld.c index d399ea6..904e9f7 100644 --- a/src/arch/x86/acpi_pld.c +++ b/src/arch/x86/acpi_pld.c @@ -18,7 +18,8 @@ #include <arch/acpi.h> #include <arch/acpi_pld.h> -int acpi_pld_fill_usb(struct acpi_pld *pld, enum acpi_upc_type type) +int acpi_pld_fill_usb(struct acpi_pld *pld, enum acpi_upc_type type, + struct acpi_pld_group *group) { if (!pld) return -1; @@ -32,6 +33,8 @@ pld->horizontal_position = PLD_HORIZONTAL_POSITION_CENTER; pld->rotation = PLD_ROTATE_0; pld->visible = 1; + pld->group.token = group->token; + pld->group.position = group->position; /* Set the shape based on port type */ switch (type) { @@ -114,16 +117,16 @@ /* [77:74] Shape */ buf[9] |= (pld->shape & 0xf) << 2; - /* [78] Group Orientation */ - buf[9] |= (pld->group_orientation & 0x1) << 6; + /* [78] Orientation */ + buf[9] |= (pld->orientation & 0x1) << 6; /* [86:79] Group Token (incorrectly defined as 1 bit in ACPI 6.2A) */ - buf[9] |= (pld->group_token & 0x1) << 7; - buf[10] |= (pld->group_token >> 0x1) & 0x7f; + buf[9] |= (pld->group.token & 0x1) << 7; + buf[10] |= (pld->group.token >> 0x1) & 0x7f; /* [94:87] Group Position */ - buf[10] |= (pld->group_position & 0x1) << 7; - buf[11] |= (pld->group_position >> 0x1) & 0x7f; + buf[10] |= (pld->group.position & 0x1) << 7; + buf[11] |= (pld->group.position >> 0x1) & 0x7f; /* [95] Bay */ buf[11] |= (pld->bay & 0x1) << 7; diff --git a/src/arch/x86/include/arch/acpi_pld.h b/src/arch/x86/include/arch/acpi_pld.h index ce279a0..1b4417d 100644 --- a/src/arch/x86/include/arch/acpi_pld.h +++ b/src/arch/x86/include/arch/acpi_pld.h @@ -75,6 +75,17 @@ PLD_ROTATE_315 }; +#define ACPI_PLD_GROUP(__token, __position) \ + { \ + .token = __token, \ + .position = __position, \ + } + +struct acpi_pld_group { + uint8_t token; + uint8_t position; +}; + struct acpi_pld { /* Color field can be explicitly ignored */ bool ignore_color; @@ -100,9 +111,8 @@ enum acpi_pld_rotate rotation; /* Port grouping */ - enum acpi_pld_orientation group_orientation; - uint8_t group_token; - uint8_t group_position; + enum acpi_pld_orientation orientation; + struct acpi_pld_group group; uint8_t draw_order; uint8_t cabinet_number; uint8_t card_cage_number; @@ -112,7 +122,8 @@ }; /* Fill out PLD structure with defaults based on USB port type */ -int acpi_pld_fill_usb(struct acpi_pld *pld, enum acpi_upc_type type); +int acpi_pld_fill_usb(struct acpi_pld *pld, enum acpi_upc_type type, + struct acpi_pld_group *group); /* Turn PLD structure into a 20 byte ACPI buffer */ int acpi_pld_to_buffer(const struct acpi_pld *pld, uint8_t *buf, int buf_len); diff --git a/src/drivers/usb/acpi/chip.h b/src/drivers/usb/acpi/chip.h index 6429f13..512893d 100644 --- a/src/drivers/usb/acpi/chip.h +++ b/src/drivers/usb/acpi/chip.h @@ -46,7 +46,13 @@ */ enum acpi_upc_type type; - /* Define a custom physical location for the port */ + /* Group peer ports */ + struct acpi_pld_group group; + + /* + * Define a custom physical location for the port. + * If enabled, this takes precedence over the 'group' field. + */ bool use_custom_pld; struct acpi_pld custom_pld; diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index f049e68..abc1718 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -57,7 +57,7 @@ } else { /* Fill PLD strucutre based on port type */ struct acpi_pld pld; - acpi_pld_fill_usb(&pld, config->type); + acpi_pld_fill_usb(&pld, config->type, &config->group); acpigen_write_pld(&pld); } -- To view, visit https://review.coreboot.org/c/coreboot/+/29998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd4cadf0f6c901eb3832ad4e1395904f99c2f5a0 Gerrit-Change-Number: 29998 Gerrit-PatchSet: 6 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/intel/cannonlake: Add USB device names
by Duncan Laurie (Code Review) 04 Dec '18

04 Dec '18

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29997 ) Change subject: soc/intel/cannonlake: Add USB device names ...................................................................... soc/intel/cannonlake: Add USB device names Add the ACPI device names for the USB ports to match what is in the DSDT so USB ports can be defined in the SSDT. Change-Id: Ibb323bbd324811fa3178b0cba3d7f0a315169486 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/c/29997 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/cannonlake/chip.c 1 file changed, 37 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index 17b173a..4604d80 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -35,6 +35,43 @@ if (dev->path.type == DEVICE_PATH_DOMAIN) return "PCI0"; + if (dev->path.type == DEVICE_PATH_USB) { + switch (dev->path.usb.port_type) { + case 0: + /* Root Hub */ + return "RHUB"; + case 2: + /* USB2 ports */ + switch (dev->path.usb.port_id) { + case 0: return "HS01"; + case 1: return "HS02"; + case 2: return "HS03"; + case 3: return "HS04"; + case 4: return "HS05"; + case 5: return "HS06"; + case 6: return "HS07"; + case 7: return "HS08"; + case 8: return "HS09"; + case 9: return "HS10"; + case 10: return "HS11"; + case 11: return "HS12"; + } + break; + case 3: + /* USB3 ports */ + switch (dev->path.usb.port_id) { + case 0: return "SS01"; + case 1: return "SS02"; + case 2: return "SS03"; + case 3: return "SS04"; + case 4: return "SS05"; + case 5: return "SS06"; + } + break; + } + return NULL; + } + if (dev->path.type != DEVICE_PATH_PCI) return NULL; -- To view, visit https://review.coreboot.org/c/coreboot/+/29997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb323bbd324811fa3178b0cba3d7f0a315169486 Gerrit-Change-Number: 29997 Gerrit-PatchSet: 5 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/intel/cannonlake: Increase bootblock size
by Duncan Laurie (Code Review) 04 Dec '18

04 Dec '18

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29996 ) Change subject: soc/intel/cannonlake: Increase bootblock size ...................................................................... soc/intel/cannonlake: Increase bootblock size Increase the bootblock size to 48K to match skylake. With UART enabled we are very near the 32K limit, and with upcoming changes to add USB devices in devicetree for a cannonlake board it is over the current 32K limit. Change-Id: I155cb0a6af1746af6833fa9f35c2ea6fe0bc709f Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/c/29996 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 9452b6d..78c6dfe 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -230,7 +230,7 @@ config C_ENV_BOOTBLOCK_SIZE hex - default 0x8000 + default 0xC000 config CBFS_SIZE hex -- To view, visit https://review.coreboot.org/c/coreboot/+/29996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I155cb0a6af1746af6833fa9f35c2ea6fe0bc709f Gerrit-Change-Number: 29996 Gerrit-PatchSet: 5 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: ec/google/wilco: Turn camera power on
by Duncan Laurie (Code Review) 04 Dec '18

04 Dec '18

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29987 ) Change subject: ec/google/wilco: Turn camera power on ...................................................................... ec/google/wilco: Turn camera power on Send the EC command required to turn the camera power on and verify that it shows up on the USB bus. Change-Id: I9e9ba712a11cef85cde91ac21a4b6b5090ef58dc Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Reviewed-on: https://review.coreboot.org/c/29987 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/ec/google/wilco/chip.c M src/ec/google/wilco/commands.h 2 files changed, 10 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index e1f468d..a9caaec 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -69,6 +69,9 @@ /* Enable WiFi radio */ wilco_ec_radio_control(RADIO_WIFI, 1); + + /* Turn on camera power */ + wilco_ec_send(KB_CAMERA, CAMERA_ON); } static void wilco_ec_resource(struct device *dev, int index, diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h index 0989b20..752e19b 100644 --- a/src/ec/google/wilco/commands.h +++ b/src/ec/google/wilco/commands.h @@ -32,6 +32,8 @@ KB_SAVE = 0x2f, /* Restore PS/2 data after S3 resume */ KB_RESTORE = 0x30, + /* Manage the EC control of camera power */ + KB_CAMERA = 0x33, /* Retrieve information about the EC */ KB_EC_INFO = 0x38, /* Set ACPI mode on or off */ @@ -67,6 +69,11 @@ RADIO_WIFI = 0x02, }; +enum ec_camera { + CAMERA_ON = 0, + CAMERA_OFF +}; + /** * wilco_ec_radio_control() - Control wireless radios. * @ec_radio: Wireless radio type. -- To view, visit https://review.coreboot.org/c/coreboot/+/29987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e9ba712a11cef85cde91ac21a4b6b5090ef58dc Gerrit-Change-Number: 29987 Gerrit-PatchSet: 5 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit December 2018