coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

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1699 discussions

Change in coreboot[master]: nb/intel/x4x/raminit: Add missing space
by Patrick Georgi (Code Review) 05 Nov '18

05 Nov '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/29346 ) Change subject: nb/intel/x4x/raminit: Add missing space ...................................................................... Patch Set 2: Code-Review+2 > Patch Set 1: > > Is this tested? printf() does need the space to display properly, but I am not sure about printk(). that has nothing to do with printf vs printk but with string concatenation in C -- To view, visit https://review.coreboot.org/29346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I42033d2f184e424818edf844cf6cf84ea07d7ed5 Gerrit-Change-Number: 29346 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Nov 2018 09:16:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/asus/p5qc: Fix spelling of Marvell
by Patrick Georgi (Code Review) 05 Nov '18

05 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29347 ) Change subject: mb/asus/p5qc: Fix spelling of Marvell ...................................................................... mb/asus/p5qc: Fix spelling of Marvell Marvell is the chip company, Marvel makes comic books. Change-Id: I437ac0d4fc706fbb62a0a74ca74a197dba4499fb Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-on: https://review.coreboot.org/29347 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb M src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb 3 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/asus/p5qc/Kconfig b/src/mainboard/asus/p5qc/Kconfig index e8d596f..75c7c7c 100644 --- a/src/mainboard/asus/p5qc/Kconfig +++ b/src/mainboard/asus/p5qc/Kconfig @@ -53,7 +53,7 @@ int default 4 -# The MARVEL IDE controller delays SeaBIOS a lot and results in an unbootable +# The MARVELL IDE controller delays SeaBIOS a lot and results in an unbootable # bogus disk. Compiling SeaBIOS without ATA support is a workaround. config PAYLOAD_CONFIGFILE diff --git a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb index 8753d4c..d645609 100644 --- a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb @@ -55,7 +55,7 @@ device pci 1c.1 off end # PCIe 2 device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 on end # PCIe 5 MARVEL IDE + device pci 1c.4 on end # PCIe 5 MARVELL IDE device pci 1c.5 on end # PCIe 6 device pci 1d.0 on end # USB device pci 1d.1 on end # USB diff --git a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb index 6fac063..8420124 100644 --- a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb @@ -55,7 +55,7 @@ device pci 1c.1 off end # PCIe 2 device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 on end # PCIe 5 MARVEL IDE + device pci 1c.4 on end # PCIe 5 MARVELL IDE device pci 1c.5 on end # PCIe 6 device pci 1d.0 on end # USB device pci 1d.1 on end # USB -- To view, visit https://review.coreboot.org/29347 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I437ac0d4fc706fbb62a0a74ca74a197dba4499fb Gerrit-Change-Number: 29347 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/sarien: Enable WWAN detection
by Patrick Georgi (Code Review) 05 Nov '18

05 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29430 ) Change subject: mb/google/sarien: Enable WWAN detection ...................................................................... mb/google/sarien: Enable WWAN detection WWAN start-up control requires RESET# assert after FULL_CARD_POWER_OFF# set to high more than 10 ms, so force RESET#(GPP_D21) to low at bootblock stage to match the sequence. BUG=N/A TEST=Boot up Sarien/Arcada board, check WWAN get detected as USB devices through lsusb. Change-Id: I36eb841a2e8f2b36771d20577314a7451fbee133 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Reviewed-on: https://review.coreboot.org/29430 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/mainboard/google/sarien/variants/arcada/gpio.c M src/mainboard/google/sarien/variants/sarien/gpio.c 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index 86da3ec..eb4ee76 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -234,6 +234,8 @@ /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ /* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP, EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ +/* RESET# need to stay low before FULL_CARD_POWER_OFF assert */ +/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */ /* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ /* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */ diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index 3656afb..690af1f 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -234,6 +234,8 @@ /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ /* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, DEEP, EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */ +/* RESET# need to stay low before FULL_CARD_POWER_OFF assert */ +/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */ /* CPU_GP0 */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */ /* SATALED# */ PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY */ /* DDPD_HPD2 */ PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* H1_FLASH_WP */ -- To view, visit https://review.coreboot.org/29430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I36eb841a2e8f2b36771d20577314a7451fbee133 Gerrit-Change-Number: 29430 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/cannonlake: Enable ISH from device
by Patrick Georgi (Code Review) 05 Nov '18

05 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29274 ) Change subject: soc/intel/cannonlake: Enable ISH from device ...................................................................... soc/intel/cannonlake: Enable ISH from device PCH ISH enabled/disabled in FSP memory init UPD, it will be match the setting in ISH device on/off in devicetree.cb. BUG=N/A TEST=Build and pass on whiskey lake rvp platform. Change-Id: I6889634bf65e7ce5cc3e3393c57c86d622f1ac68 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Reviewed-on: https://review.coreboot.org/29274 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Reviewed-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/cannonlake/romstage/fsp_params.c 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Bora Guvendik: Looks good to me, approved Pratikkumar V Prajapati: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 3cfa281..8506214 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -25,6 +25,7 @@ { unsigned int i; uint32_t mask = 0; + const struct device *dev = dev_find_slot(0, PCH_DEVFN_ISH); /* Set IGD stolen size to 64MB. */ m_cfg->IgdDvmt50PreAlloc = 2; @@ -55,6 +56,11 @@ #if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE) m_cfg->SkipMpInit = !chip_get_fsp_mp_init(); #endif + /* If ISH is enabled, enable ISH elements */ + if (!dev) + m_cfg->PchIshEnable = 0; + else + m_cfg->PchIshEnable = dev->enabled; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) -- To view, visit https://review.coreboot.org/29274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I6889634bf65e7ce5cc3e3393c57c86d622f1ac68 Gerrit-Change-Number: 29274 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shine Liu <shine.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: add Nanya memory option
by Patrick Georgi (Code Review) 05 Nov '18

05 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29341 ) Change subject: mb/google/poppy/variant/nocturne: add Nanya memory option ...................................................................... mb/google/poppy/variant/nocturne: add Nanya memory option Add option for Nanya NT6CL256T32CM-H1 part. Add comments to indicate total memory size for convenience. BUG=b:118624505 BRANCH=master TEST=none Change-Id: I82200e7b3d0a13295cb38f53ab576697ff8d302b Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-on: https://review.coreboot.org/29341 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/poppy/variants/nocturne/Makefile.inc 1 file changed, 12 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/poppy/variants/nocturne/Makefile.inc b/src/mainboard/google/poppy/variants/nocturne/Makefile.inc index c282faa..e558cfc 100644 --- a/src/mainboard/google/poppy/variants/nocturne/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nocturne/Makefile.inc @@ -1,17 +1,17 @@ SPD_SOURCES = empty # 0b0000 -SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0001 -SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD # 0b0010 -SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF # 0b0011 -SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR-NUD # 0b0100 -#SPD_SOURCES += samsung_dimm_K4EBE304EB-EGCF # 0b0101 -SPD_SOURCES += samsung_dimm_K4EBE304EB-EGCG # 0b0101 -SPD_SOURCES += hynix_dimm_H9CCNNNCLGALAR-NUD # 0b0110 -SPD_SOURCES += micron_dimm_MT52L512M32D2PF-107 # 0b0111 -SPD_SOURCES += micron_dimm_MT52L1G32D4PG-107 # 0b1000 -SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107 # 0b1001 -SPD_SOURCES += samsung_dimm_K4E6E304EC-EGCF # 0b1010 -SPD_SOURCES += samsung_dimm_K4EBE304EC-EGCF # 0b1011 +SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0001 4GB +SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD # 0b0010 4GB +SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF # 0b0011 8GB +SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR-NUD # 0b0100 8GB +SPD_SOURCES += samsung_dimm_K4EBE304EB-EGCG # 0b0101 16GB +SPD_SOURCES += hynix_dimm_H9CCNNNCLGALAR-NUD # 0b0110 16GB +SPD_SOURCES += micron_dimm_MT52L512M32D2PF-107 # 0b0111 8GB +SPD_SOURCES += micron_dimm_MT52L1G32D4PG-107 # 0b1000 16GB +SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107 # 0b1001 4GB +SPD_SOURCES += samsung_dimm_K4E6E304EC-EGCF # 0b1010 8GB +SPD_SOURCES += samsung_dimm_K4EBE304EC-EGCF # 0b1011 16GB +SPD_SOURCES += nayna_dimm_NT6CL256T32CM-H1 # 0b1100 4GB bootblock-y += gpio.c -- To view, visit https://review.coreboot.org/29341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I82200e7b3d0a13295cb38f53ab576697ff8d302b Gerrit-Change-Number: 29341 Gerrit-PatchSet: 3 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: Linuxboot: gitignore build directory
by Philipp Deppenwiese (Code Review) 05 Nov '18

05 Nov '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/29444 ) Change subject: Linuxboot: gitignore build directory ...................................................................... Linuxboot: gitignore build directory Add the Linuxboot build directory to .gitignore. Change-Id: Ic11311e2de544a334043a55eda42643d9df3374d Signed-off-by: Marcello Sylvester Bauer <info(a)marcellobauer.com> Reviewed-on: https://review.coreboot.org/29444 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M .gitignore 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/.gitignore b/.gitignore index 326fdc1..55735bf 100644 --- a/.gitignore +++ b/.gitignore @@ -16,6 +16,7 @@ payloads/external/depthcharge/depthcharge/ payloads/external/FILO/filo/ payloads/external/GRUB2/grub2/ +payloads/external/LinuxBoot/linuxboot/ payloads/external/SeaBIOS/seabios/ payloads/external/tianocore/tianocore/ payloads/external/tint/tint/ -- To view, visit https://review.coreboot.org/29444 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ic11311e2de544a334043a55eda42643d9df3374d Gerrit-Change-Number: 29444 Gerrit-PatchSet: 4 Gerrit-Owner: Marcello Sylvester Bauer <info(a)marcellobauer.com> Gerrit-Reviewer: Marcello Sylvester Bauer <info(a)marcellobauer.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: siemens/mc_apl4: Add new mainboard variant mc_apl4
by Mario Scheithauer (Code Review) 05 Nov '18

05 Nov '18

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/29467 Change subject: siemens/mc_apl4: Add new mainboard variant mc_apl4 ...................................................................... siemens/mc_apl4: Add new mainboard variant mc_apl4 This mainboard is based on mc_apl1. In a first step, it concerns a copy of mc_apl1 directory with minimum changes. Special adaptations for mc_apl4 mainboard will follow in separate commits. Change-Id: I3dfdccc8198f3a23a45d319ede6080803a46f7f6 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/Kconfig M src/mainboard/siemens/mc_apl1/Kconfig.name A src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig A src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc A src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb A src/mainboard/siemens/mc_apl1/variants/mc_apl4/mainboard.c 6 files changed, 240 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29467/1 diff --git a/src/mainboard/siemens/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/Kconfig index ee86a4d..eeb5d9b 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig +++ b/src/mainboard/siemens/mc_apl1/Kconfig @@ -19,12 +19,14 @@ default "mc_apl1" if BOARD_SIEMENS_MC_APL1 default "mc_apl2" if BOARD_SIEMENS_MC_APL2 default "mc_apl3" if BOARD_SIEMENS_MC_APL3 + default "mc_apl4" if BOARD_SIEMENS_MC_APL4 config MAINBOARD_PART_NUMBER string default "MC APL1" if BOARD_SIEMENS_MC_APL1 default "MC APL2" if BOARD_SIEMENS_MC_APL2 default "MC APL3" if BOARD_SIEMENS_MC_APL3 + default "MC APL4" if BOARD_SIEMENS_MC_APL4 config MAX_CPUS int diff --git a/src/mainboard/siemens/mc_apl1/Kconfig.name b/src/mainboard/siemens/mc_apl1/Kconfig.name index e1c2aa1..592d8aa 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig.name +++ b/src/mainboard/siemens/mc_apl1/Kconfig.name @@ -9,3 +9,7 @@ config BOARD_SIEMENS_MC_APL3 bool "-> MC APL3" select BOARD_SIEMENS_BASEBOARD_MC_APL1 + +config BOARD_SIEMENS_MC_APL4 + bool "-> MC APL4" + select BOARD_SIEMENS_BASEBOARD_MC_APL1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig new file mode 100644 index 0000000..3cf7406 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Kconfig @@ -0,0 +1,16 @@ + +if BOARD_SIEMENS_MC_APL4 + +config BOARD_SIEMENS_MC_APL4_VAR + def_bool y + select DRIVER_INTEL_I210 + select DRIVERS_I2C_RX6110SA + select DRIVER_SIEMENS_NC_FPGA + select NC_FPGA_NOTIFY_CB_READY + select APL_SKIP_SET_POWER_LIMITS + +config DEVICETREE + string + default "variants/mc_apl4/devicetree.cb" + +endif # BOARD_SIEMENS_MC_APL4 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc new file mode 100644 index 0000000..f3c87b2 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += mainboard.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb new file mode 100644 index 0000000..f3e8a77 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -0,0 +1,119 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "sci_irq" = "SCIS_IRQ10" + + # Disable unused clkreq of PCIe root ports + register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge + register "pcie_rp_clkreq_pin[1]" = "2" # FPGA + register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY + register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + # 0:HS400(Default), 1:HS200, 2:DDR50 + register "emmc_host_max_speed" = "2" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Proximity Sensor | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_STANDARD + }, + }" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 off end # - DPTF + device pci 00.2 off end # - NPK + device pci 02.0 on end # - Gen - Display + device pci 03.0 off end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 off end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 off end # - Shared SRAM + device pci 0e.0 off end # - Audio + device pci 11.0 on end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY + device pci 13.1 on end # - RP 3 - PCIe A 1 - MACPHY + device pci 13.2 off end # - RP 4 - PCIe-A 2 + device pci 13.3 off end # - RP 5 - PCIe-A 3 + device pci 14.0 on end # - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge + device pci 14.1 on end # - RP 1 - PCIe-B 1 - FPGA + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on # - I2C 0 + # Enable external RTC chip + chip drivers/i2c/rx6110sa + register "pmon_sampling" = "PMON_SAMPL_256_MS" + register "bks_on" = "0" + register "bks_off" = "1" + register "iocut_en" = "1" + register "set_user_date" = "1" + register "user_year" = "04" + register "user_month" = "07" + register "user_day" = "01" + register "user_weekday" = "4" + device i2c 0x32 on end # RTC RX6110 SA + end + end + device pci 16.1 off end # - I2C 1 + device pci 16.2 off end # - I2C 2 + device pci 16.3 off end # - I2C 3 + device pci 17.0 off end # - I2C 4 + device pci 17.1 off end # - I2C 5 + device pci 17.2 off end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 off end # - SPI 0 + device pci 19.1 off end # - SPI 1 + device pci 19.2 off end # - SPI 2 + device pci 1a.0 off end # - PWM + device pci 1b.0 off end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1d.0 off end # - UFS + device pci 1e.0 off end # - SDIO + device pci 1f.0 on end # - LPC + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/mainboard.c new file mode 100644 index 0000000..ccf3ab8 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/mainboard.c @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <gpio.h> +#include <hwilib.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> +#include <soc/pcr_ids.h> +#include <timer.h> +#include <timestamp.h> +#include <baseboard/variants.h> + +#define TX_DWORD3 0xa8c + +void variant_mainboard_final(void) +{ + struct device *dev = NULL; + + /* + * PIR6 register mapping for PCIe root ports + * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA# + */ + pcr_write16(PID_ITSS, 0x314c, 0x0321); + + /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */ + dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0); + if (dev) + pci_write_config8(dev, 0xd8, 0x3e); + + /* Enable CLKRUN_EN for power gating LPC */ + lpc_enable_pci_clk_cntl(); + + /* + * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2 + * offset 0x341D bit3 and bit0. + * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2 + * offset 0x341C bit [3:0]. + */ + pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN)); + + /* + * Correct the SATA transmit signal via the High Speed I/O Transmit + * Control Register 3. + * Bit [23:16] set the output voltage swing for TX line. + * The value 0x4a sets the swing level to 0.58 V. + */ + pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16)); +} + +static void wait_for_legacy_dev(void *unused) +{ + uint32_t legacy_delay, us_since_boot; + struct stopwatch sw; + + /* Open main hwinfo block. */ + if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + return; + + /* Get legacy delay parameter from hwinfo. */ + if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay, + sizeof(legacy_delay)) != sizeof(legacy_delay)) + return; + + us_since_boot = get_us_since_boot(); + /* No need to wait if the time since boot is already long enough.*/ + if (us_since_boot > legacy_delay) + return; + stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000); + printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...", + legacy_delay - us_since_boot, legacy_delay); + stopwatch_wait_until_expired(&sw); + printk(BIOS_NOTICE, "done!\n"); +} + +static void finalize_boot(void *unused) +{ + /* Set coreboot ready LED. */ + gpio_output(CNV_RGI_DT, 1); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); -- To view, visit https://review.coreboot.org/29467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3dfdccc8198f3a23a45d319ede6080803a46f7f6 Gerrit-Change-Number: 29467 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>

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Change in coreboot[master]: siemens/mc_apl2: Adjust GPIO settings for mc_apl2
by Werner Zeh (Code Review) 05 Nov '18

05 Nov '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/29318 ) Change subject: siemens/mc_apl2: Adjust GPIO settings for mc_apl2 ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29318/2/src/mainboard/siemens/mc_apl1/varia… File src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c: https://review.coreboot.org/#/c/29318/2/src/mainboard/siemens/mc_apl1/varia… PS2, Line 97: MASK Please align the indention to match with the open bracket of the macro. This is spread across the whole file whenever a line was split. -- To view, visit https://review.coreboot.org/29318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I16387358d6c6fa15efd16f7ba7f6b89740477e9d Gerrit-Change-Number: 29318 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Pöche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Nov 2018 08:02:45 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src/soc/intel/braswell/southcluster.c: Configure IO APIC
by Frans Hendriks (Code Review) 05 Nov '18

05 Nov '18

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/29423 ) Change subject: src/soc/intel/braswell/southcluster.c: Configure IO APIC ...................................................................... Patch Set 3: > Patch Set 3: > > (2 comments) The area need to be reserved to ensure no other use of this area. It might work without this area, but to be ACPI compliant coreboot must claim used areas. In comment of CBFS_SIZE mentioned it defaults span the whole ROM. The use of IO_APIC is in same style of RCBA (at least for braswell). You mean the RCBAxx() macro style used on some other platforms? -- To view, visit https://review.coreboot.org/29423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d Gerrit-Change-Number: 29423 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 05 Nov 2018 07:33:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/octopus: Add support to get OEM name from CBFS
by Wisley Chen (Code Review) 05 Nov '18

05 Nov '18

Wisley Chen has uploaded this change for review. ( https://review.coreboot.org/29466 Change subject: mb/google/octopus: Add support to get OEM name from CBFS ...................................................................... mb/google/octopus: Add support to get OEM name from CBFS refer to https://review.coreboot.org/c/coreboot/+/26142 This change: 1. Allows mainboard to add OEM table to CBFS 2. Provides mainboard specific smbios_mainboard_manufacturer that reads OEM ID from EC using CBI and compares it against the OEM ID in CBFS table to identify the right OEM string. BUG=b:118798180 TEST=emerge-ocotopus coreboot Change-Id: Idd7385db9a6189d70b92d31a0aa00ed03b37404c Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- M src/mainboard/google/octopus/Kconfig M src/mainboard/google/octopus/Makefile.inc M src/mainboard/google/octopus/mainboard.c 3 files changed, 87 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/29466/1 diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index f00803d..d4e8e58 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -136,4 +136,8 @@ default 1 if BOARD_GOOGLE_MEEP default 255 if BOARD_GOOGLE_OCTOPUS +config OEM_BIN_FILE + string "OEM ID table" + default "" + endif # BOARD_GOOGLE_OCTOPUS diff --git a/src/mainboard/google/octopus/Makefile.inc b/src/mainboard/google/octopus/Makefile.inc index 1a9adbc..9f28956 100644 --- a/src/mainboard/google/octopus/Makefile.inc +++ b/src/mainboard/google/octopus/Makefile.inc @@ -16,3 +16,8 @@ VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +# Add OEM ID table +cbfs-files-y += oem.bin +oem.bin-file := $(call strip_quotes,$(CONFIG_OEM_BIN_FILE)) +oem.bin-type := raw diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index fceb95d..6ca99f7 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -16,7 +16,9 @@ #include <arch/acpi.h> #include <baseboard/variants.h> #include <boardid.h> +#include <cbfs.h> #include <console/console.h> +#include <commonlib/cbfs_serialized.h> #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> @@ -180,3 +182,79 @@ /* Defer to variant for board-specific updates. */ variant_update_devtree(dev); } + +#define OEM_UNKNOWN 0xff + +/* + * Read OEM ID from EC using cbi commands. + * Return value: + * Success = OEM ID read from EC + * Failure = OEM_UNKNOWN (0xff) + */ +static uint8_t read_oem_id(void) +{ + static uint8_t oem_id = OEM_UNKNOWN; + uint32_t id; + + if (oem_id != OEM_UNKNOWN) + return oem_id; + + if (google_chromeec_cbi_get_oem_id(&id)) + return OEM_UNKNOWN; + + if (id > OEM_UNKNOWN) { + printk(BIOS_ERR, "%s: OEM ID too big %u!\n", __func__, id); + return OEM_UNKNOWN; + } + + oem_id = id; + printk(BIOS_DEBUG, "%s: OEM ID=%d\n", __func__, oem_id); + + return oem_id; +} + +/* "oem.bin" in cbfs contains array of records using the following structure. */ +struct oem_mapping { + uint8_t oem_id; + char oem_name[10]; +} __packed; + +/* Local buffer to read "oem.bin" */ +static char oem_bin_data[200]; + +const char *smbios_mainboard_manufacturer(void) +{ + uint8_t oem_id = read_oem_id(); + const struct oem_mapping *oem_entry = (void *)&oem_bin_data; + size_t oem_data_size; + size_t curr = 0; + static const char *manuf; + + if (manuf) + return manuf; + + /* If OEM ID cannot be determined, return default manuf string. */ + if (oem_id == OEM_UNKNOWN) + return CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; + + oem_data_size = cbfs_boot_load_file("oem.bin", oem_bin_data, + sizeof(oem_bin_data), + CBFS_TYPE_RAW); + + while ((curr < oem_data_size) && + ((oem_data_size - curr) >= sizeof(*oem_entry))) { + if (oem_id == oem_entry->oem_id) { + manuf = oem_entry->oem_name; + break; + } + curr += sizeof(*oem_entry); + oem_entry++; + } + + if (manuf == NULL) + manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; + + return manuf; +} + + -- To view, visit https://review.coreboot.org/29466 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idd7385db9a6189d70b92d31a0aa00ed03b37404c Gerrit-Change-Number: 29466 Gerrit-PatchSet: 1 Gerrit-Owner: Wisley Chen <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com>

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coreboot-gerrit November 2018