coreboot-gerrit November 2018

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Change in coreboot[master]: mb/google/kahlee: edp panel initialization time tuning
by build bot (Jenkins) (Code Review) 05 Nov '18

05 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29469 ) Change subject: mb/google/kahlee: edp panel initialization time tuning ...................................................................... Patch Set 2: (4 comments) https://review.coreboot.org/#/c/29469/2/src/mainboard/google/kahlee/OemCust… File src/mainboard/google/kahlee/OemCustomize.c: https://review.coreboot.org/#/c/29469/2/src/mainboard/google/kahlee/OemCust… PS2, Line 84: " config, \n"); unnecessary whitespace before a quoted newline https://review.coreboot.org/#/c/29469/2/src/mainboard/google/kahlee/OemCust… PS2, Line 88: if ((cfg->lvds_poseq_blon_to_varybl) && (cfg->lvds_poseq_varybl_to_blon)) { line over 80 characters https://review.coreboot.org/#/c/29469/2/src/mainboard/google/kahlee/OemCust… PS2, Line 90: params->LvdsPowerOnSeqVaryBlToBlon = cfg->lvds_poseq_varybl_to_blon; line over 80 characters https://review.coreboot.org/#/c/29469/2/src/mainboard/google/kahlee/OemCust… PS2, Line 91: params->LvdsPowerOnSeqBlonToVaryBl = cfg->lvds_poseq_blon_to_varybl; line over 80 characters -- To view, visit https://review.coreboot.org/29469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb Gerrit-Change-Number: 29469 Gerrit-PatchSet: 2 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Nov 2018 12:13:09 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/kahlee: edp panel initialization time tuning
by chris wang (Code Review) 05 Nov '18

05 Nov '18

Hello Chris Wang, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29469 to look at the new patch set (#2). Change subject: mb/google/kahlee: edp panel initialization time tuning ...................................................................... mb/google/kahlee: edp panel initialization time tuning 1.adding two parameters for panel initialization timing. > lvds_poseq_varybl_to_blon > lvds_poseq_blon_to_varybl 2.changing GPIO EP133 to high as default. BUG=b:118011567 TEST=emerge-grunt coreboot Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> --- M src/mainboard/google/kahlee/OemCustomize.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/kahlee/variants/liara/devicetree.cb M src/soc/amd/stoneyridge/chip.h 4 files changed, 18 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29469/2 -- To view, visit https://review.coreboot.org/29469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb Gerrit-Change-Number: 29469 Gerrit-PatchSet: 2 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/kahlee: edp panel initialization time tuning
by build bot (Jenkins) (Code Review) 05 Nov '18

05 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29469 ) Change subject: mb/google/kahlee: edp panel initialization time tuning ...................................................................... Patch Set 1: (4 comments) https://review.coreboot.org/#/c/29469/1/src/mainboard/google/kahlee/OemCust… File src/mainboard/google/kahlee/OemCustomize.c: https://review.coreboot.org/#/c/29469/1/src/mainboard/google/kahlee/OemCust… PS1, Line 84: " config, \n"); unnecessary whitespace before a quoted newline https://review.coreboot.org/#/c/29469/1/src/mainboard/google/kahlee/OemCust… PS1, Line 88: if ((cfg->lvds_poseq_blon_to_varybl) && (cfg->lvds_poseq_varybl_to_blon)) { line over 80 characters https://review.coreboot.org/#/c/29469/1/src/mainboard/google/kahlee/OemCust… PS1, Line 90: params->LvdsPowerOnSeqVaryBlToBlon = cfg->lvds_poseq_varybl_to_blon; line over 80 characters https://review.coreboot.org/#/c/29469/1/src/mainboard/google/kahlee/OemCust… PS1, Line 91: params->LvdsPowerOnSeqBlonToVaryBl = cfg->lvds_poseq_blon_to_varybl; line over 80 characters -- To view, visit https://review.coreboot.org/29469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb Gerrit-Change-Number: 29469 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Nov 2018 12:01:56 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/kahlee: edp panel initialization time tuning
by chris wang (Code Review) 05 Nov '18

05 Nov '18

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/29469 to review the following change. Change subject: mb/google/kahlee: edp panel initialization time tuning ...................................................................... mb/google/kahlee: edp panel initialization time tuning 1.adding two parameters for panel initialization timing. > lvds_poseq_varybl_to_blon > lvds_poseq_blon_to_varybl 2.changing GPIO EP133 to high as default. BUG=b:118011567 TEST=emerge-grunt coreboot Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> --- M src/mainboard/google/kahlee/OemCustomize.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/kahlee/variants/liara/devicetree.cb M src/soc/amd/stoneyridge/chip.h 4 files changed, 20 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29469/1 diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index a0bd8cd..e1275f0 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -16,6 +16,8 @@ #include <chip.h> #include <amdblocks/agesawrapper.h> #include <boardid.h> +#include <console/console.h> +#include <soc/pci_devs.h> #define DIMMS_PER_CHANNEL 1 #if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH @@ -75,5 +77,18 @@ void set_board_env_params(GNB_ENV_CONFIGURATION *params) { + const struct soc_amd_stoneyridge_config *cfg; + const struct device *dev = dev_find_slot(0, GNB_DEVFN); + if (!dev || !dev->chip_info) { + printk(BIOS_WARNING, "Warning: Cannot find SoC devicetree" + " config, \n"); + return; + } + cfg = dev->chip_info; + if ((cfg->lvds_poseq_blon_to_varybl) && (cfg->lvds_poseq_varybl_to_blon)) { + printk(BIOS_DEBUG, "Change panel init timing\n"); + params->LvdsPowerOnSeqVaryBlToBlon = cfg->lvds_poseq_varybl_to_blon; + params->LvdsPowerOnSeqBlonToVaryBl = cfg->lvds_poseq_blon_to_varybl; + } params->EDPv1_4VSMode = EDP_VS_HIGH_VDIFF_MODE; } diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 6095a08..5c74c89 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -218,7 +218,7 @@ PAD_GPI(GPIO_130, PULL_UP), /* GPIO_133 - APU_EDP_BKLTEN_L (backlight - Active LOW) */ - PAD_GPO(GPIO_133, HIGH), + PAD_GPO(GPIO_133, LOW), /* GPIO_135 - BCLK Buffer Enable */ PAD_GPO(GPIO_135, HIGH), diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/devicetree.cb index 343fbeb..8b964c2 100644 --- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/liara/devicetree.cb @@ -20,7 +20,8 @@ register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" register "uma_size" = "32 * MiB" - + register "lvds_poseq_varybl_to_blon" = "0x5" + register "lvds_poseq_blon_to_varybl" = "0x5" # Enable I2C0 for audio, USB3 hub at 400kHz register "i2c[0]" = "{ .speed = I2C_SPEED_FAST, diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index 320bef0..29ce026 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -63,6 +63,8 @@ u8 stapm_percent; u32 stapm_time_ms; u32 stapm_power_mw; + u8 lvds_poseq_varybl_to_blon; + u8 lvds_poseq_blon_to_varybl; }; typedef struct soc_amd_stoneyridge_config config_t; -- To view, visit https://review.coreboot.org/29469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb Gerrit-Change-Number: 29469 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com>

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Change in coreboot[master]: [DO NOT MERGE]: local test for mem init time
by Tristan Hsieh (Code Review) 05 Nov '18

05 Nov '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/29468 Change subject: [DO NOT MERGE]: local test for mem init time ...................................................................... [DO NOT MERGE]: local test for mem init time Change-Id: Id0de3017b003b6b594a6f9f8f7c431198ab9047e Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/mainboard/google/kukui/romstage.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/29468/1 diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 7c5a70d..a5eb913 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -14,11 +14,17 @@ */ #include <arch/stages.h> +#include <console/console.h> #include <soc/mmu_operations.h> #include <soc/emi.h> +#include <timer.h> void platform_romstage_main(void) { + struct stopwatch sw; + stopwatch_init(&sw); mt_mem_init(get_sdram_config()); + printk(BIOS_DEBUG, "mem init time: %ld usecs\n", + stopwatch_duration_usecs(&sw)); mtk_mmu_after_dram(); } -- To view, visit https://review.coreboot.org/29468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id0de3017b003b6b594a6f9f8f7c431198ab9047e Gerrit-Change-Number: 29468 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

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Change in coreboot[master]: src/soc/intel/braswell/southcluster.c: Configure IO APIC
by Patrick Rudolph (Code Review) 05 Nov '18

05 Nov '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/29423 ) Change subject: src/soc/intel/braswell/southcluster.c: Configure IO APIC ...................................................................... Patch Set 3: > > Patch Set 3: > > > > (2 comments) > > The area need to be reserved to ensure no other use of this area. > It might work without this area, but to be ACPI compliant coreboot > must claim used areas. > In comment of CBFS_SIZE mentioned it defaults span the whole ROM. > "It defaults to span the whole ROM on all but Intel systems that use an Intel Firmware Descriptor." On vboot enabled systems CBFS_SIZE << BIOS_REGION. You need to read the size of the BIOS region from SPIBAR. > The use of IO_APIC is in same style of RCBA (at least for > braswell). You mean the RCBAxx() macro style used on some other > platforms? yes, like #define IOAPIC32(x) ... -- To view, visit https://review.coreboot.org/29423 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I917c30892b46ac1d964e7bab339082d17a1e706d Gerrit-Change-Number: 29423 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 05 Nov 2018 10:44:48 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: siemens/mc_apl2: Adjust GPIO settings for mc_apl2
by Mario Scheithauer (Code Review) 05 Nov '18

05 Nov '18

Hello Werner Zeh, Uwe Pöche, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29318 to look at the new patch set (#5). Change subject: siemens/mc_apl2: Adjust GPIO settings for mc_apl2 ...................................................................... siemens/mc_apl2: Adjust GPIO settings for mc_apl2 This mainboard variant requires GPIO adaptations to match the hardware. Change-Id: I16387358d6c6fa15efd16f7ba7f6b89740477e9d Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc A src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c 2 files changed, 687 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/29318/5 -- To view, visit https://review.coreboot.org/29318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I16387358d6c6fa15efd16f7ba7f6b89740477e9d Gerrit-Change-Number: 29318 Gerrit-PatchSet: 5 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Pöche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: siemens/mc_apl2: Adjust GPIO settings for mc_apl2
by Mario Scheithauer (Code Review) 05 Nov '18

05 Nov '18

Hello Werner Zeh, Uwe Pöche, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29318 to look at the new patch set (#4). Change subject: siemens/mc_apl2: Adjust GPIO settings for mc_apl2 ...................................................................... siemens/mc_apl2: Adjust GPIO settings for mc_apl2 This mainboard variant requires GPIO adaptations to match the hardware. Change-Id: I16387358d6c6fa15efd16f7ba7f6b89740477e9d Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc A src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c 2 files changed, 686 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/29318/4 -- To view, visit https://review.coreboot.org/29318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I16387358d6c6fa15efd16f7ba7f6b89740477e9d Gerrit-Change-Number: 29318 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Pöche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: siemens/mc_apl2: Adjust GPIO settings for mc_apl2
by Mario Scheithauer (Code Review) 05 Nov '18

05 Nov '18

Hello Werner Zeh, Uwe Pöche, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29318 to look at the new patch set (#3). Change subject: siemens/mc_apl2: Adjust GPIO settings for mc_apl2 ...................................................................... siemens/mc_apl2: Adjust GPIO settings for mc_apl2 This mainboard variant requires GPIO adaptations to match the hardware. Change-Id: I16387358d6c6fa15efd16f7ba7f6b89740477e9d Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc A src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c 2 files changed, 687 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/29318/3 -- To view, visit https://review.coreboot.org/29318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I16387358d6c6fa15efd16f7ba7f6b89740477e9d Gerrit-Change-Number: 29318 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Pöche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/x4x/raminit: Add missing space
by Patrick Georgi (Code Review) 05 Nov '18

05 Nov '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29346 ) Change subject: nb/intel/x4x/raminit: Add missing space ...................................................................... nb/intel/x4x/raminit: Add missing space TEST=Make the printk reachable, check with `strings build/cbfs/fallback/romstage.elf | grep lowest` that this patch changes "MHzas" to "MHz as". Change-Id: I42033d2f184e424818edf844cf6cf84ea07d7ed5 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-on: https://review.coreboot.org/29346 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/northbridge/intel/x4x/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 80bde6c..ff1f970 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -304,7 +304,7 @@ min_tCLK = MAX(min_tCLK, saved_timings->min_tclk); if (min_tCLK == 0) { printk(BIOS_ERR, "DRAM frequency is under lowest supported " - "frequency (400 MHz). Increasing to 400 MHz" + "frequency (400 MHz). Increasing to 400 MHz " "as last resort"); min_tCLK = TCK_400MHZ; } -- To view, visit https://review.coreboot.org/29346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I42033d2f184e424818edf844cf6cf84ea07d7ed5 Gerrit-Change-Number: 29346 Gerrit-PatchSet: 3 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit November 2018