coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

1 participants
1699 discussions

Change in coreboot[master]: [RFC] lib/spd_bin: Redesign API
by Nico Huber (Code Review) 05 Nov '18

05 Nov '18

Nico Huber has uploaded a new patch set (#2). ( https://review.coreboot.org/29481 ) Change subject: [RFC] lib/spd_bin: Redesign API ...................................................................... [RFC] lib/spd_bin: Redesign API About every two years, somebody reinvents the wheel wrt. SPD handling. Let's break the cycle by providing an API that is simple enough to be used in mainboard code and handles all common patterns (e.g. reading SPDs from CBFS or SMBus). This is not complete yet, but I wanted to get feedback as early as possible. The rough idea is: o mainboard code provides a struct with information about where to fetch the SPD from, *per module* (e.g. CBFS, SMBus, memory address) o common code gathers the SPDs and normalizes the struct, so all entries will eventually be memory addresses The current version uses a simple array to represent the modules. This doesn't reflect the actual topology of memory channels, which is in- stead implied by the consumer of the normalized struct, atm. This could be extended later, for instance, with a common SPD cache that could be stored along the MRC cache data. Note that for the latest incarnation, the SPD code of intel/cannonlake, this removes the option to let FSP load the SPD from SMBus. It didn't seem useful, though, as it removes all flexibility. And isn't FSP's responsibility anyway. Change-Id: Iac300a374e5cd56a9d202cf24ad8fe8367b780d8 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/Kconfig M src/include/spd_bin.h M src/lib/spd_bin.c M src/mainboard/google/fizz/Kconfig M src/mainboard/google/fizz/romstage.c M src/mainboard/google/kahlee/romstage.c M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/kahlee/variants/baseboard/memory.c M src/mainboard/google/zoombini/romstage.c M src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/coffeelake_rvp/romstage.c M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/kblrvp/romstage.c M src/mainboard/intel/saddlebrook/Kconfig M src/mainboard/intel/saddlebrook/romstage.c M src/mainboard/purism/librem_skl/Kconfig M src/mainboard/purism/librem_skl/romstage.c M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/cnl_memcfg_init.c M src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h 21 files changed, 277 insertions(+), 241 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/29481/2 -- To view, visit https://review.coreboot.org/29481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iac300a374e5cd56a9d202cf24ad8fe8367b780d8 Gerrit-Change-Number: 29481 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: [RFC] lib/spd_bin: Redesign API
by build bot (Jenkins) (Code Review) 05 Nov '18

05 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29481 ) Change subject: [RFC] lib/spd_bin: Redesign API ...................................................................... Patch Set 1: (3 comments) https://review.coreboot.org/#/c/29481/1/src/include/spd_bin.h File src/include/spd_bin.h: https://review.coreboot.org/#/c/29481/1/src/include/spd_bin.h@92 PS1, Line 92: ssize_t gather_spds(struct spd_binfo *); function definition argument 'struct spd_binfo *' should also have an identifier name https://review.coreboot.org/#/c/29481/1/src/include/spd_bin.h@94 PS1, Line 94: void dump_spd_info(const struct spd_binfo *); function definition argument 'const struct spd_binfo *' should also have an identifier name https://review.coreboot.org/#/c/29481/1/src/lib/spd_bin.c File src/lib/spd_bin.c: https://review.coreboot.org/#/c/29481/1/src/lib/spd_bin.c@227 PS1, Line 227: if (common_len == -1) { braces {} are not necessary for any arm of this statement -- To view, visit https://review.coreboot.org/29481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iac300a374e5cd56a9d202cf24ad8fe8367b780d8 Gerrit-Change-Number: 29481 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Nov 2018 17:37:19 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: [WIP] mb/kontron/bsl6: Add new Skylake COMe module
by build bot (Jenkins) (Code Review) 05 Nov '18

05 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29480 ) Change subject: [WIP] mb/kontron/bsl6: Add new Skylake COMe module ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29480/1/src/mainboard/kontron/bsl6/romstage… File src/mainboard/kontron/bsl6/romstage.c: https://review.coreboot.org/#/c/29480/1/src/mainboard/kontron/bsl6/romstage… PS1, Line 39: FSP_M_CONFIG *const memory_params = &mupd->FspmConfig; need consistent spacing around '*' (ctx:WxV) -- To view, visit https://review.coreboot.org/29480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If2b6a3f1e9dd095463f1f1521068b9f66a9189c5 Gerrit-Change-Number: 29480 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Nov 2018 17:37:05 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: device/i2c_bus: Add i2c_dev_readb_at_word()
by build bot (Jenkins) (Code Review) 05 Nov '18

05 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29478 ) Change subject: device/i2c_bus: Add i2c_dev_readb_at_word() ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/29478/1/src/device/i2c_bus.c File src/device/i2c_bus.c: https://review.coreboot.org/#/c/29478/1/src/device/i2c_bus.c@189 PS1, Line 189: transfer(busdev, msg, ARRAY_SIZE(msg)); Avoid multiple line dereference - prefer 'busdev->ops->ops_i2c_bus->transfer' https://review.coreboot.org/#/c/29478/1/src/include/device/i2c_bus.h File src/include/device/i2c_bus.h: https://review.coreboot.org/#/c/29478/1/src/include/device/i2c_bus.h@98 PS1, Line 98: int i2c_dev_readb_at_word(struct device *, function definition argument 'struct device *' should also have an identifier name -- To view, visit https://review.coreboot.org/29478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7516f3e5d9aca362c2b340aa5627d91510c09412 Gerrit-Change-Number: 29478 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Nov 2018 17:36:51 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: ec/kontron: Add support for Kontron kempld
by build bot (Jenkins) (Code Review) 05 Nov '18

05 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29476 ) Change subject: ec/kontron: Add support for Kontron kempld ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/29476/1/src/ec/kontron/kempld/kempld_i2c.c File src/ec/kontron/kempld/kempld_i2c.c: https://review.coreboot.org/#/c/29476/1/src/ec/kontron/kempld/kempld_i2c.c@… PS1, Line 169: } else { else is not generally useful after a break or return https://review.coreboot.org/#/c/29476/1/src/ec/kontron/kempld/kempld_i2c.c@… PS1, Line 214: printk(BIOS_SPEW, "kempld_i2c: Processed %zu segments.\n", num); line over 80 characters -- To view, visit https://review.coreboot.org/29476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If9a0826c4a8f5c8cd573610c2d10561334258b36 Gerrit-Change-Number: 29476 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Nov 2018 17:36:26 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: [RFC] lib/spd_bin: Redesign API
by Nico Huber (Code Review) 05 Nov '18

05 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29481 Change subject: [RFC] lib/spd_bin: Redesign API ...................................................................... [RFC] lib/spd_bin: Redesign API About every two years, somebody reinvents the wheel wrt. SPD handling. Let's break the cycle by providing an API that is simple enough to be used in mainboard code and handles all common patterns (e.g. reading SPDs from CBFS or SMBus). This is not complete yet, but I wanted to get feedback as early as possible. The rough idea is: o mainboard code provides a struct with information about where to fetch the SPD from, *per module* (e.g. CBFS, SMBus, memory address) o common code gathers the SPDs and normalizes the struct, so all entries will eventually be memory addresses The current version uses a simple array to represent the modules. This doesn't reflect the actual topology of memory channels, which is in- stead implied by the consumer of the normalized struct, atm. This could be extended later, for instance, with a common SPD cache that could be stored along the MRC cache data. Note that for the latest incarnation, the SPD code of intel/cannonlake, this removes the option to let FSP load the SPD from SMBus. It didn't seem useful, though, as it removes all flexibility. And isn't FSP's responsibility anyway. Change-Id: Iac300a374e5cd56a9d202cf24ad8fe8367b780d8 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/Kconfig M src/include/spd_bin.h M src/lib/spd_bin.c M src/mainboard/google/fizz/Kconfig M src/mainboard/google/fizz/romstage.c M src/mainboard/google/kahlee/romstage.c M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/kahlee/variants/baseboard/memory.c M src/mainboard/google/zoombini/romstage.c M src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/coffeelake_rvp/romstage.c M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/kblrvp/romstage.c M src/mainboard/intel/saddlebrook/Kconfig M src/mainboard/intel/saddlebrook/romstage.c M src/mainboard/kontron/bsl6/Kconfig M src/mainboard/kontron/bsl6/romstage.c M src/mainboard/purism/librem_skl/Kconfig M src/mainboard/purism/librem_skl/romstage.c M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/cnl_memcfg_init.c M src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h 23 files changed, 287 insertions(+), 248 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/29481/1 diff --git a/src/Kconfig b/src/Kconfig index 2777d26..2938246 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1211,6 +1211,11 @@ Total SPD size that will be used for DIMM. Ex: DDR3 256, DDR4 512. +config DIMM_SPD_SMBUS + bool + help + Support fetching SPDs from SMBus. + config SPD_READ_BY_WORD bool diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index e0a50ff..1f20e8b 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -16,8 +16,8 @@ #ifndef SPD_BIN_H #define SPD_BIN_H -#include <arch/early_variables.h> #include <stdint.h> +#include <stdlib.h> #include <commonlib/region.h> #define SPD_PAGE_LEN 256 @@ -42,18 +42,59 @@ #define LPDDR4_SPD_PART_OFF 329 #define LPDDR4_SPD_PART_LEN 20 -struct spd_block { - u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */ - u8 *spd_array[CONFIG_DIMM_MAX]; - /* Length of each dimm */ - u16 len; +enum spd_bin_src { + SPD_BIN_NONE = 0, + SPD_BIN_SMBUS, /* read SPD from SMBus */ + SPD_BIN_CBFS, /* read SPD from CBFS file `spd.bin` containing + fixed entries of CONFIG_DIMM_SPD_SIZE bytes */ + SPD_BIN_COPY, /* copy SPD pointer from another entry */ + SPD_BIN_PTR, /* read SPD from memory address */ }; -void print_spd_info(uint8_t spd[]); -/* Return 0 on success & -1 on failure */ -int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index); -void dump_spd_info(struct spd_block *blk); -void get_spd_smbus(struct spd_block *blk); +struct spd_bin_dimm { + enum spd_bin_src src; + union { + u8 smbus_addr; /* 7 bit I2C address */ + u8 index; /* for SPD_BIN_CPFS or SPD_BIN_COPY */ + const u8 *spd; + }; + size_t len; +}; + +struct spd_binfo { + struct spd_bin_dimm spds[CONFIG_DIMM_MAX]; +}; + +#define SPD_BINFO_CBFS(idx) \ + { .spds = { { .src = SPD_BIN_CBFS, .index = idx, }, }, } +#define SPD_BINFO_SMBUS(a1) \ + { .spds = { { .src = SPD_BIN_SMBUS, .smbus_addr = a1, }, }, } +#define SPD_BINFO_SMBUS2(a1, a2) \ + { .spds = { { .src = SPD_BIN_SMBUS, .smbus_addr = a1, }, \ + { .src = SPD_BIN_SMBUS, .smbus_addr = a2, }, }, } +#define SPD_BINFO_SMBUS4(a1, a2, a3, a4) \ + { .spds = { { .src = SPD_BIN_SMBUS, .smbus_addr = a1, }, \ + { .src = SPD_BIN_SMBUS, .smbus_addr = a2, }, \ + { .src = SPD_BIN_SMBUS, .smbus_addr = a3, }, \ + { .src = SPD_BIN_SMBUS, .smbus_addr = a4, }, }, } + +/* + * Read SPDs from SMBus and CBFS if requested. If successful, all + * active entries should have SPD_BIN_PTR as `src` type and a valid + * `ptr` and `len`. + * + * Returns + * a common length if any SPD is present and *all* present + * SPDs have the same length, + * * 0 if multiple SPDs are present with different lengths, + * * -1 if no valid SPD could be found. + */ +ssize_t gather_spds(struct spd_binfo *); + +void dump_spd_info(const struct spd_binfo *); + + +/* FIXME: conflicting API below ------------------------------------------- */ /* expects SPD size to be 128 bytes, reads from "spd.bin" in CBFS and verifies the checksum. Only available if CONFIG_DIMM_SPD_SIZE == 128. */ diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 79bda1e..4277ea9 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -14,27 +14,20 @@ */ #include <arch/byteorder.h> +#include <arch/early_variables.h> #include <cbfs.h> +#include <commonlib/region.h> #include <console/console.h> #include <spd_bin.h> +#include <stdint.h> +#include <stdlib.h> #include <string.h> #include <device/early_smbus.h> #include <device/dram/ddr3.h> static u8 spd_data[CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE] CAR_GLOBAL; -void dump_spd_info(struct spd_block *blk) -{ - u8 i; - - for (i = 0; i < CONFIG_DIMM_MAX; i++) - if (blk->spd_array[i] != NULL && blk->spd_array[i][0] != 0) { - printk(BIOS_DEBUG, "SPD @ 0x%02X\n", blk->addr_map[i]); - print_spd_info(blk->spd_array[i]); - } -} - -void print_spd_info(uint8_t spd[]) +static void print_spd_info(const uint8_t spd[]) { const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 128 }; @@ -98,31 +91,17 @@ } } -static void update_spd_len(struct spd_block *blk) +void dump_spd_info(const struct spd_binfo *const info) { - u8 i, j = 0; - for (i = 0 ; i < CONFIG_DIMM_MAX; i++) - if (blk->spd_array[i] != NULL) - j |= blk->spd_array[i][SPD_DRAM_TYPE]; + int i; - /* If spd used is DDR4, then its length is 512 byte. */ - if (j == SPD_DRAM_DDR4) - blk->len = SPD_PAGE_LEN_DDR4; - else - blk->len = SPD_PAGE_LEN; -} - -int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index) -{ - struct cbfsf fh; - - uint32_t cbfs_type = CBFS_TYPE_SPD; - - if (cbfs_boot_locate(&fh, "spd.bin", &cbfs_type) < 0) - return -1; - cbfs_file_data(spd_rdev, &fh); - return rdev_chain(spd_rdev, spd_rdev, spd_index * CONFIG_DIMM_SPD_SIZE, - CONFIG_DIMM_SPD_SIZE); + for (i = 0; i < CONFIG_DIMM_MAX; i++) { + if (info->spds[i].src == SPD_BIN_PTR && + info->spds[i].spd != NULL && info->spds[i].spd[0] != 0) { + printk(BIOS_DEBUG, "SPD #%d\n", i); + print_spd_info(info->spds[i].spd); + } + } } static void smbus_read_spd(u8 *spd, u8 addr) @@ -142,14 +121,14 @@ } } -static void get_spd(u8 *spd, u8 addr) +static ssize_t get_spd_smbus(u8 *const spd, const size_t len, const u8 addr) { + if (!IS_ENABLED(CONFIG_DIMM_SPD_SMBUS)) + return -1; + if (smbus_read_byte(0, addr, 0) == 0xff) { - printk(BIOS_INFO, "No memory dimm at address %02X\n", - addr << 1); - /* Make sure spd is zeroed if dimm doesn't exist. */ - memset(spd, 0, CONFIG_DIMM_SPD_SIZE); - return; + printk(BIOS_INFO, "No SPD at address %02x.\n", addr); + return -1; } smbus_read_spd(spd, addr); @@ -162,20 +141,98 @@ /* Restore to page 0 */ smbus_write_byte(0, SPD_PAGE_0, 0, 0); } + + /* FIXME: Actually match read length. */ + return len; } -void get_spd_smbus(struct spd_block *blk) +static ssize_t get_spd_cbfs(u8 *const spd, const size_t len, const u8 index) { - u8 i; - unsigned char *spd_data_ptr = car_get_var_ptr(&spd_data); + uint32_t cbfs_type = CBFS_TYPE_SPD; + struct region_device rdev; + struct cbfsf fh; - for (i = 0 ; i < CONFIG_DIMM_MAX; i++) { - get_spd(spd_data_ptr + i * CONFIG_DIMM_SPD_SIZE, - blk->addr_map[i]); - blk->spd_array[i] = spd_data_ptr + i * CONFIG_DIMM_SPD_SIZE; + if (cbfs_boot_locate(&fh, "spd.bin", &cbfs_type) < 0) + return -1; + + cbfs_file_data(&rdev, &fh); + return rdev_readat(&rdev, spd, index * len, len); +} + +static ssize_t get_spd_copy(u8 **const ptr, const struct spd_binfo *const info, + const int i, const size_t len) +{ + const u8 src_index = info->spds[i].index; + + if (src_index > i) { + printk(BIOS_WARNING, "Can only copy preceding SPD entries.\n"); + return -1; } - update_spd_len(blk); + if (info->spds[src_index].src != SPD_BIN_PTR) { + printk(BIOS_WARNING, "Can only copy PTR SPD entries.\n"); + return -1; + } + + *ptr = (u8 *)info->spds[src_index].spd; + return info->spds[src_index].len; +} + +ssize_t gather_spds(struct spd_binfo *const info) +{ + const size_t len = CONFIG_DIMM_SPD_SIZE; + u8 *const spd_buffer = car_get_var_ptr(&spd_data); + ssize_t common_len = -1; + int i; + + for (i = 0; i < CONFIG_DIMM_MAX; ++i) { + ssize_t ret = 0; + u8 *ptr = NULL; + + switch (info->spds[i].src) { + case SPD_BIN_NONE: + break; + case SPD_BIN_SMBUS: + ptr = spd_buffer + i * len; + ret = get_spd_smbus(ptr, len, info->spds[i].smbus_addr); + break; + case SPD_BIN_CBFS: + ptr = spd_buffer + i * len; + ret = get_spd_cbfs(ptr, len, info->spds[i].index); + break; + case SPD_BIN_COPY: + ret = get_spd_copy(&ptr, info, i, len); + break; + case SPD_BIN_PTR: + ptr = (u8 *)info->spds[i].spd; + ret = info->spds[i].len; + break; + default: + ret = -1; + break; + } + + if (ret < 0) + printk(BIOS_WARNING, "Failed to fetch SPD #%d.\n", i); + else if (ret < len && info->spds[i].src != SPD_BIN_NONE) + printk(BIOS_WARNING, "Short SPD read for #%d.\n", i); + + info->spds[i].spd = ptr; + if (ret <= 0) { + info->spds[i].src = SPD_BIN_NONE; + info->spds[i].len = 0; + } else { + info->spds[i].src = SPD_BIN_PTR; + info->spds[i].len = ret; + if (common_len == -1) { + common_len = ret; + } else if (common_len != ret) { + common_len = 0; + } + } + } + + return common_len; } #if CONFIG_DIMM_SPD_SIZE == 128 diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index 1763f19..7feb6ab 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -2,6 +2,7 @@ config BOARD_GOOGLE_BASEBOARD_FIZZ def_bool n select BOARD_ROMSIZE_KB_16384 + select DIMM_SPD_SMBUS select DRIVERS_GENERIC_MAX98357A if BOARD_GOOGLE_KALISTA select DRIVERS_I2C_DA7219 if BOARD_GOOGLE_KALISTA select DRIVERS_I2C_GENERIC diff --git a/src/mainboard/google/fizz/romstage.c b/src/mainboard/google/fizz/romstage.c index 335662e..8c8b144 100644 --- a/src/mainboard/google/fizz/romstage.c +++ b/src/mainboard/google/fizz/romstage.c @@ -13,7 +13,10 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <soc/romstage.h> +#include <stddef.h> +#include <stdint.h> #include <string.h> #include <spd_bin.h> @@ -36,14 +39,18 @@ memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target)); /* Read spd block to get memory config */ - struct spd_block blk = { - .addr_map = { 0x50, 0x52, }, - }; - mem_cfg->DqPinsInterleaved = 1; - get_spd_smbus(&blk); - mem_cfg->MemorySpdDataLen = blk.len; - mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; - mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; + struct spd_binfo spd_info = { .spds = { + { .src = SPD_BIN_SMBUS, .smbus_addr = 0x50, }, + { .src = SPD_BIN_SMBUS, .smbus_addr = 0x52, }, + } }; + const ssize_t common_len = gather_spds(&spd_info); + if (common_len <= 0) + die("Failed to read any SPD from SMBus.\n"); - dump_spd_info(&blk); + mem_cfg->DqPinsInterleaved = 1; + mem_cfg->MemorySpdDataLen = common_len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)spd_info.spds[0].spd; + mem_cfg->MemorySpdPtr10 = (uintptr_t)spd_info.spds[1].spd; + + dump_spd_info(&spd_info); } diff --git a/src/mainboard/google/kahlee/romstage.c b/src/mainboard/google/kahlee/romstage.c index 5ec5c25..ca0e7c8 100644 --- a/src/mainboard/google/kahlee/romstage.c +++ b/src/mainboard/google/kahlee/romstage.c @@ -15,11 +15,30 @@ #include <amdblocks/dimm_spd.h> #include <baseboard/variants.h> +#include <console/console.h> #include <soc/romstage.h> +#include <spd_bin.h> +#include <stddef.h> +#include <string.h> int mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len) { - return variant_mainboard_read_spd(spdAddress, buf, len); + const u8 spd_index = variant_memory_sku(); + struct spd_binfo spd_info = SPD_BINFO_CBFS(spd_index); + + const ssize_t common_len = gather_spds(&spd_info); + if (common_len <= 0) + printk(BIOS_ERR, "Error: Failed to read SPD from CBFS.\n"); + return -1; + } + + if (len != common_len) { + printk(BIOS_ERR, "Error: Read SPD of incorrect length.\n"); + return -1; + } + + memcpy(buf, spd_info.spds[0].spd, len); + return 0; } void __weak variant_romstage_entry(int s3_resume) diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h index 6e89105..d29cea3 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h @@ -24,7 +24,6 @@ uint8_t variant_memory_sku(void); /* Return board SKU. Limited to uint8_t, so it fits into 3 decimal digits */ uint8_t variant_board_sku(void); -int variant_mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len); int variant_get_xhci_oc_map(uint16_t *usb_oc_map); int variant_get_ehci_oc_map(uint16_t *usb_oc_map); const struct soc_amd_gpio *variant_early_gpio_table(size_t *size); diff --git a/src/mainboard/google/kahlee/variants/baseboard/memory.c b/src/mainboard/google/kahlee/variants/baseboard/memory.c index 67402fb..d7f88d6 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/memory.c +++ b/src/mainboard/google/kahlee/variants/baseboard/memory.c @@ -14,11 +14,8 @@ */ #include <baseboard/variants.h> -#include <console/console.h> #include <gpio.h> /* src/include/gpio.h */ -#include <spd_bin.h> #include <variant/gpio.h> -#include <amdblocks/dimm_spd.h> uint8_t __weak variant_memory_sku(void) { @@ -31,29 +28,3 @@ return gpio_base2_value(pads, ARRAY_SIZE(pads)); } - -int __weak variant_mainboard_read_spd(uint8_t spdAddress, - char *buf, size_t len) -{ - struct region_device spd_rdev; - u8 spd_index = variant_memory_sku(); - - printk(BIOS_INFO, "%s SPD index %d\n", __func__, spd_index); - - if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) { - printk(BIOS_ERR, "Error: spd.bin not found\n"); - return -1; - } - - if (len != region_device_sz(&spd_rdev)) { - printk(BIOS_ERR, "Error: spd.bin is not the correct size\n"); - return -1; - } - - if (rdev_readat(&spd_rdev, buf, 0, len) != len) { - printk(BIOS_ERR, "Error: couldn't read spd.bin\n"); - return -1; - } - - return 0; -} diff --git a/src/mainboard/google/zoombini/romstage.c b/src/mainboard/google/zoombini/romstage.c index 4bd0ede..c07cfd9 100644 --- a/src/mainboard/google/zoombini/romstage.c +++ b/src/mainboard/google/zoombini/romstage.c @@ -16,14 +16,16 @@ #include <baseboard/variants.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> +#include <spd_bin.h> void mainboard_memory_init_params(FSPM_UPD *memupd) { - const struct spd_info spd = { - .spd_by_index = true, - .spd_spec.spd_index = variant_memory_sku(), - }; + struct spd_binfo spd_info = { .spds = { + { .src = SPD_BIN_CBFS, .index = variant_memory_sku(), }, + { .src = SPD_BIN_NONE, }, + { .src = SPD_BIN_COPY, .index = 0, }, + }, }; cannonlake_memcfg_init(&memupd->FspmConfig, - variant_lpddr4_config(), &spd); + variant_lpddr4_config(), &spd_info); } diff --git a/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c b/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c index 457be7f..642cef6 100644 --- a/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c +++ b/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c @@ -14,11 +14,12 @@ */ #include <arch/byteorder.h> -#include <cbfs.h> #include <console/console.h> #include <fsp/api.h> #include <soc/romstage.h> #include "spd/spd.h" +#include <stddef.h> +#include <stdint.h> #include <string.h> #include <spd_bin.h> @@ -40,14 +41,13 @@ mem_cfg->ECT = 1; /* Early Command Training Enabled */ spd_index = 2; - struct region_device spd_rdev; + struct spd_binfo spd_info = SPD_BINFO_CBFS(spd_index); + const ssize_t common_len = gather_spds(&spd_info); + if (common_len <= 0) + die("Failed to read SPD from CBFS.\n"); - if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) - die("spd.bin not found\n"); - - mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); - /* Memory leak is ok since we have memory mapped boot media */ - mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + mem_cfg->MemorySpdDataLen = common_len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)spd_info.spds[0].spd; mem_cfg->RefClk = 0; /* Auto Select CLK freq */ mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; } diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index f69bb71..408c7c6 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -4,17 +4,16 @@ def_bool y select BOARD_ROMSIZE_KB_16384 if !BOARD_INTEL_COFFEELAKE_RVPU select BOARD_ROMSIZE_KB_32768 if BOARD_INTEL_COFFEELAKE_RVPU - select GENERIC_SPD_BIN select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS - select GENERIC_SPD_BIN select DRIVERS_I2C_HID select DRIVERS_I2C_GENERIC select SOC_INTEL_COFFEELAKE select SOC_INTEL_CANNONLAKE_MEMCFG_INIT select SOC_INTEL_CANNONLAKE_PCH_H if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 select SOC_INTEL_COMMON_BLOCK_HDA_VERB if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 + select DIMM_SPD_SMBUS config MAINBOARD_DIR string diff --git a/src/mainboard/intel/coffeelake_rvp/romstage.c b/src/mainboard/intel/coffeelake_rvp/romstage.c index 1ab2d78..1e8c153 100644 --- a/src/mainboard/intel/coffeelake_rvp/romstage.c +++ b/src/mainboard/intel/coffeelake_rvp/romstage.c @@ -17,16 +17,11 @@ #include <baseboard/variants.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> +#include <spd_bin.h> void mainboard_memory_init_params(FSPM_UPD *memupd) { - const struct spd_info spd = { - .spd_smbus_address[0] = 0xA0, - .spd_smbus_address[1] = 0xA2, - .spd_smbus_address[2] = 0xA4, - .spd_smbus_address[3] = 0xA6, - }; - + struct spd_binfo spd_info = SPD_BINFO_SMBUS4(0x50, 0x51, 0x52, 0x53); cannonlake_memcfg_init(&memupd->FspmConfig, - variant_memcfg_config(), &spd); + variant_memcfg_config(), &spd_info); } diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index bf17c4b..6ece334 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -3,6 +3,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select BOARD_ROMSIZE_KB_16384 + select DIMM_SPD_SMBUS if BOARD_INTEL_KBLRVP7 || BOARD_INTEL_KBLRVP8 select EC_ACPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index a29a4af..79ab910 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -14,7 +14,6 @@ */ #include <arch/byteorder.h> -#include <cbfs.h> #include <console/console.h> #include <fsp/api.h> #include <gpio.h> @@ -22,11 +21,12 @@ #include <soc/romstage.h> #include <soc/gpio.h> #include "spd/spd.h" +#include <stddef.h> +#include <stdint.h> #include <string.h> #include <spd_bin.h> #include "board_id.h" - void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg; @@ -41,29 +41,31 @@ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP3)) { - struct region_device spd_rdev; + struct spd_binfo spd_info = SPD_BINFO_CBFS(spd_index); + const ssize_t common_len = gather_spds(&spd_info); + if (common_len <= 0) + die("Failed to read SPD from CBFS.\n"); mem_cfg->DqPinsInterleaved = 0; - if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) - die("spd.bin not found\n"); - mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); - /* Memory leak is ok since we have memory mapped boot media */ - mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + mem_cfg->MemorySpdDataLen = common_len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)spd_info.spds[0].spd; } else { /* CONFIG_BOARD_INTEL_KBLRVP7 and CONFIG_BOARD_INTEL_KBLRVP8 */ - struct spd_block blk = { - .addr_map = { 0x50, 0x51, 0x52, 0x53, }, - }; + struct spd_binfo spd_info = + SPD_BINFO_SMBUS4(0x50, 0x51, 0x52, 0x53); + const ssize_t common_len = gather_spds(&spd_info); + if (common_len <= 0) + die("Failed to read valid SPD(s) from SMBus.\n"); mem_cfg->DqPinsInterleaved = 1; - get_spd_smbus(&blk); - mem_cfg->MemorySpdDataLen = blk.len; - mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; - mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; + mem_cfg->MemorySpdDataLen = common_len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)spd_info.spds[0].spd; + mem_cfg->MemorySpdPtr10 = (uintptr_t)spd_info.spds[2].spd; if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)) { - mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; - mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + mem_cfg->MemorySpdPtr01 = + (uintptr_t)spd_info.spds[1].spd; + mem_cfg->MemorySpdPtr11 = + (uintptr_t)spd_info.spds[3].spd; } - } mupd->FspmTestConfig.DmiVc1 = 1; if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)) diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index 8b8a789..5408f35 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -19,6 +19,7 @@ def_bool y select BOARD_ROMSIZE_KB_4096 select CONSOLE_SERIAL + select DIMM_SPD_SMBUS select DRIVERS_UART select GENERIC_SPD_BIN select HAVE_ACPI_RESUME diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index 49fa5e3..95abd61 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -26,6 +26,8 @@ #include <soc/romstage.h> #include "spd/spd.h" #include <spd_bin.h> +#include <stdint.h> +#include <stddef.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> @@ -50,16 +52,16 @@ struct romstage_params *params, MEMORY_INIT_UPD *memory_params) { - struct spd_block blk = { - .addr_map = { 0x50, 0x52, }, - }; + struct spd_binfo spd_info = SPD_BINFO_SMBUS2(0x50, 0x52); + const ssize_t common_len = gather_spds(&spd_info); + if (common_len <= 0) + die("Failed to read valid SPD(s) from SMBus.\n"); + dump_spd_info(&spd_info); + printk(BIOS_SPEW, "spd block length: 0x%08x\n", common_len); - get_spd_smbus(&blk); - dump_spd_info(&blk); - printk(BIOS_SPEW, "spd block length: 0x%08x\n", blk.len); - - memory_params->MemorySpdPtr00 = (UINT32) blk.spd_array[0]; - memory_params->MemorySpdPtr10 = (UINT32) blk.spd_array[2]; + memory_params->MemorySpdDataLen = common_len; + memory_params->MemorySpdPtr00 = (uintptr_t)spd_info.spds[0].spd; + memory_params->MemorySpdPtr10 = (uintptr_t)spd_info.spds[1].spd; printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n", memory_params->MemorySpdPtr00); printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n", @@ -83,7 +85,5 @@ memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget, sizeof(params->pei_data->RcompTarget)); - /* update spd length*/ - memory_params->MemorySpdDataLen = blk.len; memory_params->DqPinsInterleaved = TRUE; } diff --git a/src/mainboard/kontron/bsl6/Kconfig b/src/mainboard/kontron/bsl6/Kconfig index c7604a0..079dedd 100644 --- a/src/mainboard/kontron/bsl6/Kconfig +++ b/src/mainboard/kontron/bsl6/Kconfig @@ -18,6 +18,7 @@ select MAINBOARD_HAS_LIBGFXINIT select DRIVERS_I2C_NCT7802Y select DRIVERS_I2C_LM96000 + select DIMM_SPD_SMBUS config MAINBOARD_DIR string diff --git a/src/mainboard/kontron/bsl6/romstage.c b/src/mainboard/kontron/bsl6/romstage.c index efd3186..4c36f36 100644 --- a/src/mainboard/kontron/bsl6/romstage.c +++ b/src/mainboard/kontron/bsl6/romstage.c @@ -13,9 +13,11 @@ * GNU General Public License for more details. */ +#include <stddef.h> #include <stdint.h> #include <string.h> #include <assert.h> +#include <console/console.h> #include <spd_bin.h> #include <soc/romstage.h> #include <fsp/soc_binding.h> @@ -37,17 +39,17 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *const memory_params = &mupd->FspmConfig; - struct spd_block blk = { - .addr_map = { 0x50, 0x52 }, - }; + struct spd_binfo spd_info = SPD_BINFO_SMBUS2(0x50, 0x52); assert(sizeof(memory_params->RcompResistor) == sizeof(rcomp_resistors)); assert(sizeof(memory_params->RcompTarget) == sizeof(rcomp_targets)); - memory_params->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; - get_spd_smbus(&blk); - memory_params->MemorySpdPtr00 = (u32)blk.spd_array[0]; - memory_params->MemorySpdPtr10 = (u32)blk.spd_array[1]; + const ssize_t common_len = gather_spds(&spd_info); + if (common_len <= 0) + die("Failed to read valid SPD(s) from SMBus.\n"); + memory_params->MemorySpdDataLen = common_len; + memory_params->MemorySpdPtr00 = (uintptr_t)spd_info.spds[0].spd; + memory_params->MemorySpdPtr10 = (uintptr_t)spd_info.spds[1].spd; memcpy(memory_params->RcompResistor, rcomp_resistors, sizeof(memory_params->RcompResistor)); diff --git a/src/mainboard/purism/librem_skl/Kconfig b/src/mainboard/purism/librem_skl/Kconfig index be4b7a3..7ad68dd 100644 --- a/src/mainboard/purism/librem_skl/Kconfig +++ b/src/mainboard/purism/librem_skl/Kconfig @@ -8,6 +8,7 @@ # Workaround for EC/KBC IRQ1 select SERIRQ_CONTINUOUS_MODE select MAINBOARD_USES_FSP2_0 + select DIMM_SPD_SMBUS select SPD_READ_BY_WORD select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/purism/librem_skl/romstage.c b/src/mainboard/purism/librem_skl/romstage.c index 48db885..a6800a7 100644 --- a/src/mainboard/purism/librem_skl/romstage.c +++ b/src/mainboard/purism/librem_skl/romstage.c @@ -16,8 +16,11 @@ * GNU General Public License for more details. */ +#include <stddef.h> +#include <stdint.h> #include <string.h> #include <assert.h> +#include <console/console.h> #include <soc/romstage.h> #include <spd_bin.h> #include "pei_data.h" @@ -25,15 +28,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *mem_cfg; - struct spd_block blk = { - .addr_map = { 0x50 }, - }; + struct spd_binfo spd_info = SPD_BINFO_SMBUS(0x50); mem_cfg = &mupd->FspmConfig; - get_spd_smbus(&blk); - dump_spd_info(&blk); - assert(blk.spd_array[0][0] != 0); + const ssize_t common_len = gather_spds(&spd_info); + if (common_len <= 0) + die("Failed to read SPD from SMBus.\n"); + dump_spd_info(&spd_info); mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); @@ -41,6 +43,6 @@ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); mem_cfg->DqPinsInterleaved = TRUE; - mem_cfg->MemorySpdDataLen = blk.len; - mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; + mem_cfg->MemorySpdDataLen = common_len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)spd_info.spds[0].spd; } diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 9452b6d..c8493fb 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -190,6 +190,7 @@ config SOC_INTEL_CANNONLAKE_MEMCFG_INIT bool default n + select GENERIC_SPD_BIN config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int diff --git a/src/soc/intel/cannonlake/cnl_memcfg_init.c b/src/soc/intel/cannonlake/cnl_memcfg_init.c index 4425862..87199cf 100644 --- a/src/soc/intel/cannonlake/cnl_memcfg_init.c +++ b/src/soc/intel/cannonlake/cnl_memcfg_init.c @@ -17,6 +17,8 @@ #include <fsp/util.h> #include <soc/cnl_memcfg_init.h> #include <spd_bin.h> +#include <stddef.h> +#include <stdint.h> #include <string.h> static void meminit_memcfg(FSP_M_CONFIG *mem_cfg, @@ -48,82 +50,25 @@ sizeof(mem_cfg->RcompTarget)); } -static void meminit_memcfg_spd(FSP_M_CONFIG *mem_cfg, - const struct cnl_mb_cfg *board_cfg, - size_t spd_data_len, uintptr_t spd_data_ptr) -{ - mem_cfg->MemorySpdDataLen = spd_data_len; - mem_cfg->MemorySpdPtr00 = spd_data_ptr; - - /* Use the same spd data for channel 1, Dimm 0 */ - mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; -} - -/* - * Initialize default memory settings using spd data contained in a buffer. - */ -static void meminit_spd_data(FSP_M_CONFIG *mem_cfg, - const struct cnl_mb_cfg *cnl_cfg, - size_t spd_data_len, uintptr_t spd_data_ptr) -{ - assert(spd_data_ptr && spd_data_len); - meminit_memcfg_spd(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr); -} - -/* - * Initialize default memory settings using the spd file specified by - * spd_index. The spd_index is an index into the SPD_SOURCES array defined - * in spd/Makefile.inc. - */ -static void meminit_cbfs_spd_index(FSP_M_CONFIG *mem_cfg, - const struct cnl_mb_cfg *cnl_cfg, - int spd_index) -{ - size_t spd_data_len; - uintptr_t spd_data_ptr; - struct region_device spd_rdev; - - printk(BIOS_DEBUG, "SPD INDEX = %d\n", spd_index); - if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) - die("spd.bin not found or incorrect index\n"); - spd_data_len = region_device_sz(&spd_rdev); - /* Memory leak is ok since we have memory mapped boot media */ - assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); - spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); - meminit_spd_data(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr); -} - /* Initialize onboard memory configurations for CannonLake */ void cannonlake_memcfg_init(FSP_M_CONFIG *mem_cfg, const struct cnl_mb_cfg *cnl_cfg, - const struct spd_info *spd) + struct spd_binfo *spd_info) { - bool OnModuleSpd = false; /* Early Command Training Enabled */ mem_cfg->ECT = cnl_cfg->ect; mem_cfg->DqPinsInterleaved = cnl_cfg->dq_pins_interleaved; mem_cfg->CaVrefConfig = cnl_cfg->vref_ca_config; - /* Spd pointer will only be used if all smbus slave address of memory - * sockets on the platform is empty */ - for (int i = 0; i < ARRAY_SIZE(mem_cfg->SpdAddressTable); i++) { - if (spd->spd_smbus_address[i] != 0) { - mem_cfg->SpdAddressTable[i] = spd->spd_smbus_address[i]; - OnModuleSpd = true; - } - } + const ssize_t common_len = gather_spds(spd_info); + if (common_len <= 0) + die("Failed to read valid SPD(s).\n"); - if (!OnModuleSpd) { - if (spd->spd_by_index) { - meminit_cbfs_spd_index(mem_cfg, cnl_cfg, - spd->spd_spec.spd_index); - } else { - meminit_spd_data(mem_cfg, cnl_cfg, - spd->spd_spec.spd_data_ptr_info.spd_data_len, - spd->spd_spec.spd_data_ptr_info.spd_data_ptr); - } - } + mem_cfg->MemorySpdDataLen = common_len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)spd_info->spds[0].spd; + mem_cfg->MemorySpdPtr01 = (uintptr_t)spd_info->spds[1].spd; + mem_cfg->MemorySpdPtr10 = (uintptr_t)spd_info->spds[2].spd; + mem_cfg->MemorySpdPtr11 = (uintptr_t)spd_info->spds[3].spd; meminit_memcfg(mem_cfg, cnl_cfg); - } diff --git a/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h index 245d2cf..6f2651c 100644 --- a/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h +++ b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h @@ -19,6 +19,7 @@ #include <stddef.h> #include <stdint.h> #include <fsp/soc_binding.h> +#include <spd_bin.h> /* Number of dq bits controlled per dqs */ #define DQ_BITS_PER_DQS 8 @@ -35,20 +36,6 @@ DDR_NUM_CHANNELS }; -struct spd_by_pointer { - size_t spd_data_len; - uintptr_t spd_data_ptr; -}; - -struct spd_info { - bool spd_by_index; - union spd_data_by { - int spd_index; - struct spd_by_pointer spd_data_ptr_info; - } spd_spec; - uint8_t spd_smbus_address[4]; -}; - /* Board-specific memory dq mapping information */ struct cnl_mb_cfg { /* @@ -110,6 +97,6 @@ */ void cannonlake_memcfg_init(FSP_M_CONFIG *mem_cfg, const struct cnl_mb_cfg *cnl_cfg, - const struct spd_info *spd); + struct spd_binfo *); #endif /* _SOC_CANNONLAKE_MEMCFG_INIT_H_ */ -- To view, visit https://review.coreboot.org/29481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iac300a374e5cd56a9d202cf24ad8fe8367b780d8 Gerrit-Change-Number: 29481 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

1 0

Change in coreboot[master]: [WIP] mb/kontron/bsl6: Add new Skylake COMe module
by Nico Huber (Code Review) 05 Nov '18

05 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29480 Change subject: [WIP] mb/kontron/bsl6: Add new Skylake COMe module ...................................................................... [WIP] mb/kontron/bsl6: Add new Skylake COMe module Add Kontron/bSL6 together with Siemens/Boxer26, a baseboard for the bSL6. Change-Id: If2b6a3f1e9dd095463f1f1521068b9f66a9189c5 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- A src/mainboard/kontron/bsl6/Kconfig A src/mainboard/kontron/bsl6/Kconfig.name A src/mainboard/kontron/bsl6/Makefile.inc A src/mainboard/kontron/bsl6/acpi/ec.asl A src/mainboard/kontron/bsl6/acpi/mainboard.asl A src/mainboard/kontron/bsl6/acpi/superio.asl A src/mainboard/kontron/bsl6/acpi_tables.c A src/mainboard/kontron/bsl6/board_info.txt A src/mainboard/kontron/bsl6/bootblock.c A src/mainboard/kontron/bsl6/cmos.default A src/mainboard/kontron/bsl6/cmos.layout A src/mainboard/kontron/bsl6/dsdt.asl A src/mainboard/kontron/bsl6/gpio.h A src/mainboard/kontron/bsl6/mainboard.c A src/mainboard/kontron/bsl6/ramstage.c A src/mainboard/kontron/bsl6/romstage.c A src/mainboard/kontron/bsl6/variant.h A src/mainboard/kontron/bsl6/variants/boxer26/boxer26_eeprom.h A src/mainboard/kontron/bsl6/variants/boxer26/devicetree.cb A src/mainboard/kontron/bsl6/variants/boxer26/gma-mainboard.ads A src/mainboard/kontron/bsl6/variants/boxer26/romstage.c A src/mainboard/kontron/bsl6/variants/boxer26/smbios.c A src/mainboard/kontron/bsl6/variants/bsl6/devicetree.cb A src/mainboard/kontron/bsl6/variants/bsl6/gma-mainboard.ads A src/mainboard/kontron/bsl6/variants/bsl6/romstage.c 25 files changed, 1,466 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/29480/1 diff --git a/src/mainboard/kontron/bsl6/Kconfig b/src/mainboard/kontron/bsl6/Kconfig new file mode 100644 index 0000000..c7604a0 --- /dev/null +++ b/src/mainboard/kontron/bsl6/Kconfig @@ -0,0 +1,61 @@ +if BOARD_KONTRON_BSL6 || BOARD_SIEMENS_BOXER26 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ROMSIZE_KB_16384 + select SOC_INTEL_SKYLAKE + select SKYLAKE_SOC_PCH_H + select EXCLUDE_NATIVE_SD_INTERFACE + select NO_FADT_8042 + select HAVE_ACPI_RESUME if BOARD_KONTRON_BSL6 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_USES_FSP2_0 + select SERIRQ_CONTINUOUS_MODE + select EC_KONTRON_KEMPLD + select MAINBOARD_HAS_LIBGFXINIT + select DRIVERS_I2C_NCT7802Y + select DRIVERS_I2C_LM96000 + +config MAINBOARD_DIR + string + default "kontron/bsl6" + +config MAINBOARD_PART_NUMBER + string + default "bSL6" if BOARD_KONTRON_BSL6 + default "Boxer26" if BOARD_SIEMENS_BOXER26 + +config VARIANT_DIR + string + default "bsl6" if BOARD_KONTRON_BSL6 + default "boxer26" if BOARD_SIEMENS_BOXER26 + +config DEVICETREE + string + default "variants/bsl6/devicetree.cb" if BOARD_KONTRON_BSL6 + default "variants/boxer26/devicetree.cb" if BOARD_SIEMENS_BOXER26 + +config MAX_CPUS + int + default 8 + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +endif + +if BOARD_SIEMENS_BOXER26 + +config MAINBOARD_VENDOR + string + default "Siemens" + +endif diff --git a/src/mainboard/kontron/bsl6/Kconfig.name b/src/mainboard/kontron/bsl6/Kconfig.name new file mode 100644 index 0000000..0f0577e --- /dev/null +++ b/src/mainboard/kontron/bsl6/Kconfig.name @@ -0,0 +1,5 @@ +config BOARD_KONTRON_BSL6 + bool "COMe-bSL6" + +config BOARD_SIEMENS_BOXER26 + bool "COMe-bSL6 on Siemens/Boxer26" diff --git a/src/mainboard/kontron/bsl6/Makefile.inc b/src/mainboard/kontron/bsl6/Makefile.inc new file mode 100644 index 0000000..74263f4 --- /dev/null +++ b/src/mainboard/kontron/bsl6/Makefile.inc @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 secunet Security Networks AG +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock.c + +romstage-y += variants/$(VARIANT_DIR)/romstage.c + +ramstage-y += mainboard.c +ramstage-y += ramstage.c + +ramstage-$(CONFIG_BOARD_SIEMENS_BOXER26) += variants/boxer26/smbios.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads diff --git a/src/mainboard/kontron/bsl6/acpi/ec.asl b/src/mainboard/kontron/bsl6/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/kontron/bsl6/acpi/ec.asl diff --git a/src/mainboard/kontron/bsl6/acpi/mainboard.asl b/src/mainboard/kontron/bsl6/acpi/mainboard.asl new file mode 100644 index 0000000..861d39f --- /dev/null +++ b/src/mainboard/kontron/bsl6/acpi/mainboard.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../gpio.h" + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + } +} diff --git a/src/mainboard/kontron/bsl6/acpi/superio.asl b/src/mainboard/kontron/bsl6/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/kontron/bsl6/acpi/superio.asl diff --git a/src/mainboard/kontron/bsl6/acpi_tables.c b/src/mainboard/kontron/bsl6/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/kontron/bsl6/acpi_tables.c diff --git a/src/mainboard/kontron/bsl6/board_info.txt b/src/mainboard/kontron/bsl6/board_info.txt new file mode 100644 index 0000000..f1db42f --- /dev/null +++ b/src/mainboard/kontron/bsl6/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Kontron +Board name: COMe-bSL6 +Category: come +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/kontron/bsl6/bootblock.c b/src/mainboard/kontron/bsl6/bootblock.c new file mode 100644 index 0000000..7f29158 --- /dev/null +++ b/src/mainboard/kontron/bsl6/bootblock.c @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <ec/kontron/kempld/kempld.h> + +void bootblock_mainboard_early_init(void) +{ + kempld_enable_uart_for_console(); +} diff --git a/src/mainboard/kontron/bsl6/cmos.default b/src/mainboard/kontron/bsl6/cmos.default new file mode 100644 index 0000000..09ada53 --- /dev/null +++ b/src/mainboard/kontron/bsl6/cmos.default @@ -0,0 +1,11 @@ +baud_rate = 115200 +debug_level = Info + +hyper_threading = Disable + +power_on_after_fail = Enable + +boot_devices = (hd0,0);(hd1,0) +boot_default = 0xff + +cmos_defaults_loaded = No diff --git a/src/mainboard/kontron/bsl6/cmos.layout b/src/mainboard/kontron/bsl6/cmos.layout new file mode 100644 index 0000000..2eda115 --- /dev/null +++ b/src/mainboard/kontron/bsl6/cmos.layout @@ -0,0 +1,133 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2015 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +#384 1 e 4 boot_option +#388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 2 baud_rate +395 4 e 3 debug_level +#399 1 r 0 unused + +# ----------------------------------------------------------------- +# coreboot config options: cpu +400 1 e 5 hyper_threading +#401 7 r 0 unused + +# coreboot config options: pch +408 2 e 4 power_on_after_fail +#410 30 r 0 unused + +# coreboot config options: mainboard +440 1 e 5 ethernet1 +441 1 e 5 ethernet2 +442 1 e 5 ethernet3 +#443 69 r 0 unused + +# payload config options +512 256 s 0 boot_devices +768 8 h 0 boot_default +776 1 e 1 cmos_defaults_loaded +#777 207 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 No +1 1 Yes +2 0 115200 +2 1 57600 +2 2 38400 +2 3 19200 +2 4 9600 +2 5 4800 +2 6 2400 +2 7 1200 +3 1 Emergency +3 2 Alert +3 3 Critical +3 4 Error +3 5 Warning +3 6 Notice +3 7 Info +3 8 Debug +3 9 Spew +4 0 Disable +4 1 Enable +4 2 Keep +5 0 Disable +5 1 Enable +# ----------------------------------------------------------------- +checksums + +checksum 392 983 984 diff --git a/src/mainboard/kontron/bsl6/dsdt.asl b/src/mainboard/kontron/bsl6/dsdt.asl new file mode 100644 index 0000000..6ef3856 --- /dev/null +++ b/src/mainboard/kontron/bsl6/dsdt.asl @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <soc/intel/skylake/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + // Chrome OS specific + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/kontron/bsl6/gpio.h b/src/mainboard/kontron/bsl6/gpio.h new file mode 100644 index 0000000..1880809 --- /dev/null +++ b/src/mainboard/kontron/bsl6/gpio.h @@ -0,0 +1,276 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* MAX98357A SD_MODE */ +#define GPIO_SPEAKER_MAXIM_AMP_SDMODE GPP_B2 + +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_C6 + +/* BIOS Flash Write Protect */ +#define GPIO_PCH_WP GPP_C23 + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C13 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_C15 + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */ +#define GPE_WLAN_WAKE GPE0_DW0_16 + +/* GPP_B5 is TOUCHPAD WAKE. GPP_B group is routed to DW0 in the GPE0 block */ +#define GPE_TOUCHPAD_WAKE GPE0_DW0_05 + +/* Input device interrupt configuration */ +#define TOUCHPAD_INT_L GPP_B3_IRQ +#define TOUCHSCREEN_INT_L GPP_E7_IRQ +#define MIC_INT_L GPP_F10_IRQ + +/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */ +#define EC_SCI_GPI GPE0_DW2_16 +#define EC_SMI_GPI GPP_E15 + +#ifndef __ACPI__ +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, PLTRST, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, PLTRST, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, PLTRST, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, PLTRST, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, PLTRST, NF1), +/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, PLTRST, NF1), +/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, PLTRST, NF1), +/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, NONE, PLTRST, OFF), +/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, PLTRST, NF1), +/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, 20K_PD, PLTRST, NF1), +/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, 20K_PD, PLTRST, NF1), +/* EC_HID_INT */ PAD_CFG_GPI_INT(GPP_A11, NONE, PLTRST, OFF), +/* ISH_KB_PROX_INT */ PAD_CFG_GPO(GPP_A12, 1, PLTRST), +/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), +/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), +/* SD_1P8_SEL */ PAD_CFG_GPI_INT(GPP_A16, NONE, PLTRST, OFF), +/* SD_PWR_EN */ PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, OFF), +/* ACCEL INTERRUPT */ PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), +/* ISH_GP1 */ PAD_CFG_GPI_INT(GPP_A19, NONE, PLTRST, OFF), +/* GYRO_DRDY */ PAD_CFG_GPO(GPP_A20, 1, DEEP), +/* FLIP_ACCEL_INT */ PAD_CFG_GPO(GPP_A21, 1, DEEP), +/* GYRO_INT */ PAD_CFG_GPO(GPP_A22, 1, DEEP), +/* ISH_GP5 */ PAD_CFG_GPI_INT(GPP_A23, NONE, PLTRST, OFF), + +/* CORE_VID0 */ PAD_CFG_GPI_INT(GPP_B0, NONE, PLTRST, OFF), +/* CORE_VID1 */ PAD_CFG_GPI_INT(GPP_B1, NONE, PLTRST, OFF), +/* HSJ_MIC_DET */ PAD_CFG_GPI_INT(GPP_B2, NONE, PLTRST, OFF), +/* TRACKPAD_INT */ PAD_CFG_GPO(GPP_B3, 1, DEEP), +/* BT_RF_KILL */ PAD_CFG_NF(GPP_B4, NONE, PLTRST, NF1), +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), +/* WIFI_CLK_REQ */ PAD_CFG_GPO(GPP_B6, 1, DEEP), +/* KEPLR_CLK_REQ */ PAD_CFG_GPO(GPP_B7, 1, DEEP), +/* SRCCLKREQ3# */ PAD_CFG_GPO(GPP_B8, 1, DEEP), +/* SSD_CLK_REQ */ PAD_CFG_GPO(GPP_B9, 1, DEEP), +/* SRCCLKREQ5# */ PAD_CFG_GPO(GPP_B10, 1, DEEP), +/* MPHY_EXT_PWR_GATE */ PAD_CFG_GPI_INT(GPP_B11, NONE, PLTRST, OFF), +/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* GPP_B_14_SPKR */ PAD_CFG_NF(GPP_B14, 20K_PD, PLTRST, NF1), +/* GSPI0_CS# */ PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, OFF), +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_INT(GPP_B16, NONE, PLTRST, OFF), +/* SSD_PCIE_WAKE */ PAD_CFG_GPO(GPP_B17, 1, DEEP), +/* GSPI0_MOSI */ PAD_CFG_GPI_INT(GPP_B18, NONE, PLTRST, OFF), +/* CCODEC_SPI_CS */ PAD_CFG_GPI_INT(GPP_B19, NONE, PLTRST, OFF), +/* CODEC_SPI_CLK */ PAD_CFG_GPI_INT(GPP_B20, NONE, PLTRST, OFF), +/* CODEC_SPI_MISO */ PAD_CFG_GPI_INT(GPP_B21, NONE, PLTRST, OFF), +/* CODEC_SPI_MOSI */ PAD_CFG_GPI_INT(GPP_B22, NONE, PLTRST, OFF), +/* SM1ALERT# */ PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PU, DEEP), + +/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_GPI_ACPI_SCI(GPP_C2, NONE, DEEP, YES), +/* M2_WWAN_PWREN */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), +/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), +/* SML0ALERT# */ PAD_CFG_GPI_INT(GPP_C5, NONE, PLTRST, OFF), +/* EC_IN_RW */ /* XXX: not readable */ +/* USB_CTL */ /* XXX: not readable */ +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, PLTRST, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, PLTRST, NF1), +/* NFC_RST* */ PAD_CFG_NF(GPP_C10, NONE, PLTRST, NF1), +/* EN_PP3300_KEPLER */ PAD_CFG_NF(GPP_C11, NONE, PLTRST, NF1), +/* PCH_MEM_CFG0 */ PAD_CFG_NF(GPP_C12, NONE, PLTRST, NF1), +/* PCH_MEM_CFG1 */ PAD_CFG_NF(GPP_C13, NONE, PLTRST, NF1), +/* PCH_MEM_CFG2 */ PAD_CFG_NF(GPP_C14, NONE, PLTRST, NF1), +/* PCH_MEM_CFG3 */ PAD_CFG_NF(GPP_C15, NONE, PLTRST, NF1), +/* I2C0_SDA */ PAD_CFG_GPI_INT(GPP_C16, NONE, PLTRST, OFF), +/* I2C0_SCL */ PAD_CFG_GPI_INT(GPP_C17, NONE, PLTRST, OFF), +/* I2C1_SDA */ PAD_CFG_GPI_INT(GPP_C18, NONE, PLTRST, OFF), +/* I2C1_SCL */ PAD_CFG_GPI_INT(GPP_C19, NONE, PLTRST, OFF), +/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, PLTRST, NF1), +/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, PLTRST, NF1), +/* TCH_PNL_PWREN */ PAD_CFG_NF(GPP_C22, NONE, PLTRST, NF1), +/* SPI_WP_STATUS */ PAD_CFG_NF(GPP_C23, NONE, PLTRST, NF1), + +/* ITCH_SPI_CS */ PAD_CFG_GPO(GPP_D0, 1, DEEP), +/* ITCH_SPI_CLK */ PAD_CFG_GPI_INT(GPP_D1, NONE, DEEP, OFF), +/* ITCH_SPI_MISO_1 */ PAD_CFG_GPI_INT(GPP_D2, NONE, DEEP, OFF), +/* ITCH_SPI_MISO_0 */ PAD_CFG_GPO(GPP_D3, 1, DEEP), +/* CAM_FLASH_STROBE */ PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, OFF), +/* EN_PP3300_DX_EMMC */ PAD_CFG_NF(GPP_D5, NONE, PLTRST, NF1), +/* EN_PP1800_DX_EMMC */ PAD_CFG_NF(GPP_D6, NONE, PLTRST, NF1), +/* SH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, PLTRST, NF1), +/* SH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, PLTRST, NF1), + PAD_CFG_GPO(GPP_D9, 0, DEEP), +/* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP), +/* USB_A1_ILIM_SEL */ PAD_CFG_GPI_SCI_HIGH(GPP_D11, NONE, DEEP, LEVEL), +/* EN_PP3300_DX_CAM */ PAD_CFG_GPI_SCI_HIGH(GPP_D12, NONE, DEEP, LEVEL), +/* EN_PP1800_DX_AUDIO */PAD_CFG_GPI_INT(GPP_D13, NONE, PLTRST, OFF), +/* ISH_UART0_TXD */ PAD_CFG_GPI_INT(GPP_D14, NONE, PLTRST, OFF), +/* ISH_UART0_RTS */ PAD_CFG_GPI_INT(GPP_D15, NONE, PLTRST, OFF), +/* ISH_UART0_CTS */ PAD_CFG_GPI_INT(GPP_D16, NONE, PLTRST, OFF), +/* DMIC_CLK_1 */ PAD_CFG_GPO(GPP_D17, 0, DEEP), +/* DMIC_DATA_1 */ PAD_CFG_GPI_INT(GPP_D18, NONE, DEEP, OFF), +/* DMIC_CLK_0 */ PAD_CFG_GPO(GPP_D19, 0, DEEP), +/* DMIC_DATA_0 */ PAD_CFG_GPO(GPP_D20, 0, DEEP), +/* ITCH_SPI_D2 */ PAD_CFG_GPO(GPP_D21, 1, DEEP), +/* ITCH_SPI_D3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), +/* I2S_MCLK */ PAD_CFG_GPI_INT(GPP_D23, NONE, PLTRST, OFF), + +/* SPI_TPM_IRQ */ PAD_CFG_NF(GPP_E0, 20K_PU, PLTRST, NF1), +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, 20K_PU, PLTRST, NF1), +/* SSD_PEDET */ PAD_CFG_GPI_INT(GPP_E2, NONE, PLTRST, OFF), +/* CPU_GP0 */ PAD_CFG_GPI_SCI_HIGH(GPP_E3, NONE, DEEP, LEVEL), +/* SSD_SATA_DEVSLP */ PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), +/* SATA_DEVSLP1 */ PAD_CFG_GPI_INT(GPP_E5, NONE, PLTRST, OFF), +/* SATA_DEVSLP2 */ PAD_CFG_GPI_INT(GPP_E6, NONE, PLTRST, OFF), +/* TCH_PNL_INTR* */ PAD_CFG_GPI_ACPI_SCI(GPP_E7, NONE, DEEP, YES), +/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, PLTRST, NF1), +/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), +/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), +/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + +/* I2S2_SCLK */ PAD_CFG_GPI_INT(GPP_F0, NONE, PLTRST, OFF), +/* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, 20K_PU, PLTRST, NF1), +/* I2S2_TXD */ PAD_CFG_NF(GPP_F2, NONE, PLTRST, NF1), +/* I2S2_RXD */ PAD_CFG_NF(GPP_F3, NONE, PLTRST, NF1), +/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, PLTRST, NF1), +/* I2C2_SCL */ PAD_CFG_GPI_ACPI_SCI(GPP_F5, NONE, DEEP, NONE), +/* I2C3_SDA */ PAD_CFG_NF(GPP_F6, NONE, PWROK, NF1), +/* I2C3_SCL */ PAD_CFG_GPI_INT(GPP_F7, NONE, PLTRST, OFF), +/* I2C4_SDA */ PAD_CFG_GPI_INT(GPP_F8, NONE, PLTRST, OFF), +/* I2C4_SCL */ PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), +/* I2C5_SCL */ PAD_CFG_GPI_INT(GPP_F11, NONE, PLTRST, OFF), +/* EMMC_CMD */ PAD_CFG_GPI_APIC_INVERT(GPP_F12, NONE, PLTRST), +/* EMMC_DATA0 */ PAD_CFG_GPI_APIC(GPP_F13, NONE, PLTRST), +/* EMMC_DATA1 */ PAD_CFG_GPI_APIC_INVERT(GPP_F14, NONE, DEEP), +/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), +/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), +/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), +/* EMMC_DATA5 */ PAD_CFG_GPO(GPP_F18, 1, PLTRST), +/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* EMMC_CLK */ PAD_CFG_GPO(GPP_F22, 1, PLTRST), + PAD_CFG_GPO(GPP_F23, 1, DEEP), + +/* SD_CMD */ PAD_CFG_GPO(GPP_G0, 1, PLTRST), +/* SD_DATA0 */ PAD_CFG_GPO(GPP_G1, 1, PLTRST), +/* SD_DATA1 */ PAD_CFG_GPI_SCI_LOW(GPP_G2, NONE, PLTRST, LEVEL), +/* SD_DATA2 */ PAD_CFG_GPI_SCI_LOW(GPP_G3, NONE, PLTRST, LEVEL), +/* SD_DATA3 */ PAD_CFG_GPO(GPP_G4, 1, DEEP), +/* SD_CD# */ PAD_CFG_GPI_APIC(GPP_G5, NONE, PLTRST), +/* SD_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_G6, NONE, PLTRST, YES), +/* SD_WP */ PAD_CFG_GPO(GPP_G7, 1, DEEP), + PAD_CFG_GPI_INT(GPP_G8, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G9, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G10, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G11, NONE, PLTRST, OFF), + PAD_CFG_GPI_ACPI_SCI(GPP_G12, 20K_PD, PLTRST, YES), + PAD_CFG_GPO(GPP_G13, 1, PLTRST), + PAD_CFG_GPI_ACPI_SCI(GPP_G14, NONE, PLTRST, YES), + PAD_CFG_GPO(GPP_G15, 0, PLTRST), + PAD_CFG_TERM_GPO(GPP_G16, 1, 20K_PD, PLTRST), + PAD_CFG_GPI_INT(GPP_G17, NONE, PLTRST, OFF), + PAD_CFG_GPI_APIC(GPP_G18, NONE, PLTRST), + PAD_CFG_NF(GPP_G19, NONE, PLTRST, NF1), + PAD_CFG_GPI_APIC(GPP_G20, NONE, PLTRST), + PAD_CFG_GPI_ACPI_SCI(GPP_G21, NONE, DEEP, YES), + PAD_CFG_GPO(GPP_G22, 1, PLTRST), + PAD_CFG_GPO(GPP_G23, 1, PLTRST), + + PAD_CFG_GPO(GPP_H0, 1, DEEP), + PAD_CFG_GPO(GPP_H1, 1, DEEP), + PAD_CFG_GPO(GPP_H2, 1, DEEP), + PAD_CFG_GPO(GPP_H3, 1, DEEP), + PAD_CFG_GPO(GPP_H4, 1, DEEP), + PAD_CFG_GPO(GPP_H5, 1, DEEP), + PAD_CFG_GPO(GPP_H6, 1, DEEP), + PAD_CFG_GPO(GPP_H7, 1, DEEP), + PAD_CFG_GPO(GPP_H8, 1, DEEP), + PAD_CFG_GPO(GPP_H9, 1, DEEP), + PAD_CFG_GPI_INT(GPP_H10, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H11, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H12, NONE, PLTRST, OFF), + PAD_CFG_GPI_APIC(GPP_H13, NONE, PLTRST), + PAD_CFG_GPI_APIC(GPP_H14, NONE, PLTRST), + PAD_CFG_GPI_APIC(GPP_H15, NONE, PLTRST), + PAD_CFG_GPI_INT(GPP_H16, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_H17, 1, PLTRST), + PAD_CFG_GPI_INT(GPP_H18, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H19, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H20, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H21, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_H22, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_H23, 0, DEEP), + +/* PCH_BATLOW */ PAD_CFG_GPI_INT(GPD0, NONE, PLTRST, OFF), +/* EC_PCH_ACPRESENT */ PAD_CFG_GPO(GPD1, 0, PWROK), +/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, PWROK, NF1), +/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, 20K_PU, PWROK, NF1), +/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), +/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), +/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_CFG_GPO(GPD7, 1, PWROK), +/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), +/* PCH_SLP_WLAN# */ PAD_CFG_GPO(GPD9, 0, PWROK), +/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), +/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), + + PAD_CFG_NF(GPP_I0, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I5, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I6, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I7, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I8, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I9, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_I10, NONE, PLTRST, NF1), +}; + +#endif + +#endif diff --git a/src/mainboard/kontron/bsl6/mainboard.c b/src/mainboard/kontron/bsl6/mainboard.c new file mode 100644 index 0000000..dcd5a29 --- /dev/null +++ b/src/mainboard/kontron/bsl6/mainboard.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> + +static void mainboard_init(device_t dev) +{ +} + +/* + * mainboard_enable is executed as first thing after + * enumerate_buses(). + */ +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/kontron/bsl6/ramstage.c b/src/mainboard/kontron/bsl6/ramstage.c new file mode 100644 index 0000000..44fb9cd --- /dev/null +++ b/src/mainboard/kontron/bsl6/ramstage.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/kontron/bsl6/romstage.c b/src/mainboard/kontron/bsl6/romstage.c new file mode 100644 index 0000000..efd3186 --- /dev/null +++ b/src/mainboard/kontron/bsl6/romstage.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <assert.h> +#include <spd_bin.h> +#include <soc/romstage.h> +#include <fsp/soc_binding.h> +#include <pc80/mc146818rtc.h> + +#include "variant.h" + +/* TODO: DQ byte map only applies to LPDDR3? */ + +/* TODO: Does DQS CPU<>DRAM map apply to DDR4? */ + +/* Rcomp resistor */ +static const u16 rcomp_resistors[3] = { 121, 75, 100 }; + +/* Rcomp target */ +/* TODO: values are from Saddle Brook RVP */ +static const u16 rcomp_targets[5] = { 100, 40, 20, 20, 26 }; + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *const memory_params = &mupd->FspmConfig; + struct spd_block blk = { + .addr_map = { 0x50, 0x52 }, + }; + + assert(sizeof(memory_params->RcompResistor) == sizeof(rcomp_resistors)); + assert(sizeof(memory_params->RcompTarget) == sizeof(rcomp_targets)); + + memory_params->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; + get_spd_smbus(&blk); + memory_params->MemorySpdPtr00 = (u32)blk.spd_array[0]; + memory_params->MemorySpdPtr10 = (u32)blk.spd_array[1]; + + memcpy(memory_params->RcompResistor, rcomp_resistors, + sizeof(memory_params->RcompResistor)); + memcpy(memory_params->RcompTarget, rcomp_targets, + sizeof(memory_params->RcompTarget)); + + memory_params->DqPinsInterleaved = true; + + get_option(&memory_params->HyperThreading, "hyper_threading"); + + variant_memory_init_params(mupd); +} diff --git a/src/mainboard/kontron/bsl6/variant.h b/src/mainboard/kontron/bsl6/variant.h new file mode 100644 index 0000000..773278d --- /dev/null +++ b/src/mainboard/kontron/bsl6/variant.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_H +#define VARIANT_H + +#include <fsp/soc_binding.h> + +void variant_memory_init_params(FSPM_UPD *); + +#endif diff --git a/src/mainboard/kontron/bsl6/variants/boxer26/boxer26_eeprom.h b/src/mainboard/kontron/bsl6/variants/boxer26/boxer26_eeprom.h new file mode 100644 index 0000000..f39a7ce --- /dev/null +++ b/src/mainboard/kontron/bsl6/variants/boxer26/boxer26_eeprom.h @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _BOXER26_EEPROM_H +#define _BOXER26_EEPROM_H + +#include <stdint.h> + +enum boxer26_strings { + BOARD_MATNR, + BOARD_SERIAL_NUMBER, + BOARD_VERSION, + BOARD_MCTRL_FW_VERSION, + BOARD_CCR_FW_VERSION, + BOARD_NIC_FW_VERSION, + BOARD_LP_VERSION, + BOARD_VERSION_ID, + + SYSTEM_PRODUCT_NAME, + SYSTEM_VERSION, + SYSTEM_SERIAL_NUMBER, + SYSTEM_UUID, + SYSTEM_MANUFACTURER, + SYSTEM_PRODUCTION_DATE, + SYSTEM_MLFB, + SYSTEM_MATNR, +}; + +struct boxer26_location { + uint16_t offset; + uint16_t length; +}; + +static const struct boxer26_location boxer26_locations[] = { + [BOARD_MATNR] = { 0x0000, 0x20 }, + [BOARD_SERIAL_NUMBER] = { 0x0020, 0x20 }, + [BOARD_VERSION] = { 0x0040, 0x20 }, + [BOARD_MCTRL_FW_VERSION] = { 0x0060, 0x20 }, + [BOARD_CCR_FW_VERSION] = { 0x0080, 0x20 }, + [BOARD_NIC_FW_VERSION] = { 0x00a0, 0x20 }, + [BOARD_LP_VERSION] = { 0x00c0, 0x20 }, + [BOARD_VERSION_ID] = { 0x0100, 0x20 }, + + [SYSTEM_PRODUCT_NAME] = { 0x4000, 0x20 }, + [SYSTEM_VERSION] = { 0x4040, 0x10 }, + [SYSTEM_SERIAL_NUMBER] = { 0x4060, 0x10 }, + [SYSTEM_UUID] = { 0x4080, 0x24 }, + [SYSTEM_MANUFACTURER] = { 0x40c0, 0x20 }, + [SYSTEM_PRODUCTION_DATE] = { 0x4100, 0x20 }, + [SYSTEM_MLFB] = { 0x4140, 0x20 }, + [SYSTEM_MATNR] = { 0x4180, 0x20 }, +}; + +#endif diff --git a/src/mainboard/kontron/bsl6/variants/boxer26/devicetree.cb b/src/mainboard/kontron/bsl6/variants/boxer26/devicetree.cb new file mode 100644 index 0000000..9884514 --- /dev/null +++ b/src/mainboard/kontron/bsl6/variants/boxer26/devicetree.cb @@ -0,0 +1,206 @@ +chip soc/intel/skylake + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ11" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # EC/kempld at 0xa80/0xa81 + register "gen1_dec" = "0x00000a81" + + register "speed_shift_enable" = "1" + + register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" + + # FSP Configuration + register "SmbusEnable" = "1" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" # KBL FSP only, XXX unused? + register "FspSkipMpInit" = "1" + + register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" + register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" + register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" + register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" + + register "PmConfigPciClockRun" = "1" + + register "PmConfigPwrCycDur" = "RESET_POWER_CYCLE_4S" + + register "SerialIrqConfigSirqEnable" = "1" + register "SerialIrqConfigSirqMode" = "SERIAL_IRQ_CONTINUOUS_MODE" + + # VR Settings Configuration for 2 Domains + #+----------------+-------+-------+ + #| Domain/Setting | VCC | VCCGT | + #+----------------+-------+-------+ + #| Psi1Threshold | 20A | 20A | + #| Psi2Threshold | 5A | 5A | + #| Psi3Threshold | 1A | 1A | + #| Psi3Enable | 1 | 1 | + #| Psi4Enable | 1 | 1 | + #| ImonSlope | 0 | 0 | + #| ImonOffset | 0 | 0 | + #| IccMax | 55A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | + #| AcLoadline | 2.1 | 3.1 | + #| DcLoadline | 2.1 | 3.1 | + #+----------------+-------+-------+ + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(55), + .voltage_limit = 1520, + .ac_loadline = 210, + .dc_loadline = 210, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + # Vendor set Psys Pmax to 30W + register "psys_pmax" = "30" + + # Enable Root ports 9..11 (COMe 0..2) + register "PcieRpEnable[ 8]" = "1" + register "PcieRpEnable[ 9]" = "1" + register "PcieRpEnable[10]" = "1" + + register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" + register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" + register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" + register "usb2_ports[3]" = "USB2_PORT_LONG(OC1)" + register "usb2_ports[4]" = "USB2_PORT_LONG(OC2)" # Debug + + register "EnableSata" = "1" + register "SataMode" = "KBLFSP_SATA_MODE_AHCI" + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" # Debug + # SataPortsDevSlp not supported + + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + + # TODO: only needed if short term +25% is bad + # PL2 override 25W + #register "tdp_pl2_override" = "25" + + # TODO + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 08.0 on end # Gaussion Mixture Model + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 19.0 off end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # I2C #4 + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.2 on end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip ec/kontron/kempld + register "uart[0]" = "{ KEMPLD_UART_3F8, 4 }" + device generic 0.0 on end # UART #0 + device generic 1.0 on # I2C + chip drivers/i2c/lm96000 + register "vin[1].low" = "1140*100/116" + register "vin[1].high" = "1260*100/116" + register "vin[0].low" = "1810" + register "vin[0].high" = "2000" + register "vin[2].low" = "3140" + register "vin[2].high" = "3470" + register "vin[3].low" = "4750" + register "vin[3].high" = "5250" + register "vin[4].low" = "11400" + register "vin[4].high" = "12600" + + register "fan_in[0].low" = "3240" + register "fan_in[1].low" = "3240" + + register "fan[0].mode" = "LM96000_FAN_MANUAL" + register "fan[0].spinup" = "LM96000_SPINUP_250MS" + register "fan[0].freq" = "LM96000_PWM_25_7KHZ" + register "fan[0].duty_cycle" = "100" + + register "fan[1].mode" = "LM96000_FAN_MANUAL" + register "fan[1].spinup" = "LM96000_SPINUP_250MS" + register "fan[1].freq" = "LM96000_PWM_25_7KHZ" + register "fan[1].duty_cycle" = "100" + + device i2c 0x2c on end + end + device i2c 0x57 on end # Serial EEPROM + end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 off end # Intel HDA + device pci 1f.4 on # SMBus + chip drivers/i2c/nct7802y + register "fan[1].mode" = "FAN_MANUAL" + register "fan[1].duty_cycle" = "100" + device i2c 0x2e on end + end + end + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE # Debug + end +end diff --git a/src/mainboard/kontron/bsl6/variants/boxer26/gma-mainboard.ads b/src/mainboard/kontron/bsl6/variants/boxer26/gma-mainboard.ads new file mode 100644 index 0000000..7dcfb0a --- /dev/null +++ b/src/mainboard/kontron/bsl6/variants/boxer26/gma-mainboard.ads @@ -0,0 +1,11 @@ +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := (DP2, HDMI2, others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c b/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c new file mode 100644 index 0000000..e1d0bea --- /dev/null +++ b/src/mainboard/kontron/bsl6/variants/boxer26/romstage.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <console/console.h> +#include <pc80/mc146818rtc.h> +#include <fsp/soc_binding.h> + +#include "../../variant.h" + +void variant_memory_init_params(FSPM_UPD *const mupd) +{ + char nvram_var[] = "ethernetx"; + unsigned int i; + + for (i = 0; i < 3; ++i) { + u8 eth_enable = 1; + nvram_var[sizeof(nvram_var) - 2] = '1' + i; + get_option(&eth_enable, nvram_var); + if (!eth_enable) { + printk(BIOS_DEBUG, "Disabling ethernet%u.\n", 1 + i); + mupd->FspmConfig.PcieRpEnableMask &= ~(1 << (i + 8)); + } + } +} diff --git a/src/mainboard/kontron/bsl6/variants/boxer26/smbios.c b/src/mainboard/kontron/bsl6/variants/boxer26/smbios.c new file mode 100644 index 0000000..361e817 --- /dev/null +++ b/src/mainboard/kontron/bsl6/variants/boxer26/smbios.c @@ -0,0 +1,156 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <commonlib/helpers.h> +#include <commonlib/endian.h> +#include <lib.h> +#include <console/console.h> +#include <device/device.h> +#include <device/i2c_bus.h> +#include <smbios.h> + +#include "boxer26_eeprom.h" + +#define MAX_STRING_LENGTH 256 + +static const char *eeprom_read_string(const enum boxer26_strings idx) +{ + static char str[MAX_STRING_LENGTH + 1]; + + struct device *const dev = dev_find_slot_on_smbus(1, 0x57); + if (!dev) { + printk(BIOS_WARNING, "Boxer26: Serial EEPROM not found\n"); + str[0] = '\0'; + return str; + } + + const u16 offset = boxer26_locations[idx].offset; + const u16 length = MIN(boxer26_locations[idx].length, + MAX_STRING_LENGTH); + + if (i2c_dev_readb_at_word(dev, (u8 *)str, length, offset) != length) { + printk(BIOS_WARNING, "Boxer26: Failed to read serial EEPROM\n"); + str[0] = '\0'; + } else { + u16 i; + /* Terminate at first non-printable character. */ + for (i = 0; i < length; ++i) { + if (!isprint(str[i])) + break; + } + str[i] = '\0'; + } + + return str; +} + +const char *smbios_system_manufacturer(void) +{ + return eeprom_read_string(SYSTEM_MANUFACTURER); +} + +const char *smbios_system_product_name(void) +{ + return eeprom_read_string(SYSTEM_PRODUCT_NAME); +} + +const char *smbios_system_serial_number(void) +{ + return eeprom_read_string(SYSTEM_SERIAL_NUMBER); +} + +const char *smbios_system_version(void) +{ + return eeprom_read_string(SYSTEM_VERSION); +} + +static int parse_uuid_word16(u8 **const uuid_dst, const char **const uuid_str, + const int le) +{ + u8 buf[2]; + + if (hexstrtobin(*uuid_str, buf, sizeof(buf)) != sizeof(buf)) + return -1; + if (le) + write_le16(*uuid_dst, read_be16(buf)); + else + memcpy(*uuid_dst, buf, sizeof(buf)); + *uuid_dst += sizeof(buf); + *uuid_str += 2 * sizeof(buf); + + if (**uuid_str != '-') + return -1; + ++*uuid_str; + + return 0; +} + +static int parse_uuid_word32(u8 **const uuid_dst, const char **const uuid_str) +{ + u8 buf[4]; + + if (hexstrtobin(*uuid_str, buf, sizeof(buf)) != sizeof(buf)) + return -1; + write_le32(*uuid_dst, read_be32(buf)); + *uuid_dst += sizeof(buf); + *uuid_str += 2 * sizeof(buf); + + if (**uuid_str != '-') + return -1; + ++*uuid_str; + + return 0; +} + +static int parse_uuid(u8 *uuid, const char *uuid_str) +{ + unsigned int i; + + if (strlen(uuid_str) != 36) + return -1; + if (parse_uuid_word32(&uuid, &uuid_str)) + return -1; + if (parse_uuid_word16(&uuid, &uuid_str, 1)) + return -1; + if (parse_uuid_word16(&uuid, &uuid_str, 1)) + return -1; + if (parse_uuid_word16(&uuid, &uuid_str, 0)) + return -1; + for (i = 0; i < 6; ++i, ++uuid, uuid_str += 2) { + uint8_t tmp; + if (hexstrtobin(uuid_str, &tmp, sizeof(tmp)) != 1) + return -1; + *uuid = tmp; + } + return 0; +} + +void smbios_system_set_uuid(u8 *const uuid) +{ + if (parse_uuid(uuid, eeprom_read_string(SYSTEM_UUID))) { + printk(BIOS_WARNING, "Boxer26: Cannot parse UUID\n"); + memset(uuid, 0x00, 16); + } +} + +const char *smbios_mainboard_serial_number(void) +{ + return eeprom_read_string(BOARD_SERIAL_NUMBER); +} + +const char *smbios_mainboard_version(void) +{ + return eeprom_read_string(BOARD_VERSION); +} diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/variants/bsl6/devicetree.cb new file mode 100644 index 0000000..76a556d --- /dev/null +++ b/src/mainboard/kontron/bsl6/variants/bsl6/devicetree.cb @@ -0,0 +1,198 @@ +chip soc/intel/skylake + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ11" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # EC/kempld at 0xa80/0xa81 + register "gen1_dec" = "0x00000a81" + + register "speed_shift_enable" = "1" + + register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" + + # FSP Configuration + register "SmbusEnable" = "1" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" # KBL FSP only, XXX unused? + register "FspSkipMpInit" = "1" + + register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" + register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" + register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" + register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" + + register "PmConfigPciClockRun" = "1" + + register "PmConfigPwrCycDur" = "RESET_POWER_CYCLE_4S" + + register "SerialIrqConfigSirqEnable" = "1" + register "SerialIrqConfigSirqMode" = "SERIAL_IRQ_CONTINUOUS_MODE" + + # VR Settings Configuration for 2 Domains + #+----------------+-------+-------+ + #| Domain/Setting | VCC | VCCGT | + #+----------------+-------+-------+ + #| Psi1Threshold | 20A | 20A | + #| Psi2Threshold | 5A | 5A | + #| Psi3Threshold | 1A | 1A | + #| Psi3Enable | 1 | 1 | + #| Psi4Enable | 1 | 1 | + #| ImonSlope | 0 | 0 | + #| ImonOffset | 0 | 0 | + #| IccMax | 55A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | + #| AcLoadline | 2.1 | 3.1 | + #| DcLoadline | 2.1 | 3.1 | + #+----------------+-------+-------+ + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(55), + .voltage_limit = 1520, + .ac_loadline = 210, + .dc_loadline = 210, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + # Vendor set Psys Pmax to 30W + register "psys_pmax" = "30" + + # Enable Root port 1..4 (COMe 4..7), 9..12 (COMe 0..3) + register "PcieRpEnable[ 0]" = "1" + register "PcieRpEnable[ 1]" = "1" + register "PcieRpEnable[ 2]" = "1" + register "PcieRpEnable[ 3]" = "1" + register "PcieRpEnable[ 8]" = "1" + register "PcieRpEnable[ 9]" = "1" + register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[11]" = "1" + + register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" + register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" + register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" + register "usb2_ports[3]" = "USB2_PORT_LONG(OC1)" + register "usb2_ports[4]" = "USB2_PORT_LONG(OC2)" + register "usb2_ports[5]" = "USB2_PORT_LONG(OC2)" + register "usb2_ports[6]" = "USB2_PORT_LONG(OC3)" + register "usb2_ports[7]" = "USB2_PORT_LONG(OC3)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC4)" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" + + register "EnableSata" = "1" + register "SataMode" = "KBLFSP_SATA_MODE_AHCI" + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + # SataPortsDevSlp not supported + + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + + # TODO: only needed if short term +25% is bad + # PL2 override 25W + #register "tdp_pl2_override" = "25" + + # TODO + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 08.0 on end # Gaussion Mixture Model + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 19.0 off end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # I2C #4 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 on end # PCI Express Port 2 + device pci 1c.2 on end # PCI Express Port 3 + device pci 1c.3 on end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.2 on end # PCI Express Port 11 + device pci 1d.3 on end # PCI Express Port 12 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip ec/kontron/kempld + register "uart[0]" = "{ KEMPLD_UART_3F8, 4 }" + device generic 0.0 on end # UART #0 + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 off end # Intel HDA + device pci 1f.4 on # SMBus + chip drivers/i2c/nct7802y + register "peci[0]" = "{ PECI_DOMAIN_0, 100 }" + register "fan[1].mode" = "FAN_SMART" + register "fan[1].smart.mode" = "SMART_FAN_DUTY" + register "fan[1].smart.tempsrc" = "TEMP_SOURCE_PECI_0" + register "fan[1].smart.table" = "{ { 30, 40 }, + { 40, 48 }, + { 50, 60 }, + { 60, 76 } }" + register "fan[1].smart.critical_temp" = "80" + device i2c 0x2e on end + end + end + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/gma-mainboard.ads b/src/mainboard/kontron/bsl6/variants/bsl6/gma-mainboard.ads new file mode 100644 index 0000000..11ec840 --- /dev/null +++ b/src/mainboard/kontron/bsl6/variants/bsl6/gma-mainboard.ads @@ -0,0 +1,19 @@ +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/romstage.c b/src/mainboard/kontron/bsl6/variants/bsl6/romstage.c new file mode 100644 index 0000000..b37dbb6 --- /dev/null +++ b/src/mainboard/kontron/bsl6/variants/bsl6/romstage.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/soc_binding.h> + +#include "../../variant.h" + +void variant_memory_init_params(FSPM_UPD *const mupd) +{ +} -- To view, visit https://review.coreboot.org/29480 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If2b6a3f1e9dd095463f1f1521068b9f66a9189c5 Gerrit-Change-Number: 29480 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

1 0

Change in coreboot[master]: string.h: Add isprint()
by Nico Huber (Code Review) 05 Nov '18

05 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29479 Change subject: string.h: Add isprint() ...................................................................... string.h: Add isprint() Change-Id: If179687f0a15cf5b16723ad18d8eb86a2d5fa48d Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/include/string.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/29479/1 diff --git a/src/include/string.h b/src/include/string.h index fc96393..2f6b5f1 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -156,6 +156,11 @@ } } +static inline int isprint(int c) +{ + return c >= ' ' && c <= '~'; +} + static inline int isdigit(int c) { return (c >= '0' && c <= '9'); -- To view, visit https://review.coreboot.org/29479 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If179687f0a15cf5b16723ad18d8eb86a2d5fa48d Gerrit-Change-Number: 29479 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

1 0

Change in coreboot[master]: x86/smbios: Untangle system and board tables
by Nico Huber (Code Review) 05 Nov '18

05 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29477 Change subject: x86/smbios: Untangle system and board tables ...................................................................... x86/smbios: Untangle system and board tables We were used to set the same values in the system and board tables. We'll keep the mainboard values as defaults for the system tables, so nothing changes unless somebody overrides the system table hooks. Change-Id: I3c9c95a1307529c3137647a161a698a4c3daa0ae Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M Documentation/Intel/Board/Galileo_checklist.html M src/arch/x86/smbios.c M src/drivers/i2c/at24rf08c/lenovo_serials.c M src/include/smbios.h M src/mainboard/emulation/qemu-i440fx/fw_cfg.c M src/mainboard/google/fizz/mainboard.c M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/octopus/mainboard.c M src/mainboard/google/poppy/variants/nami/mainboard.c M src/mainboard/google/poppy/variants/nautilus/mainboard.c M src/mainboard/google/poppy/variants/rammus/mainboard.c M src/mainboard/google/reef/mainboard.c M src/mainboard/pcengines/apu1/mainboard.c M src/mainboard/pcengines/apu2/mainboard.c M src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat M src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat 16 files changed, 56 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/29477/1 diff --git a/Documentation/Intel/Board/Galileo_checklist.html b/Documentation/Intel/Board/Galileo_checklist.html index 3fc04b1..7b06f54 100644 --- a/Documentation/Intel/Board/Galileo_checklist.html +++ b/Documentation/Intel/Board/Galileo_checklist.html @@ -134,7 +134,7 @@ <tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_manufacturer</td></tr> <tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_product_name</td></tr> <tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_serial_number</td></tr> -<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_set_uuid</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_system_set_uuid</td></tr> <tr bgcolor=#c0ffc0><td>Required</td><td>smbios_mainboard_version</td></tr> <tr bgcolor=#ffffc0><td>Optional</td><td>smm_disable_busmaster</td></tr> <tr bgcolor=#ffffc0><td>Optional</td><td>soc_after_silicon_init</td></tr> diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index c0545ce..29d1342 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -397,8 +397,6 @@ return len; } -#if !IS_ENABLED(CONFIG_SMBIOS_PROVIDED_BY_MOBO) - const char *__weak smbios_mainboard_serial_number(void) { return CONFIG_MAINBOARD_SERIAL_NUMBER; @@ -419,12 +417,6 @@ return CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME; } -void __weak smbios_mainboard_set_uuid(u8 *uuid) -{ - /* leave all zero */ -} -#endif - const char *__weak smbios_mainboard_asset_tag(void) { return ""; @@ -445,18 +437,36 @@ return SMBIOS_BOARD_TYPE_UNKNOWN; } -const char *__weak smbios_mainboard_sku(void) +const char *__weak smbios_system_serial_number(void) +{ + return smbios_mainboard_serial_number(); +} + +const char *__weak smbios_system_version(void) +{ + return smbios_mainboard_version(); +} + +const char *__weak smbios_system_manufacturer(void) +{ + return smbios_mainboard_manufacturer(); +} + +const char *__weak smbios_system_product_name(void) +{ + return smbios_mainboard_product_name(); +} + +void __weak smbios_system_set_uuid(u8 *uuid) +{ + /* leave all zero */ +} + +const char *__weak smbios_system_sku(void) { return ""; } -#ifdef CONFIG_MAINBOARD_FAMILY -const char *smbios_mainboard_family(void) -{ - return CONFIG_MAINBOARD_FAMILY; -} -#endif /* CONFIG_MAINBOARD_FAMILY */ - static int smbios_write_type1(unsigned long *current, int handle) { struct smbios_type1 *t = (struct smbios_type1 *)*current; @@ -467,17 +477,17 @@ t->handle = handle; t->length = len - 2; t->manufacturer = smbios_add_string(t->eos, - smbios_mainboard_manufacturer()); + smbios_system_manufacturer()); t->product_name = smbios_add_string(t->eos, - smbios_mainboard_product_name()); + smbios_system_product_name()); t->serial_number = smbios_add_string(t->eos, - smbios_mainboard_serial_number()); - t->sku = smbios_add_string(t->eos, smbios_mainboard_sku()); - t->version = smbios_add_string(t->eos, smbios_mainboard_version()); + smbios_system_serial_number()); + t->sku = smbios_add_string(t->eos, smbios_system_sku()); + t->version = smbios_add_string(t->eos, smbios_system_version()); #ifdef CONFIG_MAINBOARD_FAMILY - t->family = smbios_add_string(t->eos, smbios_mainboard_family()); + t->family = smbios_add_string(t->eos, CONFIG_MAINBOARD_FAMILY); #endif - smbios_mainboard_set_uuid(t->uuid); + smbios_system_set_uuid(t->uuid); len = t->length + smbios_string_table_len(t->eos); *current += len; return len; @@ -521,7 +531,7 @@ t->handle = handle; t->length = len - 2; t->manufacturer = smbios_add_string(t->eos, - smbios_mainboard_manufacturer()); + smbios_system_manufacturer()); t->bootup_state = SMBIOS_STATE_SAFE; t->power_supply_state = SMBIOS_STATE_SAFE; t->thermal_state = SMBIOS_STATE_SAFE; diff --git a/src/drivers/i2c/at24rf08c/lenovo_serials.c b/src/drivers/i2c/at24rf08c/lenovo_serials.c index 0209bb2..c609a7e 100644 --- a/src/drivers/i2c/at24rf08c/lenovo_serials.c +++ b/src/drivers/i2c/at24rf08c/lenovo_serials.c @@ -116,7 +116,7 @@ return lenovo_mainboard_partnumber(); } -void smbios_mainboard_set_uuid(u8 *uuid) +void smbios_system_set_uuid(u8 *uuid) { static char result[16]; unsigned i; diff --git a/src/include/smbios.h b/src/include/smbios.h index 574b924..d19c176 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -35,22 +35,23 @@ const char *name, u8 instance, u16 segment, u8 bus, u8 device, u8 function); +const char *smbios_system_manufacturer(void); +const char *smbios_system_product_name(void); +const char *smbios_system_serial_number(void); +const char *smbios_system_version(void); +void smbios_system_set_uuid(u8 *uuid); +const char *smbios_system_sku(void); + const char *smbios_mainboard_manufacturer(void); const char *smbios_mainboard_product_name(void); - const char *smbios_mainboard_serial_number(void); const char *smbios_mainboard_version(void); -void smbios_mainboard_set_uuid(u8 *uuid); + const char *smbios_mainboard_bios_version(void); const char *smbios_mainboard_asset_tag(void); u8 smbios_mainboard_feature_flags(void); const char *smbios_mainboard_location_in_chassis(void); - -const char *smbios_mainboard_sku(void); u8 smbios_mainboard_enclosure_type(void); -#ifdef CONFIG_MAINBOARD_FAMILY -const char *smbios_mainboard_family(void); -#endif #define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) #define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c index f6a3de7..f009dfa 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg.c +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg.c @@ -475,7 +475,7 @@ return type1_serial_number ?: CONFIG_MAINBOARD_SERIAL_NUMBER; } -void smbios_mainboard_set_uuid(u8 *uuid) +void smbios_system_set_uuid(u8 *uuid) { fw_cfg_smbios_init(); memcpy(uuid, type1_uuid, 16); diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index 5670936..54fd7df 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -177,7 +177,7 @@ return oem_id; } -const char *smbios_mainboard_sku(void) +const char *smbios_system_sku(void) { static char sku_str[5]; /* sku{0..7} */ diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index ebdcc93..d8e0984 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -220,7 +220,7 @@ } #endif -const char *smbios_mainboard_sku(void) +const char *smbios_system_sku(void) { static char sku_str[7]; /* sku{0..255} */ diff --git a/src/mainboard/google/octopus/mainboard.c b/src/mainboard/google/octopus/mainboard.c index fceb95d..a472a2d 100644 --- a/src/mainboard/google/octopus/mainboard.c +++ b/src/mainboard/google/octopus/mainboard.c @@ -131,7 +131,7 @@ return sku_id; } -const char *smbios_mainboard_sku(void) +const char *smbios_system_sku(void) { static char sku_str[7]; /* sku{0..255} */ uint32_t sku_id = get_board_sku(); diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index ba994c2..6807175 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -102,7 +102,7 @@ return sku_id; } -const char *smbios_mainboard_sku(void) +const char *smbios_system_sku(void) { static char sku_str[14]; /* sku{0..4294967295} */ diff --git a/src/mainboard/google/poppy/variants/nautilus/mainboard.c b/src/mainboard/google/poppy/variants/nautilus/mainboard.c index bacf1a4..8dd4eea 100644 --- a/src/mainboard/google/poppy/variants/nautilus/mainboard.c +++ b/src/mainboard/google/poppy/variants/nautilus/mainboard.c @@ -26,7 +26,7 @@ #define B_PCH_OC_WDT_CTL_EN BIT14 #define B_PCH_OC_WDT_CTL_UNXP_RESET_STS BIT22 -const char *smbios_mainboard_sku(void) +const char *smbios_system_sku(void) { static char sku_str[5]; /* sku{0-1} */ diff --git a/src/mainboard/google/poppy/variants/rammus/mainboard.c b/src/mainboard/google/poppy/variants/rammus/mainboard.c index a3474d4..5c5b258 100644 --- a/src/mainboard/google/poppy/variants/rammus/mainboard.c +++ b/src/mainboard/google/poppy/variants/rammus/mainboard.c @@ -34,7 +34,7 @@ return sku_id; } -const char *smbios_mainboard_sku(void) +const char *smbios_system_sku(void) { static char sku_str[14]; /* sku{0..4294967295} */ diff --git a/src/mainboard/google/reef/mainboard.c b/src/mainboard/google/reef/mainboard.c index 05af84a..20b6a26 100644 --- a/src/mainboard/google/reef/mainboard.c +++ b/src/mainboard/google/reef/mainboard.c @@ -88,7 +88,7 @@ { } -const char *smbios_mainboard_sku(void) +const char *smbios_system_sku(void) { static char sku_str[7]; /* sku{0..255} */ diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 1105d5f..084a186 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -263,7 +263,7 @@ /* * We will stuff the memory size into the smbios sku location. */ -const char *smbios_mainboard_sku(void) +const char *smbios_system_sku(void) { static char sku[5]; if (sku[0] != 0) diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 99ddf80..7f05a0d 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -222,7 +222,7 @@ /* * We will stuff the memory size into the smbios sku location. */ -const char *smbios_mainboard_sku(void) +const char *smbios_system_sku(void) { static char sku[5]; if (sku[0] != 0) diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat index 64f8584..7ef036f 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat @@ -32,7 +32,7 @@ smbios_mainboard_manufacturer smbios_mainboard_product_name smbios_mainboard_serial_number -smbios_mainboard_set_uuid +smbios_system_set_uuid smbios_mainboard_version smm_disable_busmaster soc_after_silicon_init diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat index 6608583..1ad7bd8 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat @@ -29,7 +29,7 @@ smbios_mainboard_manufacturer smbios_mainboard_product_name smbios_mainboard_serial_number -smbios_mainboard_set_uuid +smbios_system_set_uuid smbios_mainboard_version smm_disable_busmaster soc_after_silicon_init -- To view, visit https://review.coreboot.org/29477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3c9c95a1307529c3137647a161a698a4c3daa0ae Gerrit-Change-Number: 29477 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

1 0

Change in coreboot[master]: device/i2c_bus: Add i2c_dev_readb_at_word()
by Nico Huber (Code Review) 05 Nov '18

05 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29478 Change subject: device/i2c_bus: Add i2c_dev_readb_at_word() ...................................................................... device/i2c_bus: Add i2c_dev_readb_at_word() Does the same as i2c_dev_readb_at() but sends a 2-byte offset to the I2C chip (for larger EEPROM parts). Change-Id: I7516f3e5d9aca362c2b340aa5627d91510c09412 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/device/i2c_bus.c M src/include/device/i2c_bus.h 2 files changed, 47 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/29478/1 diff --git a/src/device/i2c_bus.c b/src/device/i2c_bus.c index 30bb80c..8d8e61a 100644 --- a/src/device/i2c_bus.c +++ b/src/device/i2c_bus.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <device/smbus.h> #include <device/i2c_bus.h> +#include <commonlib/endian.h> struct bus *i2c_link(struct device *const dev) { @@ -159,3 +160,40 @@ return -1; } } + +int i2c_dev_readb_at_word(struct device *const dev, + uint8_t *const buf, const size_t len, uint16_t off) +{ + struct device *const busdev = i2c_busdev(dev); + if (!busdev) + return -1; + + if (busdev->ops->ops_i2c_bus) { + const struct i2c_msg msg[] = { + { + .flags = 0, + .slave = dev->path.i2c.device, + .buf = (uint8_t *)&off, + .len = sizeof(off), + }, + { + .flags = I2C_M_RD, + .slave = dev->path.i2c.device, + .buf = buf, + .len = len, + }, + }; + + write_be16(&off, off); + const int ret = busdev->ops->ops_i2c_bus-> + transfer(busdev, msg, ARRAY_SIZE(msg)); + if (ret) + return ret; + else + return len; + } else { + printk(BIOS_ERR, "%s Missing ops_i2c_bus->transfer", + dev_path(busdev)); + return -1; + } +} diff --git a/src/include/device/i2c_bus.h b/src/include/device/i2c_bus.h index 6aa4f9b..27e261f 100644 --- a/src/include/device/i2c_bus.h +++ b/src/include/device/i2c_bus.h @@ -89,4 +89,13 @@ */ int i2c_dev_writeb_at(struct device *, uint8_t off, uint8_t val); +/* + * Sends the 2-byte register offset `off` and reads `len` bytes into `buf`. + * + * Returns the number of bytes read on success, negative `enum cb_err` + * value on error. + */ +int i2c_dev_readb_at_word(struct device *, + uint8_t *buf, size_t len, uint16_t off); + #endif /* _DEVICE_I2C_BUS_H_ */ -- To view, visit https://review.coreboot.org/29478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7516f3e5d9aca362c2b340aa5627d91510c09412 Gerrit-Change-Number: 29478 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2018