coreboot-gerrit November 2018

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Change in coreboot[master]: ec/kontron: Add support for Kontron kempld
by Nico Huber (Code Review) 05 Nov '18

05 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29476 Change subject: ec/kontron: Add support for Kontron kempld ...................................................................... ec/kontron: Add support for Kontron kempld A programmable logic device used by Kontron as EC on their COM express modules. The name `kempld` is taken from Linux kernel sources, as is the I2C driver. The meaning of the acronym is unclear, probably: Kontron Embedded Module PLD. Change-Id: If9a0826c4a8f5c8cd573610c2d10561334258b36 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- A src/ec/kontron/kempld/Kconfig A src/ec/kontron/kempld/Makefile.inc A src/ec/kontron/kempld/chip.h A src/ec/kontron/kempld/early_kempld.c A src/ec/kontron/kempld/kempld.c A src/ec/kontron/kempld/kempld.h A src/ec/kontron/kempld/kempld_i2c.c A src/ec/kontron/kempld/kempld_internal.h 8 files changed, 605 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/29476/1 diff --git a/src/ec/kontron/kempld/Kconfig b/src/ec/kontron/kempld/Kconfig new file mode 100644 index 0000000..647bd12 --- /dev/null +++ b/src/ec/kontron/kempld/Kconfig @@ -0,0 +1,5 @@ +config EC_KONTRON_KEMPLD + bool + help + Driver for Kontron's express module programmable logic device used + on their COMexpress modules. diff --git a/src/ec/kontron/kempld/Makefile.inc b/src/ec/kontron/kempld/Makefile.inc new file mode 100644 index 0000000..0d59886 --- /dev/null +++ b/src/ec/kontron/kempld/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-$(CONFIG_EC_KONTRON_KEMPLD) += early_kempld.c +ramstage-$(CONFIG_EC_KONTRON_KEMPLD) += early_kempld.c +ramstage-$(CONFIG_EC_KONTRON_KEMPLD) += kempld.c +ramstage-$(CONFIG_EC_KONTRON_KEMPLD) += kempld_i2c.c diff --git a/src/ec/kontron/kempld/chip.h b/src/ec/kontron/kempld/chip.h new file mode 100644 index 0000000..7f06937 --- /dev/null +++ b/src/ec/kontron/kempld/chip.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef EC_KONTRON_KEMPLD_CHIP_H +#define EC_KONTRON_KEMPLD_CHIP_H + +#define KEMPLD_NUM_UARTS 2 + +enum kempld_uart_io { + KEMPLD_UART_3F8 = 0, + KEMPLD_UART_2F8 = 1, + KEMPLD_UART_3E8 = 2, + KEMPLD_UART_2E8 = 3, +}; + +struct kempld_uart { + enum kempld_uart_io io; + unsigned int irq; +}; + +struct ec_kontron_kempld_config { + struct kempld_uart uart[KEMPLD_NUM_UARTS]; +}; + +#endif /* EC_KONTRON_KEMPLD_CHIP_H */ diff --git a/src/ec/kontron/kempld/early_kempld.c b/src/ec/kontron/kempld/early_kempld.c new file mode 100644 index 0000000..773b8b6 --- /dev/null +++ b/src/ec/kontron/kempld/early_kempld.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/io.h> +#include <delay.h> + +#include "chip.h" +#include "kempld.h" +#include "kempld_internal.h" + +void kempld_write8(const uint8_t addr, const uint8_t data) +{ + outb(addr, KEMPLD_IDX); + outb(data, KEMPLD_DAT); +} + +uint8_t kempld_read8(const uint8_t addr) +{ + outb(addr, KEMPLD_IDX); + return inb(KEMPLD_DAT); +} + +int kempld_get_mutex(int timeout_ms) +{ + while (inb(KEMPLD_IDX) & KEMPLD_MUTEX_KEY && timeout_ms--) + mdelay(1); + return timeout_ms; +} + +void kempld_release_mutex(void) +{ + outb(KEMPLD_MUTEX_KEY, KEMPLD_IDX); +} + +void kempld_enable_uart_for_console(void) +{ + if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + return; + + if (kempld_get_mutex(100) < 0) + return; + + switch (CONFIG_UART_FOR_CONSOLE) { + case 0: + kempld_write8(KEMPLD_UART_0, + KEMPLD_UART_ENABLE | + KEMPLD_UART_3F8 << KEMPLD_UART_IO_SHIFT); + break; + case 1: + kempld_write8(KEMPLD_UART_1, + KEMPLD_UART_ENABLE | + KEMPLD_UART_2F8 << KEMPLD_UART_IO_SHIFT); + break; + default: + break; + } + + kempld_release_mutex(); +} diff --git a/src/ec/kontron/kempld/kempld.c b/src/ec/kontron/kempld/kempld.c new file mode 100644 index 0000000..19c1880 --- /dev/null +++ b/src/ec/kontron/kempld/kempld.c @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> + +#include "chip.h" +#include "kempld.h" +#include "kempld_internal.h" + +static void kempld_uart_read_resources(struct device *dev) +{ + static const unsigned int io_addr[] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; + + const struct ec_kontron_kempld_config *const config = dev->chip_info; + + struct resource *const res_io = new_resource(dev, 0); + struct resource *const res_irq = new_resource(dev, 1); + const unsigned int uart = dev->path.generic.subid; + if (!config || !res_io || !res_irq || uart >= KEMPLD_NUM_UARTS) + return; + + const enum kempld_uart_io io = config->uart[uart].io; + if (io >= ARRAY_SIZE(io_addr)) { + printk(BIOS_ERR, "KEMPLD: Bad io value '%d' for UART#%u\n.", + io, uart); + dev->enabled = false; + return; + } + + const int irq = config->uart[uart].irq; + if (irq >= 16) { + printk(BIOS_ERR, "KEMPLD: Bad irq value '%d' for UART#%u\n.", + irq, uart); + dev->enabled = false; + return; + } + + res_io->base = io_addr[io]; + res_io->size = 8; + res_io->flags = IORESOURCE_IO | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + res_irq->base = irq; + res_irq->size = 1; + res_irq->flags = IORESOURCE_IO | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + if (kempld_get_mutex(100) < 0) + return; + + const uint8_t reg = uart ? KEMPLD_UART_1 : KEMPLD_UART_0; + const uint8_t val = kempld_read8(reg); + kempld_write8(reg, (val & ~(KEMPLD_UART_IO_MASK | KEMPLD_UART_IRQ_MASK)) + | io << KEMPLD_UART_IO_SHIFT + | irq << KEMPLD_UART_IRQ_SHIFT); + + kempld_release_mutex(); +} + +static void kempld_uart_enable_resources(struct device *dev) +{ + if (kempld_get_mutex(100) < 0) + return; + + const unsigned int uart = dev->path.generic.subid; + const uint8_t reg = uart ? KEMPLD_UART_1 : KEMPLD_UART_0; + kempld_write8(reg, kempld_read8(reg) | KEMPLD_UART_ENABLE); + + kempld_release_mutex(); +} + +static struct device_operations kempld_uart_ops = { + .read_resources = kempld_uart_read_resources, + .enable_resources = kempld_uart_enable_resources, +}; + +static void kempld_enable_dev(struct device *const dev) +{ + if (dev->path.type == DEVICE_PATH_GENERIC) { + switch (dev->path.generic.id) { + case 0: + if (dev->path.generic.subid < KEMPLD_NUM_UARTS) { + dev->ops = &kempld_uart_ops; + break; + } + case 1: + if (dev->path.generic.subid == 0) { + kempld_i2c_device_init(dev); + break; + } + default: + printk(BIOS_WARNING, + "KEMPLD: Spurious device %s.\n", + dev_path(dev)); + break; + } + } +} + +struct chip_operations ec_kontron_kempld_ops = { + CHIP_NAME("Kontron KEMPLD") + .enable_dev = kempld_enable_dev, +}; diff --git a/src/ec/kontron/kempld/kempld.h b/src/ec/kontron/kempld/kempld.h new file mode 100644 index 0000000..fe5f54f --- /dev/null +++ b/src/ec/kontron/kempld/kempld.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef EC_KONTRON_KEMPLD_H +#define EC_KONTRON_KEMPLD_H + +#include <stdint.h> + +void kempld_write8(uint8_t addr, uint8_t data); +uint8_t kempld_read8(uint8_t addr); + +int kempld_get_mutex(int timeout_ms); +void kempld_release_mutex(void); + +void kempld_enable_uart_for_console(void); + +#endif /* EC_KONTRON_KEMPLD_H */ diff --git a/src/ec/kontron/kempld/kempld_i2c.c b/src/ec/kontron/kempld/kempld_i2c.c new file mode 100644 index 0000000..fdc0b50 --- /dev/null +++ b/src/ec/kontron/kempld/kempld_i2c.c @@ -0,0 +1,296 @@ +/* + * I2C bus driver for Kontron COM modules + * + * Copyright (C) 2017 secunet Security Networks AG + * + * Based on the similar driver in Linux: + * + * Copyright (c) 2010-2013 Kontron Europe GmbH + * Author: Michael Brunner <michael.brunner(a)kontron.com> + * + * The driver is based on the i2c-ocores driver by Peter Korsgaard. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <console/console.h> +#include <device/device.h> +#include <device/i2c_bus.h> +#include <timer.h> +#include <delay.h> + +#include "kempld.h" +#include "kempld_internal.h" + +#define KEMPLD_I2C_PRELOW 0x0b +#define KEMPLD_I2C_PREHIGH 0x0c +#define KEMPLD_I2C_DATA 0x0e + +#define KEMPLD_I2C_CTRL 0x0d +#define I2C_CTRL_IEN 0x40 +#define I2C_CTRL_EN 0x80 + +#define KEMPLD_I2C_STAT 0x0f +#define I2C_STAT_IF 0x01 +#define I2C_STAT_TIP 0x02 +#define I2C_STAT_ARBLOST 0x20 +#define I2C_STAT_BUSY 0x40 +#define I2C_STAT_NACK 0x80 + +#define KEMPLD_I2C_CMD 0x0f +#define I2C_CMD_START 0x91 +#define I2C_CMD_STOP 0x41 +#define I2C_CMD_READ 0x21 +#define I2C_CMD_WRITE 0x11 +#define I2C_CMD_READ_ACK 0x21 +#define I2C_CMD_READ_NACK 0x29 +#define I2C_CMD_IACK 0x01 + +#define KEMPLD_I2C_FREQ_MAX 2700 /* 2.7 mHz */ +#define KEMPLD_I2C_FREQ_STD 100 /* 100 kHz */ + +#define EIO 5 +#define ENXIO 6 +#define EAGAIN 11 +#define EBUSY 16 +#define ETIMEDOUT 110 + +enum kempld_i2c_state { + STATE_DONE = 0, + STATE_INIT, + STATE_ADDR, + STATE_ADDR10, + STATE_START, + STATE_WRITE, + STATE_READ, + STATE_ERROR, +}; + +struct kempld_i2c_data { + const struct i2c_msg *msg; + size_t pos; + size_t nmsgs; + enum kempld_i2c_state state; +}; + +/* + * kempld_get_mutex must be called prior to calling this function. + */ +static int kempld_i2c_process(struct kempld_i2c_data *const i2c) +{ + u8 stat = kempld_read8(KEMPLD_I2C_STAT); + const struct i2c_msg *msg = i2c->msg; + u8 addr; + + /* Ready? */ + if (stat & I2C_STAT_TIP) + return -EBUSY; + + if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) { + /* Stop has been sent */ + kempld_write8(KEMPLD_I2C_CMD, I2C_CMD_IACK); + if (i2c->state == STATE_ERROR) + return -EIO; + return 0; + } + + /* Error? */ + if (stat & I2C_STAT_ARBLOST) { + i2c->state = STATE_ERROR; + kempld_write8(KEMPLD_I2C_CMD, I2C_CMD_STOP); + return -EAGAIN; + } + + if (i2c->state == STATE_INIT) { + if (stat & I2C_STAT_BUSY) + return -EBUSY; + + i2c->state = STATE_ADDR; + } + + if (i2c->state == STATE_ADDR) { + /* 10 bit address? */ + if (i2c->msg->flags & I2C_M_TEN) { + addr = 0xf0 | ((i2c->msg->slave >> 7) & 0x6); + i2c->state = STATE_ADDR10; + } else { + addr = (i2c->msg->slave << 1); + i2c->state = STATE_START; + } + + /* Set read bit if necessary */ + addr |= (i2c->msg->flags & I2C_M_RD) ? 1 : 0; + + kempld_write8(KEMPLD_I2C_DATA, addr); + kempld_write8(KEMPLD_I2C_CMD, I2C_CMD_START); + + return 0; + } + + /* Second part of 10 bit addressing */ + if (i2c->state == STATE_ADDR10) { + kempld_write8(KEMPLD_I2C_DATA, i2c->msg->slave & 0xff); + kempld_write8(KEMPLD_I2C_CMD, I2C_CMD_WRITE); + + i2c->state = STATE_START; + return 0; + } + + if (i2c->state == STATE_START || i2c->state == STATE_WRITE) { + i2c->state = (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE; + + if (stat & I2C_STAT_NACK) { + i2c->state = STATE_ERROR; + kempld_write8(KEMPLD_I2C_CMD, I2C_CMD_STOP); + return -ENXIO; + } + } else { + msg->buf[i2c->pos++] = kempld_read8(KEMPLD_I2C_DATA); + } + + if (i2c->pos >= msg->len) { + i2c->nmsgs--; + i2c->msg++; + i2c->pos = 0; + msg = i2c->msg; + + if (i2c->nmsgs) { + if (!(msg->flags & I2C_M_NOSTART)) { + i2c->state = STATE_ADDR; + return 0; + } else { + i2c->state = (msg->flags & I2C_M_RD) + ? STATE_READ : STATE_WRITE; + } + } else { + i2c->state = STATE_DONE; + kempld_write8(KEMPLD_I2C_CMD, I2C_CMD_STOP); + return 0; + } + } + + if (i2c->state == STATE_READ) { + kempld_write8(KEMPLD_I2C_CMD, i2c->pos == (msg->len - 1) ? + I2C_CMD_READ_NACK : I2C_CMD_READ_ACK); + } else { + kempld_write8(KEMPLD_I2C_DATA, msg->buf[i2c->pos++]); + kempld_write8(KEMPLD_I2C_CMD, I2C_CMD_WRITE); + } + + return 0; +} + +static int kempld_i2c_xfer(struct device *const dev, + const struct i2c_msg *const msgs, + const size_t num) +{ + struct kempld_i2c_data i2c; + struct stopwatch sw; + int ret; + + if (kempld_get_mutex(100) < 0) + return -ENXIO; + + i2c.msg = msgs; + i2c.pos = 0; + i2c.nmsgs = num; + i2c.state = STATE_INIT; + + /* Handle the transfer */ + stopwatch_init_msecs_expire(&sw, 1000); + while (!stopwatch_expired(&sw)) { + ret = kempld_i2c_process(&i2c); + + if (i2c.state == STATE_DONE || i2c.state == STATE_ERROR) { + if (i2c.state == STATE_DONE) { + printk(BIOS_SPEW, "kempld_i2c: Processed %zu segments.\n", num); + ret = 0; + } else { + printk(BIOS_INFO, "kempld_i2c: Transfer failed.\n"); + } + goto _release; + } + + if (ret == 0) + stopwatch_init_msecs_expire(&sw, 1000); + + udelay(10); + } + + i2c.state = STATE_ERROR; + ret = -ETIMEDOUT; + printk(BIOS_INFO, "kempld_i2c: Transfer failed.\n"); + +_release: + kempld_release_mutex(); + return ret; +} + +static const struct i2c_bus_operations kempld_i2c_bus_ops = { + .transfer = kempld_i2c_xfer, +}; + +static struct device_operations kempld_i2c_dev_ops = { + .scan_bus = &scan_smbus, + .ops_i2c_bus = &kempld_i2c_bus_ops, +}; + +void kempld_i2c_device_init(struct device *const dev) +{ + u16 prescale_corr; + long prescale; + u8 ctrl; + u8 stat; + u8 cfg; + + if (kempld_get_mutex(100) < 0) + return; + + /* Make sure the device is disabled */ + ctrl = kempld_read8(KEMPLD_I2C_CTRL); + ctrl &= ~(I2C_CTRL_EN | I2C_CTRL_IEN); + kempld_write8(KEMPLD_I2C_CTRL, ctrl); + + const u8 spec_major = KEMPLD_SPEC_GET_MAJOR(kempld_read8(KEMPLD_SPEC)); + if (spec_major == 1) + prescale = KEMPLD_CLK / (KEMPLD_I2C_FREQ_STD * 5) - 1000; + else + prescale = KEMPLD_CLK / (KEMPLD_I2C_FREQ_STD * 4) - 3000; + + if (prescale < 0) + prescale = 0; + + /* Round to the best matching value */ + prescale_corr = prescale / 1000; + if (prescale % 1000 >= 500) + prescale_corr++; + + kempld_write8(KEMPLD_I2C_PRELOW, prescale_corr & 0xff); + kempld_write8(KEMPLD_I2C_PREHIGH, prescale_corr >> 8); + + /* Disable I2C bus output on GPIO pins */ + cfg = kempld_read8(KEMPLD_CFG); + cfg &= ~KEMPLD_CFG_GPIO_I2C_MUX; + kempld_write8(KEMPLD_CFG, cfg); + + /* Enable the device */ + kempld_write8(KEMPLD_I2C_CMD, I2C_CMD_IACK); + ctrl |= I2C_CTRL_EN; + kempld_write8(KEMPLD_I2C_CTRL, ctrl); + + stat = kempld_read8(KEMPLD_I2C_STAT); + if (stat & I2C_STAT_BUSY) + kempld_write8(KEMPLD_I2C_CMD, I2C_CMD_STOP); + + dev->ops = &kempld_i2c_dev_ops; + + kempld_release_mutex(); +} diff --git a/src/ec/kontron/kempld/kempld_internal.h b/src/ec/kontron/kempld/kempld_internal.h new file mode 100644 index 0000000..93351ce --- /dev/null +++ b/src/ec/kontron/kempld/kempld_internal.h @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef EC_KONTRON_KEMPLD_INTERNAL_H +#define EC_KONTRON_KEMPLD_INTERNAL_H + +#include <device/device.h> + +/* i/o ports */ +#define KEMPLD_IDX 0xa80 +#define KEMPLD_MUTEX_KEY 0x80 +#define KEMPLD_DAT 0xa81 + +/* indexed registers */ +#define KEMPLD_SPEC 0x06 +#define KEMPLD_SPEC_GET_MINOR(x) (x & 0x0f) +#define KEMPLD_SPEC_GET_MAJOR(x) (x >> 4 & 0x0f) + +#define KEMPLD_CFG 0x37 +#define KEMPLD_CFG_GPIO_I2C_MUX (1 << 0) + +#define KEMPLD_UART_0 0x30 +#define KEMPLD_UART_1 0x31 +#define KEMPLD_UART_IRQ_SHIFT 0 +#define KEMPLD_UART_IRQ_MASK (0xf << KEMPLD_UART_IRQ_SHIFT) +#define KEMPLD_UART_IO_SHIFT 4 +#define KEMPLD_UART_IO_MASK (0x3 << KEMPLD_UART_IO_SHIFT) +#define KEMPLD_UART_ENABLE 0x80 + +#define KEMPLD_CLK 33333333 /* 33MHz */ + +void kempld_i2c_device_init(struct device *const dev); + +#endif /* EC_KONTRON_KEMPLD_INTERNAL_H */ -- To view, visit https://review.coreboot.org/29476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If9a0826c4a8f5c8cd573610c2d10561334258b36 Gerrit-Change-Number: 29476 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: drivers/i2c/nct7802y: Add new hardware-monitoring IC
by Nico Huber (Code Review) 05 Nov '18

05 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29475 Change subject: drivers/i2c/nct7802y: Add new hardware-monitoring IC ...................................................................... drivers/i2c/nct7802y: Add new hardware-monitoring IC Just another hardware-monitoring chip. Only limited fan control and PECI configuration is implemented. Change-Id: I35ea79e12941804e398c6304a08170a776f4ca76 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- A src/drivers/i2c/nct7802y/Kconfig A src/drivers/i2c/nct7802y/Makefile.inc A src/drivers/i2c/nct7802y/chip.h A src/drivers/i2c/nct7802y/nct7802y.c A src/drivers/i2c/nct7802y/nct7802y.h A src/drivers/i2c/nct7802y/nct7802y_fan.c A src/drivers/i2c/nct7802y/nct7802y_peci.c 7 files changed, 445 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/29475/1 diff --git a/src/drivers/i2c/nct7802y/Kconfig b/src/drivers/i2c/nct7802y/Kconfig new file mode 100644 index 0000000..a51f384 --- /dev/null +++ b/src/drivers/i2c/nct7802y/Kconfig @@ -0,0 +1,4 @@ +config DRIVERS_I2C_NCT7802Y + bool + help + The NCT7802Y by Nuvoton is a Hardware Monitoring IC. diff --git a/src/drivers/i2c/nct7802y/Makefile.inc b/src/drivers/i2c/nct7802y/Makefile.inc new file mode 100644 index 0000000..9544de0 --- /dev/null +++ b/src/drivers/i2c/nct7802y/Makefile.inc @@ -0,0 +1,3 @@ +ramstage-$(CONFIG_DRIVERS_I2C_NCT7802Y) += nct7802y.c +ramstage-$(CONFIG_DRIVERS_I2C_NCT7802Y) += nct7802y_fan.c +ramstage-$(CONFIG_DRIVERS_I2C_NCT7802Y) += nct7802y_peci.c diff --git a/src/drivers/i2c/nct7802y/chip.h b/src/drivers/i2c/nct7802y/chip.h new file mode 100644 index 0000000..11db12b --- /dev/null +++ b/src/drivers/i2c/nct7802y/chip.h @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DRIVERS_I2C_NCT7802Y_CHIP_H +#define DRIVERS_I2C_NCT7802Y_CHIP_H + +#include <stdint.h> + +#define NCT7802Y_PECI_CNT 2 +#define NCT7802Y_FAN_CNT 3 + +enum nct7802y_peci_mode { + PECI_DISABLED = 0, + PECI_DOMAIN_0, + PECI_DOMAIN_1, + PECI_HIGHEST, +}; + +struct nct7802y_peci_config { + enum nct7802y_peci_mode mode; + u8 base_temp; +}; + +enum nct7802y_fan_mode { + FAN_IGNORE = 0, + FAN_MANUAL, + FAN_SMART, +}; + +enum nct7802y_fan_smartmode { + SMART_FAN_DUTY = 0, /* Target values given in duty cycle %. */ + SMART_FAN_RPM, /* Target valuse given in RPM. */ +}; + +enum nct7802y_fan_speed { + FAN_SPEED_NORMAL = 0, /* RPM values <= 12,750. */ + FAN_SPPED_HIGHSPEED, /* RPM values <= 25,500. */ +}; + +enum nct7802y_fan_pecierror { + PECI_ERROR_KEEP = 0, /* Keep current value. */ + PECI_ERROR_VALUE, /* Use `pecierror_minduty`. */ + PECI_ERROR_FULLSPEED, /* Run PWM at 100% duty cycle. */ +}; + +enum nct7802y_temp_source { + TEMP_SOURCE_REMOTE_1 = 0, + TEMP_SOURCE_REMOTE_2, + TEMP_SOURCE_REMOTE_3, + TEMP_SOURCE_LOCAL, + TEMP_SOURCE_PECI_0, + TEMP_SOURCE_PECI_1, + TEMP_SOURCE_PROGRAMMABLE_0, + TEMP_SOURCE_PROGRAMMABLE_1, +}; + +struct nct7802y_fan_smartconfig { + enum nct7802y_fan_smartmode mode; + enum nct7802y_fan_speed speed; + enum nct7802y_temp_source tempsrc; + struct { + u8 temp; + u16 target; + } table[4]; + u8 critical_temp; +}; + +struct nct7802y_fan_config { + enum nct7802y_fan_mode mode; + union { + u8 duty_cycle; + struct nct7802y_fan_smartconfig smart; + }; +}; + +/* Implements only those parts currently used by coreboot mainboards. */ +struct drivers_i2c_nct7802y_config { + struct nct7802y_peci_config peci[NCT7802Y_PECI_CNT]; + struct nct7802y_fan_config fan[NCT7802Y_FAN_CNT]; + enum nct7802y_fan_pecierror on_pecierror; + u8 pecierror_minduty; +}; + +#endif /* DRIVERS_I2C_NCT7802Y_CHIP_H */ diff --git a/src/drivers/i2c/nct7802y/nct7802y.c b/src/drivers/i2c/nct7802y/nct7802y.c new file mode 100644 index 0000000..667697d --- /dev/null +++ b/src/drivers/i2c/nct7802y/nct7802y.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> + +#include "nct7802y.h" +#include "chip.h" + +static void nct7802y_init(struct device *const dev) +{ + nct7802y_init_peci(dev); + nct7802y_init_fan(dev); +} + +static struct device_operations nct7802y_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = nct7802y_init, +}; + +static void nct7802y_enable(struct device *const dev) +{ + dev->ops = &nct7802y_ops; +} + +struct chip_operations drivers_i2c_nct7802y_ops = { + CHIP_NAME("NCT7802Y") + .enable_dev = nct7802y_enable +}; diff --git a/src/drivers/i2c/nct7802y/nct7802y.h b/src/drivers/i2c/nct7802y/nct7802y.h new file mode 100644 index 0000000..999d275 --- /dev/null +++ b/src/drivers/i2c/nct7802y/nct7802y.h @@ -0,0 +1,104 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DRIVERS_I2C_NCT7802Y_H +#define DRIVERS_I2C_NCT7802Y_H + +#include <types.h> +#include <console/console.h> +#include <device/device.h> +#include <device/i2c_bus.h> + +#define BANK_SELECT 0x00 + +/* Bank 0 */ + +#define PECI_ENABLE 0x23 +#define PECI_ENABLE_AGENTx(x) (1 << (x)) + +#define FAN_ENABLE 0x24 +#define FANx_ENABLE(fan) (1 << (fan)) + +#define FAN_CTRL(fan) (0x60 + (fan)) + +#define CLOSE_LOOP_FAN_RPM_CTRL 0x63 +#define CLOSE_LOOP_FANx_EN(fan) (1 << ((fan) + 5)) +#define CLOSE_LOOP_FANx_HIGH_RPM(fan) (1 << ((fan) + 2)) +#define CLOSE_LOOP_FAN_PECI_ERR_MASK (3 << 0) +#define CLOSE_LOOP_FAN_PECI_ERR_CURR (0 << 0) +#define CLOSE_LOOP_FAN_PECI_ERR_VALUE (1 << 0) +#define CLOSE_LOOP_FAN_PECI_ERR_MAX (2 << 0) + +#define TEMP_SHIFT(temp) (((temp) % 2) * 4) +#define TEMP_TO_FAN_MAP(temp) (0x64 + (temp) / 2) +#define TEMPx_TO_FAN_MAP_MASK(temp) (7 << TEMP_SHIFT(temp)) +#define TEMPx_TO_FANy_MAP(temp, fan) (1 << (TEMP_SHIFT(temp) + (fan))) + +#define FAN_CTRL_TEMP_SRC(temp) (0x68 + (temp) / 2) +#define FAN_CTRL_TEMPx_SRC_MASK(temp) (7 << TEMP_SHIFT(temp)) +#define FAN_CTRL_TEMPx_SRCy(temp, src) ((src) << TEMP_SHIFT(temp)) + +#define FAN_DUTY_ON_PECI_ERROR 0x7a + +#define TABLEx_TEMP_POINTy(tab, pt) (0x80 + (0x10 * (tab)) + (pt)) +#define TABLEx_TARGET_POINTy(tab, pt) (0x85 + (0x10 * (tab)) + (pt)) + +/* Bank 1 */ + +#define PECI_CTRL_1 0x01 +#define PECI_CTRL_1_EN (1 << 7) +#define PECI_CTRL_1_MANUAL_EN (1 << 1) +#define PECI_CTRL_1_ROUTINE_EN (1 << 0) + +#define PECI_CTRL_3 0x03 +#define PECI_CTRL_3_EN_AGENTx(x) (1 << ((x) + 4)) +#define PECI_CTRL_3_HAS_DOM1_AGENTx(x) (1 << (x)) + +#define PECI_REPORT_TEMP_STYLE 0x04 +#define PECI_TEMP_STYLE_DOM0_AGENTx(x) (0 << ((x) + 1)) +#define PECI_TEMP_STYLE_DOM1_AGENTx(x) (1 << ((x) + 1)) +#define PECI_TEMP_STYLE_SINGLE (0 << 0) +#define PECI_TEMP_STYLE_HIGHEST (1 << 0) + +#define PECI_BASE_TEMP_AGENT(x) (0x09 + (x)) +#define PECI_BASE_TEMP_MAX (0x7f << 0) + +static inline int nct7802y_select_bank(struct device *const dev, const u8 bank) +{ + const int ret = i2c_dev_writeb_at(dev, BANK_SELECT, bank); + if (ret != CB_SUCCESS) + printk(BIOS_NOTICE, "nct7802y: Select bank failed: %d\n", ret); + return ret; +} + +static inline int nct7802y_write(struct device *const dev, + const u8 reg, const u8 value) +{ + return i2c_dev_writeb_at(dev, reg, value); +} + +static inline int nct7802y_update(struct device *const dev, const u8 reg, + const u8 unset_mask, const u8 set_mask) +{ + const int val = i2c_dev_readb_at(dev, reg); + if (val < 0) + return val; + return i2c_dev_writeb_at(dev, reg, (val & ~unset_mask) | set_mask); +} + +void nct7802y_init_fan(struct device *dev); +void nct7802y_init_peci(struct device *dev); + +#endif /* DRIVERS_I2C_NCT7802Y_H */ diff --git a/src/drivers/i2c/nct7802y/nct7802y_fan.c b/src/drivers/i2c/nct7802y/nct7802y_fan.c new file mode 100644 index 0000000..4cf7534 --- /dev/null +++ b/src/drivers/i2c/nct7802y/nct7802y_fan.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <device/device.h> + +#include "nct7802y.h" +#include "chip.h" + +static void init_fan(struct device *const dev, + const struct nct7802y_fan_config *const config, + const unsigned int fan) +{ + unsigned int temp; + unsigned int i; + + nct7802y_update(dev, FAN_ENABLE, 0, FANx_ENABLE(fan)); + + /* By default, do not map any temperature control to the fan. */ + for (temp = 0; temp < 3; ++temp) { + nct7802y_update(dev, TEMP_TO_FAN_MAP(temp), + TEMPx_TO_FANy_MAP(temp, fan), 0); + } + + if (config->mode == FAN_MANUAL) { + nct7802y_write(dev, FAN_CTRL(fan), config->duty_cycle); + } else { + u8 set = 0, div = 1; + if (config->smart.mode == SMART_FAN_RPM) { + set |= CLOSE_LOOP_FANx_EN(fan); + div = 50; + if (config->smart.speed == FAN_SPPED_HIGHSPEED) { + set |= CLOSE_LOOP_FANx_HIGH_RPM(fan); + div = 100; + } + } + nct7802y_update(dev, CLOSE_LOOP_FAN_RPM_CTRL, + CLOSE_LOOP_FANx_EN(fan) | + CLOSE_LOOP_FANx_HIGH_RPM(fan), + set); + + /* Map TEMPx to FANx to make things simple */ + nct7802y_update(dev, TEMP_TO_FAN_MAP(fan), + TEMPx_TO_FAN_MAP_MASK(fan), + TEMPx_TO_FANy_MAP(fan, fan)); + + nct7802y_update(dev, FAN_CTRL_TEMP_SRC(fan), + FAN_CTRL_TEMPx_SRC_MASK(fan), + FAN_CTRL_TEMPx_SRCy( + fan, config->smart.tempsrc)); + + for (i = 0; i < ARRAY_SIZE(config->smart.table); ++i) { + nct7802y_write(dev, TABLEx_TEMP_POINTy(fan, i), + config->smart.table[i].temp); + nct7802y_write(dev, TABLEx_TARGET_POINTy(fan, i), + config->smart.table[i].target / div); + } + nct7802y_write(dev, TABLEx_TEMP_POINTy(fan, 4), + config->smart.critical_temp); + } +} + +void nct7802y_init_fan(struct device *const dev) +{ + const struct drivers_i2c_nct7802y_config *const config = dev->chip_info; + unsigned int i; + u8 set; + + if (!config) + return; + + if (nct7802y_select_bank(dev, 0) != CB_SUCCESS) + return; + + for (i = 0; i < NCT7802Y_FAN_CNT; ++i) { + if (config->fan[i].mode != FAN_IGNORE) + init_fan(dev, &config->fan[i], i); + } + + switch (config->on_pecierror) { + case PECI_ERROR_KEEP: + set = CLOSE_LOOP_FAN_PECI_ERR_CURR; + break; + case PECI_ERROR_VALUE: + set = CLOSE_LOOP_FAN_PECI_ERR_VALUE; + break; + case PECI_ERROR_FULLSPEED: + set = CLOSE_LOOP_FAN_PECI_ERR_MAX; + break; + default: + set = 0; + break; + } + nct7802y_update(dev, CLOSE_LOOP_FAN_RPM_CTRL, + CLOSE_LOOP_FAN_PECI_ERR_MASK, set); + nct7802y_write(dev, FAN_DUTY_ON_PECI_ERROR, config->pecierror_minduty); +} diff --git a/src/drivers/i2c/nct7802y/nct7802y_peci.c b/src/drivers/i2c/nct7802y/nct7802y_peci.c new file mode 100644 index 0000000..26e62a3 --- /dev/null +++ b/src/drivers/i2c/nct7802y/nct7802y_peci.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <device/device.h> + +#include "nct7802y.h" +#include "chip.h" + +void nct7802y_init_peci(struct device *const dev) +{ + const struct drivers_i2c_nct7802y_config *const config = dev->chip_info; + unsigned int i, all_off = 1; + + /* Bank 1 can only be written to if PECI reading is enabled */ + if (nct7802y_select_bank(dev, 0) != CB_SUCCESS) + return; + nct7802y_update(dev, PECI_ENABLE, 0, PECI_ENABLE_AGENTx(0)); + + if (nct7802y_select_bank(dev, 1) != CB_SUCCESS) + return; + + for (i = 0; i < NCT7802Y_PECI_CNT; ++i) { + if (config->peci[i].mode != PECI_DISABLED) { + u8 ctrl3 = 0, style = 0; + switch (config->peci[i].mode) { + case PECI_DOMAIN_0: + ctrl3 = PECI_CTRL_3_EN_AGENTx(i); + style = PECI_TEMP_STYLE_DOM0_AGENTx(i) | + PECI_TEMP_STYLE_SINGLE; + break; + case PECI_DOMAIN_1: + ctrl3 = PECI_CTRL_3_EN_AGENTx(i) | + PECI_CTRL_3_HAS_DOM1_AGENTx(i); + style = PECI_TEMP_STYLE_DOM1_AGENTx(i) | + PECI_TEMP_STYLE_SINGLE; + break; + case PECI_HIGHEST: + ctrl3 = PECI_CTRL_3_EN_AGENTx(i) | + PECI_CTRL_3_HAS_DOM1_AGENTx(i); + style = PECI_TEMP_STYLE_HIGHEST; + break; + default: + break; + } + nct7802y_update(dev, PECI_CTRL_1, + PECI_CTRL_1_MANUAL_EN, + PECI_CTRL_1_EN | + PECI_CTRL_1_ROUTINE_EN); + nct7802y_update(dev, PECI_CTRL_3, + PECI_CTRL_3_HAS_DOM1_AGENTx(i), ctrl3); + nct7802y_update(dev, PECI_REPORT_TEMP_STYLE, + PECI_TEMP_STYLE_DOM1_AGENTx(i) | + PECI_TEMP_STYLE_HIGHEST, + style); + nct7802y_write(dev, PECI_BASE_TEMP_AGENT(i), + config->peci[i].base_temp); + all_off = 0; + } else { + nct7802y_update(dev, PECI_CTRL_3, + PECI_CTRL_3_EN_AGENTx(i), 0); + } + } + + if (all_off) + nct7802y_update(dev, PECI_CTRL_1, PECI_CTRL_1_EN, 0); + + /* Disable PECI #0 reading if we only enabled it to access bank 1 */ + if (config->peci[0].mode == PECI_DISABLED) { + if (nct7802y_select_bank(dev, 0) != CB_SUCCESS) + return; + + nct7802y_update(dev, PECI_ENABLE, PECI_ENABLE_AGENTx(0), 0); + } +} -- To view, visit https://review.coreboot.org/29475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I35ea79e12941804e398c6304a08170a776f4ca76 Gerrit-Change-Number: 29475 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

1 0

Change in coreboot[master]: device/root_device: Scan bridges on LPC bus too
by Nico Huber (Code Review) 05 Nov '18

05 Nov '18

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29474 Change subject: device/root_device: Scan bridges on LPC bus too ...................................................................... device/root_device: Scan bridges on LPC bus too Change-Id: I0eb005e41b9168fffc344ee8e666d43b605a30ba Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/device/root_device.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/29474/1 diff --git a/src/device/root_device.c b/src/device/root_device.c index e006bf9..9891401 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -65,10 +65,15 @@ void scan_lpc_bus(struct device *bus) { + struct bus *link; + printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(bus)); scan_static_bus(bus); + for (link = bus->link_list; link; link = link->next) + scan_bridges(link); + printk(BIOS_SPEW, "%s for %s done\n", __func__, dev_path(bus)); } -- To view, visit https://review.coreboot.org/29474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0eb005e41b9168fffc344ee8e666d43b605a30ba Gerrit-Change-Number: 29474 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

1 0

Change in coreboot[master]: Linuxboot: add current kernel releases
by Marcello Sylvester Bauer (Code Review) 05 Nov '18

05 Nov '18

Marcello Sylvester Bauer has posted comments on this change. ( https://review.coreboot.org/29443 ) Change subject: Linuxboot: add current kernel releases ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/29443 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ieb071696cfbb466521faaef045fc488a06f6db0c Gerrit-Change-Number: 29443 Gerrit-PatchSet: 7 Gerrit-Owner: Marcello Sylvester Bauer <info(a)marcellobauer.com> Gerrit-Reviewer: Marcello Sylvester Bauer <info(a)marcellobauer.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 05 Nov 2018 17:31:19 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/google/kahlee/variants/liara: adjust 20ms for edp panel power sequ...
by Richard Spiegel (Code Review) 05 Nov '18

05 Nov '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/29473 ) Change subject: mb/google/kahlee/variants/liara: adjust 20ms for edp panel power sequences ...................................................................... Patch Set 1: (3 comments) https://review.coreboot.org/#/c/29473/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29473/1//COMMIT_MSG@7 PS1, Line 7: a Capital letter https://review.coreboot.org/#/c/29473/1//COMMIT_MSG@9 PS1, Line 9: a Capital letter https://review.coreboot.org/#/c/29473/1//COMMIT_MSG@12 PS1, Line 12: Add a dot to the end of line. -- To view, visit https://review.coreboot.org/29473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iab46f6fc653047a1ec6e8528eefa0999d7019690 Gerrit-Change-Number: 29473 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com> Gerrit-Comment-Date: Mon, 05 Nov 2018 17:07:55 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/google/kahlee: edp panel initialization time tuning
by Richard Spiegel (Code Review) 05 Nov '18

05 Nov '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/29469 ) Change subject: mb/google/kahlee: edp panel initialization time tuning ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/29469/4/src/soc/amd/stoneyridge/chip.h File src/soc/amd/stoneyridge/chip.h: https://review.coreboot.org/#/c/29469/4/src/soc/amd/stoneyridge/chip.h@66 PS4, Line 66: u8 lvds_poseq_varybl_to_blon; : u8 lvds_poseq_blon_to_varybl; : } I see in subsequent patch that it's unit of 4 milliseconds. Add that information here. -- To view, visit https://review.coreboot.org/29469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb Gerrit-Change-Number: 29469 Gerrit-PatchSet: 4 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com> Gerrit-Comment-Date: Mon, 05 Nov 2018 17:00:44 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: mb/google/kahlee: edp panel initialization time tuning
by Richard Spiegel (Code Review) 05 Nov '18

05 Nov '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/29469 ) Change subject: mb/google/kahlee: edp panel initialization time tuning ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/29469/4//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29469/4//COMMIT_MSG@12 PS4, Line 12: GPIO EP133 to high as default This makes no sense with the actual code change. Originally it was being set to HIGH, now is being set to LOW. Add some explanation to gpio.c or add a better explanation here. -- To view, visit https://review.coreboot.org/29469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb Gerrit-Change-Number: 29469 Gerrit-PatchSet: 4 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com> Gerrit-Comment-Date: Mon, 05 Nov 2018 16:58:25 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/common/block/acpi: fix P-States extra entry
by build bot (Jenkins) (Code Review) 05 Nov '18

05 Nov '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25429 ) Change subject: soc/intel/common/block/acpi: fix P-States extra entry ...................................................................... Patch Set 6: (3 comments) https://review.coreboot.org/#/c/25429/6/src/soc/intel/common/block/acpi/acp… File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/#/c/25429/6/src/soc/intel/common/block/acpi/acp… PS6, Line 328: if (((ratio_max - ratio_min) % ratio_step) > 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/25429/6/src/soc/intel/common/block/acpi/acp… PS6, Line 331: if (turbo) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/25429/6/src/soc/intel/common/block/acpi/acp… PS6, Line 334: if (num_entries > PSS_MAX_ENTRIES) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/25429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I91090b4d87eb82b57055c24271d679d1cbb3b7a7 Gerrit-Change-Number: 25429 Gerrit-PatchSet: 6 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-Comment-Date: Mon, 05 Nov 2018 15:25:51 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/kahlee/variants/liara: adjust 20ms for edp panel power sequ...
by chris wang (Code Review) 05 Nov '18

05 Nov '18

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/29473 to review the following change. Change subject: mb/google/kahlee/variants/liara: adjust 20ms for edp panel power sequences ...................................................................... mb/google/kahlee/variants/liara: adjust 20ms for edp panel power sequences add 20ms adjust timing for edp panel in devicetree. BUG=b:118011567 TEST=verify panel sequences by ODM Change-Id: Iab46f6fc653047a1ec6e8528eefa0999d7019690 Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> --- M src/mainboard/google/kahlee/variants/liara/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/29473/1 diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/devicetree.cb index 343fbeb..eef984a 100644 --- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/liara/devicetree.cb @@ -20,6 +20,8 @@ register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" register "uma_size" = "32 * MiB" + register "lvds_poseq_varybl_to_blon" = "0x5" # in 4ms + register "lvds_poseq_blon_to_varybl" = "0x5" # in 4ms # Enable I2C0 for audio, USB3 hub at 400kHz register "i2c[0]" = "{ -- To view, visit https://review.coreboot.org/29473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iab46f6fc653047a1ec6e8528eefa0999d7019690 Gerrit-Change-Number: 29473 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com>

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Change in coreboot[master]: MAINTAINERS: Clarify this is about active upstream development
by Angel Pons (Code Review) 05 Nov '18

05 Nov '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/29471 ) Change subject: MAINTAINERS: Clarify this is about active upstream development ...................................................................... Patch Set 1: Code-Review+1 (2 comments) IMHO, this is a good idea. https://review.coreboot.org/#/c/29471/1/MAINTAINERS File MAINTAINERS: https://review.coreboot.org/#/c/29471/1/MAINTAINERS@76 PS1, Line 76: Should > Must, if we want to automate adding them as reviewers (which has been on the agenda for a while) Definitely yes. I don't think it is possible for someone to be a reviewer if they don't even have an account on review.coreboot.org https://review.coreboot.org/#/c/29471/1/MAINTAINERS@86 PS1, Line 86: react > in a timely manner Definitely yes. -- To view, visit https://review.coreboot.org/29471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9ee038dc5ee1f4993ba1d230ef6e737f20e2ff8a Gerrit-Change-Number: 29471 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Mon, 05 Nov 2018 13:57:08 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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coreboot-gerrit November 2018