coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

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1699 discussions

Change in coreboot[master]: mb/google/poppy/variant/nocturne: use PLTRST for GPP_C11
by Furquan Shaikh (Code Review) 06 Nov '18

06 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/29429 ) Change subject: mb/google/poppy/variant/nocturne: use PLTRST for GPP_C11 ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/29429/2/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nocturne/gpio.c: https://review.coreboot.org/#/c/29429/2/src/mainboard/google/poppy/variants… PS2, Line 138: PLTRST > Not sure how to reconcile the behavior in that case to ensure it doesn't have issues. Yeah, especially if we end up using the same pin for APIC(interrupts) and SCI(wake), we cannot use PLTRST. Would that always result in interrupt storms? Or is it just specific to this device and kernel driver and hence resulting in a storm. -- To view, visit https://review.coreboot.org/29429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I008532fce963c51a435378001440ac72b5ebfffc Gerrit-Change-Number: 29429 Gerrit-PatchSet: 4 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Nov 2018 22:11:18 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: use PLTRST for GPP_C11
by Nick Vaccaro (Code Review) 06 Nov '18

06 Nov '18

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/29429 ) Change subject: mb/google/poppy/variant/nocturne: use PLTRST for GPP_C11 ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/29429/2/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nocturne/gpio.c: https://review.coreboot.org/#/c/29429/2/src/mainboard/google/poppy/variants… PS2, Line 138: PLTRST > I was wondering the same thing when I added sarien/arcada. […] I think you're correct. GPP_C9 did not like being set to PLTRST, it kept device from being able to enter S3. -- To view, visit https://review.coreboot.org/29429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I008532fce963c51a435378001440ac72b5ebfffc Gerrit-Change-Number: 29429 Gerrit-PatchSet: 4 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Nov 2018 21:55:16 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: use PLTRST for GPP_C11
by Duncan Laurie (Code Review) 06 Nov '18

06 Nov '18

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/29429 ) Change subject: mb/google/poppy/variant/nocturne: use PLTRST for GPP_C11 ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/29429/2/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nocturne/gpio.c: https://review.coreboot.org/#/c/29429/2/src/mainboard/google/poppy/variants… PS2, Line 138: PLTRST > I had read in another CL yesterday (that I'm having trouble finding again to include here, sorry) th […] I was wondering the same thing when I added sarien/arcada. It does make sense that you would want the status to get reset on PLRST assertion for regular interrupt pins. But probably not if the pin is expected to be able to wake? (like Furquan's comment above) Not sure how to reconcile the behavior in that case to ensure it doesn't have issues. -- To view, visit https://review.coreboot.org/29429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I008532fce963c51a435378001440ac72b5ebfffc Gerrit-Change-Number: 29429 Gerrit-PatchSet: 4 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Nov 2018 21:51:27 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: use PLTRST for GPP_C11
by Nick Vaccaro (Code Review) 06 Nov '18

06 Nov '18

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/29429 ) Change subject: mb/google/poppy/variant/nocturne: use PLTRST for GPP_C11 ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/29429/2/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nocturne/gpio.c: https://review.coreboot.org/#/c/29429/2/src/mainboard/google/poppy/variants… PS2, Line 138: PLTRST > Any update on this? I had read in another CL yesterday (that I'm having trouble finding again to include here, sorry) that interrupts using GPI_APIC needed to use PLTRST to assure status gets reset properly across S3, which does match the behavior we were seeing when set to DEEP. Are you aware of this requirement / was the comment I read correct? I noticed that seems to hold true in a lot of other board's files, most use PLTRST with PAD_CFG_GPI_APIC(), although there are some poppy outliers (atlas, rammus, and nautilus). Do those boards use S3? I see that the SAR sensor GPIOs defined in this file need this change as well. We're not using the SAR sensors on nocturne right now, which is likely why it hasn't shown up as an issue. I'll fix that in a separate CL. -- To view, visit https://review.coreboot.org/29429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I008532fce963c51a435378001440ac72b5ebfffc Gerrit-Change-Number: 29429 Gerrit-PatchSet: 4 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Nov 2018 21:46:01 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: use PLTRST for GPP_C11
by Furquan Shaikh (Code Review) 06 Nov '18

06 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/29429 ) Change subject: mb/google/poppy/variant/nocturne: use PLTRST for GPP_C11 ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/29429/2/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nocturne/gpio.c: https://review.coreboot.org/#/c/29429/2/src/mainboard/google/poppy/variants… PS2, Line 138: PLTRST > So does it mean that there was some pending interrupt that wasn't getting handled by the kernel driv […] Any update on this? -- To view, visit https://review.coreboot.org/29429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I008532fce963c51a435378001440ac72b5ebfffc Gerrit-Change-Number: 29429 Gerrit-PatchSet: 4 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 06 Nov 2018 20:18:39 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: use PLTRST for GPP_C11
by Furquan Shaikh (Code Review) 06 Nov '18

06 Nov '18

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Change in coreboot[master]: WIP: enable ISH in arcada
by Li1 Feng (Code Review) 06 Nov '18

06 Nov '18

Li1 Feng has uploaded this change for review. ( https://review.coreboot.org/29518 Change subject: WIP: enable ISH in arcada ...................................................................... WIP: enable ISH in arcada gpio C12/ C13 configured as ISH UART1 Change-Id: I83861e32dbeeb06005c9435ba460d28756080f2d Signed-off-by: li feng <li1.feng(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/arcada/gpio.c 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/29518/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index e3b9680..b92677e 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -108,6 +108,7 @@ device pci 12.0 on end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 + device pci 13.0 on end # Integrated Sensor Hub device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.5 off end # SDCard diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index eb4ee76..a5440a0 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -81,9 +81,8 @@ /* UART0_TXD */ PAD_NC(GPP_C9, NONE), /* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */ /* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */ -/* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP, - EDGE_SINGLE), /* SIO_EXT_WAKE# */ -/* UART1_TXD */ PAD_NC(GPP_C13, NONE), +/* UART1_RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), +/* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* LCD_CBL_DET# */ /* UART1_CTS# */ PAD_NC(GPP_C15, NONE), /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TS_I2C_SDA */ -- To view, visit https://review.coreboot.org/29518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I83861e32dbeeb06005c9435ba460d28756080f2d Gerrit-Change-Number: 29518 Gerrit-PatchSet: 1 Gerrit-Owner: Li1 Feng <li1.feng(a)intel.com>

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Change in coreboot[master]: soc/intel: Hook up FSP 1.0 for FSP repo
by Philipp Deppenwiese (Code Review) 06 Nov '18

06 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29517 to look at the new patch set (#4). Change subject: soc/intel: Hook up FSP 1.0 for FSP repo ...................................................................... soc/intel: Hook up FSP 1.0 for FSP repo * Add Rangeley and Baytrail support. * Broadwell DE is buggy atm and I have already requested support from Intel * Disable warnings as errors as long issues are not resolved * Delete code and headers for repo use. Change-Id: I17d9a4c1ffea86ca1a87e5eef5c15f510624d5a9 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M Makefile.inc M src/Kconfig M src/drivers/intel/fsp1_0/Kconfig M src/drivers/intel/fsp1_0/Makefile.inc M src/northbridge/intel/fsp_rangeley/fsp/Kconfig M src/soc/intel/fsp_baytrail/fsp/Kconfig M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c M src/soc/intel/fsp_broadwell_de/fsp/Kconfig M src/vendorcode/intel/Makefile.inc D src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_1gb.absf D src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_2gb.absf D src/vendorcode/intel/fsp1_0/baytrail/include/azalia.h D src/vendorcode/intel/fsp1_0/baytrail/include/fsp.h D src/vendorcode/intel/fsp1_0/baytrail/include/fspapi.h D src/vendorcode/intel/fsp1_0/baytrail/include/fspffs.h D src/vendorcode/intel/fsp1_0/baytrail/include/fspfv.h D src/vendorcode/intel/fsp1_0/baytrail/include/fsphob.h D src/vendorcode/intel/fsp1_0/baytrail/include/fspinfoheader.h D src/vendorcode/intel/fsp1_0/baytrail/include/fspplatform.h D src/vendorcode/intel/fsp1_0/baytrail/include/fsptypes.h D src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h D src/vendorcode/intel/fsp1_0/baytrail/srx/board_fsp.c D src/vendorcode/intel/fsp1_0/baytrail/srx/fsphob.c D src/vendorcode/intel/fsp1_0/rangeley/include/fspapi.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspbootmode.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspffs.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspfv.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h D src/vendorcode/intel/fsp1_0/rangeley/include/fsphob.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspinfoheader.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h D src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h D src/vendorcode/intel/fsp1_0/rangeley/srx/fsp_support.c D src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c 36 files changed, 74 insertions(+), 5,481 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29517/4 -- To view, visit https://review.coreboot.org/29517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I17d9a4c1ffea86ca1a87e5eef5c15f510624d5a9 Gerrit-Change-Number: 29517 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: HACK: Julius' changes for v17
by Julius Werner (Code Review) 06 Nov '18

06 Nov '18

Julius Werner has abandoned this change. ( https://review.coreboot.org/29232 ) Change subject: HACK: Julius' changes for v17 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/29232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I0cd7f0deadb001b2492deadb001811713c547649 Gerrit-Change-Number: 29232 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel: Hook up FSP 1.0 for FSP repo
by Philipp Deppenwiese (Code Review) 06 Nov '18

06 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29517 to look at the new patch set (#3). Change subject: soc/intel: Hook up FSP 1.0 for FSP repo ...................................................................... soc/intel: Hook up FSP 1.0 for FSP repo * Add Rangeley and Baytrail support. * Broadwell DE is buggy atm and I have already requested support from Intel * Disable warnings as errors as long issues are not resolved * Delete code and headers for repo use. Change-Id: I17d9a4c1ffea86ca1a87e5eef5c15f510624d5a9 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M Makefile.inc M src/Kconfig M src/drivers/intel/fsp1_0/Kconfig M src/drivers/intel/fsp1_0/Makefile.inc M src/northbridge/intel/fsp_rangeley/fsp/Kconfig M src/soc/intel/fsp_baytrail/fsp/Kconfig M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c M src/soc/intel/fsp_broadwell_de/fsp/Kconfig M src/vendorcode/intel/Makefile.inc D src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_1gb.absf D src/vendorcode/intel/fsp1_0/baytrail/absf/minnowmax_2gb.absf D src/vendorcode/intel/fsp1_0/baytrail/include/azalia.h D src/vendorcode/intel/fsp1_0/baytrail/include/fsp.h D src/vendorcode/intel/fsp1_0/baytrail/include/fspapi.h D src/vendorcode/intel/fsp1_0/baytrail/include/fspffs.h D src/vendorcode/intel/fsp1_0/baytrail/include/fspfv.h D src/vendorcode/intel/fsp1_0/baytrail/include/fsphob.h D src/vendorcode/intel/fsp1_0/baytrail/include/fspinfoheader.h D src/vendorcode/intel/fsp1_0/baytrail/include/fspplatform.h D src/vendorcode/intel/fsp1_0/baytrail/include/fsptypes.h D src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h D src/vendorcode/intel/fsp1_0/baytrail/srx/board_fsp.c D src/vendorcode/intel/fsp1_0/baytrail/srx/fsphob.c D src/vendorcode/intel/fsp1_0/rangeley/include/fspapi.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspbootmode.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspffs.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspfv.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h D src/vendorcode/intel/fsp1_0/rangeley/include/fsphob.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspinfoheader.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h D src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h D src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h D src/vendorcode/intel/fsp1_0/rangeley/srx/fsp_support.c D src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c 36 files changed, 74 insertions(+), 5,481 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29517/3 -- To view, visit https://review.coreboot.org/29517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I17d9a4c1ffea86ca1a87e5eef5c15f510624d5a9 Gerrit-Change-Number: 29517 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit November 2018