Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/29469 )
Change subject: mb/google/kahlee: edp panel initialization time tuning
......................................................................
Patch Set 6:
(5 comments)
Sorry I did not noticed the other issues in the commit message... The explanation on commit message is now clear, thanks.
https://review.coreboot.org/#/c/29469/6//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/29469/6//COMMIT_MSG@7
PS6, Line 7: e
Capital letter
https://review.coreboot.org/#/c/29469/6//COMMIT_MSG@9
PS6, Line 9: a
Capital letter
https://review.coreboot.org/#/c/29469/6//COMMIT_MSG@12
PS6, Line 12: t
Capital letter
https://review.coreboot.org/#/c/29469/6//COMMIT_MSG@17
PS6, Line 17: emerge-grunt coreboot
Add a dot to the end.
https://review.coreboot.org/#/c/29469/6/src/soc/amd/stoneyridge/chip.h
File src/soc/amd/stoneyridge/chip.h:
https://review.coreboot.org/#/c/29469/6/src/soc/amd/stoneyridge/chip.h@67
PS6, Line 67: * This specifies the LVDS/eDP power up sequence time for the delay from
: * active to active.
: * 0 - Use the VBIOS default (default). The video BIOS default is 32ms.
: * n - Values other than zero specify a setting of (4 * n) milliseconds
: * time delay.
:
Nice, I like it.
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Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/29473 )
Change subject: mb/google/kahlee/variants/liara: Adjust 20ms for edp panel power sequences
......................................................................
Patch Set 4: Code-Review+2
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Hello Werner Zeh, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/29513
to look at the new patch set (#2).
Change subject: siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devices
......................................................................
siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devices
On this mainboard there is a legacy PCI device, which is connected to
the PCIe root port via a PCIe-2-PCI bridge. This device only supports
legacy interrupt routing. For this reason we have to adjust the PIR6
register (0x314c) which is responsible for PCIe device 13h and 14h. This
means that the interrupt routing will also be the same for both PCIe
devices. The bridge is connected to PCIe root port 2 and 3 over two
lanes (Device 13.0 and 13.1).
The following routing is required:
INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#->PIRQC#
Change-Id: I5028c26769a2122b1c609ad7789c9949e3cb7a87
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
1 file changed, 3 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/29513/2
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Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/29513
Change subject: siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devices
......................................................................
siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devices
On this mainboard there is a legacy PCI device, which is connected to
the PCIe root port via a PCIe-2-PCI bridge. This device only supports
legacy interrupt routing. For this reason we have to adjust the PIR6
register (0x314c) which is responsible for PCIe device 13h and 14h. This
means that the interrupt routing will also be the same for both PCIe
devices. The bridge is connected to PCIe root port 2 and 3 over two
lanes (Device 13.0 and 13.1).
The following routing is required:
INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#->PIRQC#
Change-Id: I5028c26769a2122b1c609ad7789c9949e3cb7a87
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/29513/1
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
index ccf3ab8..f6858b0 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
@@ -34,9 +34,9 @@
/*
* PIR6 register mapping for PCIe root ports
- * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA#
+ * INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#-> PIRQC#
*/
- pcr_write16(PID_ITSS, 0x314c, 0x0321);
+ pcr_write16(PID_ITSS, 0x314c, 0x2103);
/* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */
dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0);
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/29508 )
Change subject: soc/intel/icelake: Make correct IRQ mapping for ICL SA and PCH PCI devices
......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/29508/3/src/soc/intel/icelake/acpi/pci_irqs…
File src/soc/intel/icelake/acpi/pci_irqs.asl:
https://review.coreboot.org/#/c/29508/3/src/soc/intel/icelake/acpi/pci_irqs…
PS3, Line 137: Return (^PICN)
these are supposed to be PIC interrupts, which are relative to the PRT A-H settings (at least on older hardware). Is this not configurable anymore or what is the reason behind this change, which hardcodes them?
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Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29449 )
Change subject: x86/acpi.c: Be more verbose when finding the wakeup vector
......................................................................
x86/acpi.c: Be more verbose when finding the wakeup vector
Since S3 resume sometimes breaks when trying to find the wakeup vector,
it is useful to log whether it errors or not. Since it is an error,
print it as such.
Change-Id: Ib006c4a213c0da180018e5fbf7a47d6af66f8bc4
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/29449
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
---
M src/arch/x86/acpi.c
1 file changed, 10 insertions(+), 4 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c
index 24db7c0..f54aa19 100644
--- a/src/arch/x86/acpi.c
+++ b/src/arch/x86/acpi.c
@@ -1278,8 +1278,11 @@
break;
}
- if (rsdp == NULL)
+ if (rsdp == NULL) {
+ printk(BIOS_ALERT,
+ "No RSDP found, wake up from S3 not possible.\n");
return NULL;
+ }
printk(BIOS_DEBUG, "RSDP found at %p\n", rsdp);
rsdt = (acpi_rsdt_t *)(uintptr_t)rsdp->rsdt_address;
@@ -1294,15 +1297,18 @@
fadt = NULL;
}
- if (fadt == NULL)
+ if (fadt == NULL) {
+ printk(BIOS_ALERT,
+ "No FADT found, wake up from S3 not possible.\n");
return NULL;
+ }
printk(BIOS_DEBUG, "FADT found at %p\n", fadt);
facs = (acpi_facs_t *)(uintptr_t)fadt->firmware_ctrl;
if (facs == NULL) {
- printk(BIOS_DEBUG, "No FACS found, wake up from S3 not "
- "possible.\n");
+ printk(BIOS_ALERT,
+ "No FACS found, wake up from S3 not possible.\n");
return NULL;
}
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/29509 )
Change subject: soc/intel/icelake: Add PCIE ASL entry
......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/29509/3/src/soc/intel/icelake/acpi/pcie.asl
File src/soc/intel/icelake/acpi/pcie.asl:
https://review.coreboot.org/#/c/29509/3/src/soc/intel/icelake/acpi/pcie.asl…
PS3, Line 27: Package () { 0x0000ffff, 0, 0, 11 },
: Package () { 0x0000ffff, 1, 0, 10 },
: Package () { 0x0000ffff, 2, 0, 11 },
: Package () { 0x0000ffff, 3, 0, 11 } })
you are mapping multiple pins to the same link?
Could you explain it in the commit message as the commit message does not seem to match at all what you are doing...
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