Joel Kitching has uploaded a new patch set (#2). ( https://review.coreboot.org/29026 )
Change subject: tpm: clean up tpm_setup function flow
......................................................................
tpm: clean up tpm_setup function flow
Introduce two helper functions for more readable code.
BUG=None
TEST=None
Change-Id: Ibea44880683a301e82ee2ba049003c36fcb44eba
Signed-off-by: Joel Kitching <kitching(a)google.com>
---
M src/security/tpm/tspi/tspi.c
1 file changed, 37 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/29026/2
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ibea44880683a301e82ee2ba049003c36fcb44eba
Gerrit-Change-Number: 29026
Gerrit-PatchSet: 2
Gerrit-Owner: Joel Kitching <kitching(a)google.com>
Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/29025
Change subject: cbfstool: make comments more consistent
......................................................................
cbfstool: make comments more consistent
Fix a typo and make comments more consistent (start with
capital letter).
BUG=None
TEST=None
Change-Id: I97bff5e05596fc6973f0729e276a2e45b291120d
---
M util/cbfstool/cbfstool.c
1 file changed, 15 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/29025/1
diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index f8b1f65..28e0e5d 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -87,7 +87,7 @@
enum comp_algo compression;
int precompression;
enum vb2_hash_algorithm hash;
- /* for linux payloads */
+ /* For linux payloads */
char *initrd;
char *cmdline;
int force;
@@ -140,7 +140,7 @@
{
assert(region);
- /* cover the situation where a negative base address is given by the
+ /* Cover the situation where a negative base address is given by the
* user. Callers of this function negate it, so it'll be a positive
* number smaller than the region.
*/
@@ -283,7 +283,7 @@
static void fill_header_offset(void *location, uint32_t offset)
{
- // TODO: when we have a BE target, we'll need to store this as BE
+ // TODO: When we have a BE target, we'll need to store this as BE
write_le32(location, offset);
}
@@ -384,7 +384,7 @@
buffer_size(&image.buffer) - 4);
fill_header_offset(h_loc, header_offset);
/*
- * if top swap present, update the header
+ * If top swap present, update the header
* location in secondary bootblock
*/
if (param.topswap_size) {
@@ -413,7 +413,7 @@
}
/*
- * allocate topswap_size*2 bytes for bootblock to
+ * Allocate topswap_size*2 bytes for bootblock to
* accommodate the second bootblock.
*/
struct buffer new_bootblock, bb1, bb2;
@@ -427,15 +427,15 @@
buffer_size(&new_bootblock) - bb_buf_size,
bb_buf_size);
- /* copy to first bootblock */
+ /* Copy to first bootblock */
memcpy(buffer_get(&bb1), buffer_get(buffer), bb_buf_size);
- /* copy to second bootblock */
+ /* Copy to second bootblock */
memcpy(buffer_get(&bb2), buffer_get(buffer), bb_buf_size);
buffer_delete(buffer);
buffer_clone(buffer, &new_bootblock);
- /* update the location (offset) of bootblock in the region */
+ /* Update the location (offset) of bootblock in the region */
*offset = convert_to_from_top_aligned(param.image_region,
buffer_size(buffer));
@@ -633,7 +633,6 @@
* mapped one.
* If the FSP component is not xip, then use param.baseaddress that is
* passed in by the caller.
- *
*/
if (param.stage_xip) {
if (!IS_TOP_ALIGNED_ADDRESS(address))
@@ -711,7 +710,7 @@
/*
* Ensure the address is a memory mapped one. This assumes
- * x86 semantics about th boot media being directly mapped
+ * x86 semantics about the boot media being directly mapped
* below 4GiB in the CPU address space.
**/
address = -convert_to_from_absolute_top_aligned(
@@ -727,7 +726,7 @@
if (ret != 0)
return -1;
buffer_delete(buffer);
- // direct assign, no dupe.
+ // Direct assign, no dupe.
memcpy(buffer, &output, sizeof(*buffer));
header->len = htonl(output.size);
return 0;
@@ -738,7 +737,7 @@
{
struct buffer output;
int ret;
- /* per default, try and see if payload is an ELF binary */
+ /* Per default, try and see if payload is an ELF binary */
ret = parse_elf_to_payload(buffer, &output, param.compression);
/* If it's not an ELF, see if it's a FIT */
@@ -765,7 +764,7 @@
}
buffer_delete(buffer);
- // direct assign, no dupe.
+ // Direct assign, no dupe.
memcpy(buffer, &output, sizeof(*buffer));
header->len = htonl(output.size);
return 0;
@@ -782,7 +781,7 @@
return -1;
}
buffer_delete(buffer);
- // direct assign, no dupe.
+ // Direct assign, no dupe.
memcpy(buffer, &output, sizeof(*buffer));
header->len = htonl(output.size);
return 0;
@@ -1215,7 +1214,7 @@
uint32_t addr = 0;
/*
- * get the address of provided region for first row.
+ * Get the address of provided region for first row.
*/
if (param.ucode_region) {
struct buffer ucode;
@@ -1558,7 +1557,7 @@
break;
}
- /* filter out illegal long options */
+ /* Filter out illegal long options */
if (strchr(commands[i].optstring, c) == NULL) {
/* TODO maybe print actual long option instead */
ERROR("%s: invalid option -- '%c'\n",
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I97bff5e05596fc6973f0729e276a2e45b291120d
Gerrit-Change-Number: 29025
Gerrit-PatchSet: 1
Gerrit-Owner: Joel Kitching <kitching(a)google.com>
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/29023
to look at the new patch set (#2).
Change subject: riscv: add support smp_pause / smp_resume
......................................................................
riscv: add support smp_pause / smp_resume
See https://doc.coreboot.org/arch/riscv/ we know that we need to execute
smp_pause at the start of each stage and smp_resume at the end of each
stage.
Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb
Signed-off-by: Xiang Wang <wxjstz(a)126.com>
---
M src/arch/riscv/Kconfig
A src/arch/riscv/include/arch/smp/smp.h
M src/arch/riscv/include/mcall.h
3 files changed, 64 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/29023/2
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb
Gerrit-Change-Number: 29023
Gerrit-PatchSet: 2
Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/29023
Change subject: riscv: add support smp_pause / smp_resume
......................................................................
riscv: add support smp_pause / smp_resume
See https://doc.coreboot.org/arch/riscv/ we know that we need to execute
smp_pause at the start of each stage and smp_resume at the end of each
stage.
Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb
Signed-off-by: Xiang Wang <wxjstz(a)126.com>
---
M src/arch/riscv/Kconfig
A src/arch/riscv/include/arch/smp/smp.h
M src/arch/riscv/include/mcall.h
3 files changed, 66 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/29023/1
diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig
index 2d53f42..96179a5 100644
--- a/src/arch/riscv/Kconfig
+++ b/src/arch/riscv/Kconfig
@@ -32,3 +32,7 @@
config RISCV_USE_ARCH_TIMER
bool
default n
+
+config RISCV_HART_NUM
+ int
+
diff --git a/src/arch/riscv/include/arch/smp/smp.h b/src/arch/riscv/include/arch/smp/smp.h
new file mode 100644
index 0000000..7431142
--- /dev/null
+++ b/src/arch/riscv/include/arch/smp/smp.h
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 HardenedLinux.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _RISCV_SMP_H
+#define _RISCV_SMP_H
+
+#include <arch/encoding.h>
+#include <arch/smp/spinlock.h>
+#include <mcall.h>
+#include <commonlib/compiler.h>
+
+void set_msip(int hartid, int val);
+
+static inline void smp_pause(void)
+{
+ if (read_csr(mhartid) == 0)
+ return;
+ clear_csr(mstatus, MSTATUS_MIE);
+ write_csr(mie, MIP_MSIP);
+ do {
+ barrier();
+ __asm__ volatile ("wfi");
+ } while ((read_csr(mip) & MIP_MSIP) == 0);
+ set_msip(read_csr(mhartid), 0);
+ HLS()->entry.fn(HLS()->entry.arg);
+}
+
+static inline void smp_resume(void (*fn)(void *), void *arg)
+{
+ int hartid = read_csr(mhartid);
+ for (int i = 0; i < CONFIG_RISCV_HART_NUM; i++) {
+ OTHER_HLS(i)->entry.fn = fn;
+ OTHER_HLS(i)->entry.arg = arg;
+ }
+
+ for (int i = 0; i < CONFIG_RISCV_HART_NUM; i++)
+ if (i != hartid)
+ set_msip(i, 1);
+
+ HLS()->entry.fn(HLS()->entry.arg);
+}
+
+#endif
+
diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h
index d1e414a..3e559f7 100644
--- a/src/arch/riscv/include/mcall.h
+++ b/src/arch/riscv/include/mcall.h
@@ -18,7 +18,7 @@
// NOTE: this is the size of hls_t below. A static_assert would be
// nice to have.
-#define HLS_SIZE 64
+#define HLS_SIZE 80
/* We save 37 registers, currently. */
#define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * 8)
@@ -35,6 +35,10 @@
unsigned long sbi_private_data;
} sbi_device_message;
+struct blocker {
+ void *arg;
+ void (*fn)(void *arg);
+};
typedef struct {
sbi_device_message *device_request_queue_head;
@@ -46,6 +50,7 @@
int ipi_pending;
uint64_t *timecmp;
uint64_t *time;
+ struct blocker entry;
} hls_t;
#define MACHINE_STACK_TOP() ({ \
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb
Gerrit-Change-Number: 29023
Gerrit-PatchSet: 1
Gerrit-Owner: Xiang Wang <wxjstz(a)126.com>
Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/29022
Change subject: mb/google/poppy/variants/nami: Disable rear camera/DMIC for Syndra
......................................................................
mb/google/poppy/variants/nami: Disable rear camera/DMIC for Syndra
Since there are two cameras on Nami and only one camera on Syndra.
We need to disable rear camera/DMIC on all Syndra sku.
BUG=b:112876867
Change-Id: I92fb43ec84387c268ffdb6d0d34a5e5b13bcf50a
Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com>
---
M src/mainboard/google/poppy/variants/nami/gpio.c
M src/mainboard/google/poppy/variants/nami/include/variant/sku.h
M src/mainboard/google/poppy/variants/nami/mainboard.c
3 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/29022/1
diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c
index 2d0fea4..1a03c05 100644
--- a/src/mainboard/google/poppy/variants/nami/gpio.c
+++ b/src/mainboard/google/poppy/variants/nami/gpio.c
@@ -415,6 +415,10 @@
case SKU_2_VAYNE:
case SKU_0_SONA:
case SKU_1_SONA:
+ case SKU_0_SYNDRA:
+ case SKU_1_SYNDRA:
+ case SKU_2_SYNDRA:
+ case SKU_3_SYNDRA:
*num = ARRAY_SIZE(no_dmic1_sku_gpio_table);
board_gpio_tables = no_dmic1_sku_gpio_table;
break;
diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/sku.h b/src/mainboard/google/poppy/variants/nami/include/variant/sku.h
index d75eb10..e27709a 100644
--- a/src/mainboard/google/poppy/variants/nami/include/variant/sku.h
+++ b/src/mainboard/google/poppy/variants/nami/include/variant/sku.h
@@ -30,5 +30,9 @@
#define SKU_1_AKALI 0x2861
#define SKU_0_AKALI360 0x2BE7
#define SKU_1_AKALI360 0x2A67
+#define SKU_0_SYNDRA 0x2BC63
+#define SKU_1_SYNDRA 0x2BC62
+#define SKU_2_SYNDRA 0x2BC61
+#define SKU_3_SYNDRA 0X2BC60
#endif /* __MAINBOARD_SKU_H__ */
diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c
index 28fa327..7362ba6 100644
--- a/src/mainboard/google/poppy/variants/nami/mainboard.c
+++ b/src/mainboard/google/poppy/variants/nami/mainboard.c
@@ -234,6 +234,10 @@
case SKU_2_PANTHEON:
case SKU_0_SONA:
case SKU_1_SONA:
+ case SKU_0_SYNDRA:
+ case SKU_1_SYNDRA:
+ case SKU_2_SYNDRA:
+ case SKU_3_SYNDRA:
/* Disable unused port USB port */
cfg->usb2_ports[5].enable = 0;
break;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I92fb43ec84387c268ffdb6d0d34a5e5b13bcf50a
Gerrit-Change-Number: 29022
Gerrit-PatchSet: 1
Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com>