coreboot-gerrit October 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/cavium/cn8100_sff_evb: Only expose two UARTs
by Philipp Deppenwiese (Code Review) 11 Oct '18

11 Oct '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/28986 ) Change subject: mb/cavium/cn8100_sff_evb: Only expose two UARTs ...................................................................... mb/cavium/cn8100_sff_evb: Only expose two UARTs Only two UARTs are connected to the FTDI UART USB chip. Change-Id: Id5ae7266ce44c9f64c7f7aeaf23c49122041f47a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/28986 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/mainboard/cavium/cn8100_sff_evb/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb b/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb index 3398e9a..00be155 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb +++ b/src/mainboard/cavium/cn8100_sff_evb/devicetree.cb @@ -93,11 +93,11 @@ end chip soc/cavium/common/pci register "secure" = "1" - device pci 08.2 on end # UUA2 + device pci 08.2 off end # UUA2 end chip soc/cavium/common/pci register "secure" = "1" - device pci 08.3 on end # UUA3 + device pci 08.3 off end # UUA3 end chip soc/cavium/common/pci register "secure" = "1" -- To view, visit https://review.coreboot.org/28986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Id5ae7266ce44c9f64c7f7aeaf23c49122041f47a Gerrit-Change-Number: 28986 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/cavium/cn8100_sff_evb: Only expose two UARTs
by Philipp Deppenwiese (Code Review) 11 Oct '18

11 Oct '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/28986 ) Change subject: mb/cavium/cn8100_sff_evb: Only expose two UARTs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id5ae7266ce44c9f64c7f7aeaf23c49122041f47a Gerrit-Change-Number: 28986 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 11 Oct 2018 00:58:27 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: libpayload: arm64: Make exception handling closer to arm32
by build bot (Jenkins) (Code Review) 11 Oct '18

11 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29018 ) Change subject: libpayload: arm64: Make exception handling closer to arm32 ...................................................................... Patch Set 1: (9 comments) https://review.coreboot.org/#/c/29018/1/payloads/libpayload/include/arm64/a… File payloads/libpayload/include/arm64/arch/exception.h: https://review.coreboot.org/#/c/29018/1/payloads/libpayload/include/arm64/a… PS1, Line 39: #define ESR_EC_UNKNOWN 0b000000 Avoid gcc v4.3+ binary constant extension: <0b000000> https://review.coreboot.org/#/c/29018/1/payloads/libpayload/include/arm64/a… PS1, Line 40: #define ESR_EC_SVC_64 0b010101 Avoid gcc v4.3+ binary constant extension: <0b010101> https://review.coreboot.org/#/c/29018/1/payloads/libpayload/include/arm64/a… PS1, Line 41: #define ESR_EC_INSN_ABT_LOWER 0b100000 Avoid gcc v4.3+ binary constant extension: <0b100000> https://review.coreboot.org/#/c/29018/1/payloads/libpayload/include/arm64/a… PS1, Line 42: #define ESR_EC_INSN_ABT_SAME 0b100001 Avoid gcc v4.3+ binary constant extension: <0b100001> https://review.coreboot.org/#/c/29018/1/payloads/libpayload/include/arm64/a… PS1, Line 43: #define ESR_EC_DATA_ABT_LOWER 0b100100 Avoid gcc v4.3+ binary constant extension: <0b100100> https://review.coreboot.org/#/c/29018/1/payloads/libpayload/include/arm64/a… PS1, Line 44: #define ESR_EC_DATA_ABT_SAME 0b100101 Avoid gcc v4.3+ binary constant extension: <0b100101> https://review.coreboot.org/#/c/29018/1/payloads/libpayload/include/arm64/a… PS1, Line 45: #define ESR_EC_SERROR 0b101111 Avoid gcc v4.3+ binary constant extension: <0b101111> https://review.coreboot.org/#/c/29018/1/payloads/libpayload/include/arm64/a… PS1, Line 46: #define ESR_EC_SS_SAME 0b110011 Avoid gcc v4.3+ binary constant extension: <0b110011> https://review.coreboot.org/#/c/29018/1/payloads/libpayload/include/arm64/a… PS1, Line 47: #define ESR_EC_BKPT_64 0b111100 Avoid gcc v4.3+ binary constant extension: <0b111100> -- To view, visit https://review.coreboot.org/29018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia16a1124be1824392a309ae1f4cb031547d184c1 Gerrit-Change-Number: 29018 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 10 Oct 2018 23:23:06 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: libpayload: arm64: Add GDB support
by build bot (Jenkins) (Code Review) 11 Oct '18

11 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29020 ) Change subject: libpayload: arm64: Add GDB support ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/29020/1/payloads/libpayload/arch/arm64/gdb.c File payloads/libpayload/arch/arm64/gdb.c: https://review.coreboot.org/#/c/29020/1/payloads/libpayload/arch/arm64/gdb.… PS1, Line 49: else switch (exception_state.ec) { trailing statements should be on next line https://review.coreboot.org/#/c/29020/1/payloads/libpayload/arch/arm64/gdb.… PS1, Line 91: asm volatile ("mov %0, sp" : "=r"(sp) ); space prohibited before that close parenthesis ')' -- To view, visit https://review.coreboot.org/29020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2fa4dbca6c39f822f489a5e81bd052f53fda98a5 Gerrit-Change-Number: 29020 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 10 Oct 2018 23:22:07 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: libpayload: arm64: Conform to new coreboot lib_helpers.h and assume EL2
by build bot (Jenkins) (Code Review) 11 Oct '18

11 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29017 ) Change subject: libpayload: arm64: Conform to new coreboot lib_helpers.h and assume EL2 ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29017/1/payloads/libpayload/include/arm64/a… File payloads/libpayload/include/arm64/arch/lib_helpers.h: https://review.coreboot.org/#/c/29017/1/payloads/libpayload/include/arm64/a… PS1, Line 54: #define MAKE_REGISTER_ACCESSORS_EL12(reg) \ Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/29017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic9dfa48411f3805747613f03611f8a134a51cc46 Gerrit-Change-Number: 29017 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 10 Oct 2018 23:21:58 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: amd/stoneyridge: Rearrange southbridge.h
by build bot (Jenkins) (Code Review) 11 Oct '18

11 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29013 ) Change subject: amd/stoneyridge: Rearrange southbridge.h ...................................................................... Patch Set 1: (4 comments) https://review.coreboot.org/#/c/29013/1/src/soc/amd/stoneyridge/include/soc… File src/soc/amd/stoneyridge/include/soc/southbridge.h: https://review.coreboot.org/#/c/29013/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 131: #define CG1PLL_SS_STEP_SIZE_DSFRAC_MASK (0xffff << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT) line over 80 characters https://review.coreboot.org/#/c/29013/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 133: #define CG1PLL_SS_AMOUNT_DSFRAC_MASK (0xffff << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT) line over 80 characters https://review.coreboot.org/#/c/29013/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 136: #define CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK (0xf << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT) line over 80 characters https://review.coreboot.org/#/c/29013/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 166: #define DEBUG_PORT_MASK (BIT(16) | BIT(17) | (BIT(18)) Macros with complex values should be enclosed in parentheses -- To view, visit https://review.coreboot.org/29013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia6ef21431db0e758eba0ea043b54c036ec6235fe Gerrit-Change-Number: 29013 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 10 Oct 2018 23:15:19 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: amd/stoneyridge: Convert hex definitions to lower case
by build bot (Jenkins) (Code Review) 11 Oct '18

11 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29009 ) Change subject: amd/stoneyridge: Convert hex definitions to lower case ...................................................................... Patch Set 1: (5 comments) https://review.coreboot.org/#/c/29009/1/src/soc/amd/stoneyridge/include/soc… File src/soc/amd/stoneyridge/include/soc/southbridge.h: https://review.coreboot.org/#/c/29009/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 381: #define CG1PLL_SS_STEP_SIZE_DSFRAC_MASK (0xffff << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT) line over 80 characters https://review.coreboot.org/#/c/29009/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 383: #define CG1PLL_SS_AMOUNT_DSFRAC_MASK (0xffff << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT) line over 80 characters https://review.coreboot.org/#/c/29009/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 386: #define CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK (0xf << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT) line over 80 characters https://review.coreboot.org/#/c/29009/1/src/soc/amd/stoneyridge/southbridge… File src/soc/amd/stoneyridge/southbridge.c: https://review.coreboot.org/#/c/29009/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 598: cfg4 |= (0xd000 << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT) & CG1PLL_SS_AMOUNT_DSFRAC_MASK; line over 80 characters https://review.coreboot.org/#/c/29009/1/src/soc/amd/stoneyridge/southbridge… PS1, Line 600: cfg4 |= (0x02d5 << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT) & CG1PLL_SS_STEP_SIZE_DSFRAC_MASK; line over 80 characters -- To view, visit https://review.coreboot.org/29009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4531e6dad0362be73499647d9fc93c168b6f163e Gerrit-Change-Number: 29009 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 10 Oct 2018 23:14:41 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: amd/stoneyridge: Fix PmControl register size in SMI handler
by Marshall Dawson (Code Review) 11 Oct '18

11 Oct '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/29016 Change subject: amd/stoneyridge: Fix PmControl register size in SMI handler ...................................................................... amd/stoneyridge: Fix PmControl register size in SMI handler The AMD implementation of this register is only 16 bits. Change the source accordingly. TEST=Suspend/Resume a Grunt several times Change-Id: Ib900468cc1c790fa7d57bb6faa91aee012173f7a Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/smihandler.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/29016/1 diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index eeedba7..8985257 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -122,13 +122,13 @@ static void sb_slp_typ_handler(void) { - uint32_t pm1cnt, pci_ctrl, reg32; - uint16_t reg16; + uint32_t pci_ctrl, reg32; + uint16_t pm1cnt, reg16; uint8_t slp_typ, rst_ctrl; /* Figure out SLP_TYP */ - pm1cnt = inl(pm_acpi_pm_cnt_blk()); - printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", pm1cnt); + pm1cnt = inw(pm_acpi_pm_cnt_blk()); + printk(BIOS_SPEW, "SMI#: SLP = 0x%04x\n", pm1cnt); slp_typ = acpi_sleep_from_pm1(pm1cnt); /* Do any mainboard sleep handling */ @@ -196,7 +196,7 @@ } /* if (IS_ENABLED(CONFIG_ELOG_GSMI)) */ /* Reissue Pm1 write */ - outl(pm1cnt | SLP_EN, pm_acpi_pm_cnt_blk()); + outw(pm1cnt | SLP_EN, pm_acpi_pm_cnt_blk()); hlt(); } } -- To view, visit https://review.coreboot.org/29016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib900468cc1c790fa7d57bb6faa91aee012173f7a Gerrit-Change-Number: 29016 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Rename GppClkCntrl fields
by Marshall Dawson (Code Review) 11 Oct '18

11 Oct '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/29014 Change subject: amd/stoneyridge: Rename GppClkCntrl fields ...................................................................... amd/stoneyridge: Rename GppClkCntrl fields Make the field names of the MISCx00 GPPClkCntrl more manageable by shortening their names. Make the definitions look more like the rest of the header file. Change-Id: I515cd664808e38851a7dbdba899df4fb9bbbcde6 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/mainboard/google/kahlee/mainboard.c M src/soc/amd/stoneyridge/include/soc/southbridge.h 2 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/29014/1 diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index bfd1f2f..ebdcc93 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -146,15 +146,15 @@ /* Set low-power mode for BayHub eMMC bridge's PCIe clock. */ clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL), - GPP_CLK2_CLOCK_REQ_MAP_MASK, - GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 << - GPP_CLK2_CLOCK_REQ_MAP_SHIFT); + GPP_CLK2_REQ_MAP_MASK, + GPP_CLK2_REQ_MAP_CLK_REQ2 << + GPP_CLK2_REQ_MAP_SHIFT); /* Same for the WiFi */ clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL), - GPP_CLK0_CLOCK_REQ_MAP_MASK, - GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 << - GPP_CLK0_CLOCK_REQ_MAP_SHIFT); + GPP_CLK0_REQ_MAP_MASK, + GPP_CLK0_REQ_MAP_CLK_REQ0 << + GPP_CLK0_REQ_MAP_SHIFT); } /************************************************* diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index d25c90b..7f02811 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -111,13 +111,13 @@ /* FCH MISC Registers 0xfed80e00 */ #define GPP_CLK_CNTRL 0 -#define GPP_CLK2_CLOCK_REQ_MAP_SHIFT 8 -#define GPP_CLK2_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK2_CLOCK_REQ_MAP_SHIFT) -#define GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 3 +#define GPP_CLK2_REQ_MAP_SHIFT 8 +#define GPP_CLK2_REQ_MAP_MASK (0xf << GPP_CLK2_REQ_MAP_SHIFT) +#define GPP_CLK2_REQ_MAP_CLK_REQ2 3 -#define GPP_CLK0_CLOCK_REQ_MAP_SHIFT 0 -#define GPP_CLK0_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK0_CLOCK_REQ_MAP_SHIFT) -#define GPP_CLK0_CLOCK_REQ_MAP_CLK_REQ0 1 +#define GPP_CLK0_REQ_MAP_SHIFT 0 +#define GPP_CLK0_REQ_MAP_MASK (0xf << GPP_CLK0_REQ_MAP_SHIFT) +#define GPP_CLK0_REQ_MAP_CLK_REQ0 1 #define MISC_CGPLL_CONFIG1 0x08 #define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0) -- To view, visit https://review.coreboot.org/29014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I515cd664808e38851a7dbdba899df4fb9bbbcde6 Gerrit-Change-Number: 29014 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Rename CGPLL_CONFIG definitions
by Marshall Dawson (Code Review) 11 Oct '18

11 Oct '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/29015 Change subject: amd/stoneyridge: Rename CGPLL_CONFIG definitions ...................................................................... amd/stoneyridge: Rename CGPLL_CONFIG definitions Shorten the names in the MISC CGPLL_CONFIG, and make the formatting match the surrounding source. Change-Id: I71cf1ff6bd4bca7a25484b4da9388c17cfecc043 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 34 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/29015/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 7f02811..896d494 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -110,35 +110,33 @@ #define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) /* FCH MISC Registers 0xfed80e00 */ -#define GPP_CLK_CNTRL 0 -#define GPP_CLK2_REQ_MAP_SHIFT 8 -#define GPP_CLK2_REQ_MAP_MASK (0xf << GPP_CLK2_REQ_MAP_SHIFT) -#define GPP_CLK2_REQ_MAP_CLK_REQ2 3 - -#define GPP_CLK0_REQ_MAP_SHIFT 0 -#define GPP_CLK0_REQ_MAP_MASK (0xf << GPP_CLK0_REQ_MAP_SHIFT) -#define GPP_CLK0_REQ_MAP_CLK_REQ0 1 - -#define MISC_CGPLL_CONFIG1 0x08 -#define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0) -#define MISC_CGPLL_CONFIG3 0x10 -#define CG1PLL_REFDIV_SHIFT 0 -#define CG1PLL_REFDIV_MASK (0x3ff << CG1PLL_REFDIV_SHIFT) -#define CG1PLL_FBDIV_SHIFT 10 -#define CG1PLL_FBDIV_MASK (0xfff << CG1PLL_FBDIV_SHIFT) -#define MISC_CGPLL_CONFIG4 0x14 -#define CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT 0 -#define CG1PLL_SS_STEP_SIZE_DSFRAC_MASK (0xffff << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT) -#define CG1PLL_SS_AMOUNT_DSFRAC_SHIFT 16 -#define CG1PLL_SS_AMOUNT_DSFRAC_MASK (0xffff << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT) -#define MISC_CGPLL_CONFIG5 0x18 -#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT 8 -#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK (0xf << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT) -#define MISC_CGPLL_CONFIG6 0x1c -#define CG1PLL_LF_MODE_SHIFT 9 -#define CG1PLL_LF_MODE_MASK (0x1ff << CG1PLL_LF_MODE_SHIFT) -#define MISC_CLK_CNTL1 0x40 -#define CG1PLL_FBDIV_TEST BIT(26) +#define GPP_CLK_CNTRL 0x00 +#define GPP_CLK2_REQ_MAP_SHIFT 8 +#define GPP_CLK2_REQ_MAP_MASK (0xf << GPP_CLK2_REQ_MAP_SHIFT) +#define GPP_CLK2_REQ_MAP_CLK_REQ2 3 +#define GPP_CLK0_REQ_MAP_SHIFT 0 +#define GPP_CLK0_REQ_MAP_MASK (0xf << GPP_CLK0_REQ_MAP_SHIFT) +#define GPP_CLK0_REQ_MAP_CLK_REQ0 1 +#define MISC_CGPLL_CONFIG1 0x08 +#define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0) +#define MISC_CGPLL_CONFIG3 0x10 +#define CG1PLL_REFDIV_SHIFT 0 +#define CG1PLL_REFDIV_MASK (0x3ff << CG1PLL_REFDIV_SHIFT) +#define CG1PLL_FBDIV_SHIFT 10 +#define CG1PLL_FBDIV_MASK (0xfff << CG1PLL_FBDIV_SHIFT) +#define MISC_CGPLL_CONFIG4 0x14 +#define SS_STEP_SIZE_DSFRAC_SHIFT 0 +#define SS_STEP_SIZE_DSFRAC_MASK (0xffff << SS_STEP_SIZE_DSFRAC_SHIFT) +#define SS_AMOUNT_DSFRAC_SHIFT 16 +#define SS_AMOUNT_DSFRAC_MASK (0xffff << SS_AMOUNT_DSFRAC_SHIFT) +#define MISC_CGPLL_CONFIG5 0x18 +#define SS_AMOUNT_NFRAC_SLIP_SHIFT 8 +#define SS_AMOUNT_NFRAC_SLIP_MASK (0xf << SS_AMOUNT_NFRAC_SLIP_SHIFT) +#define MISC_CGPLL_CONFIG6 0x1c +#define CG1PLL_LF_MODE_SHIFT 9 +#define CG1PLL_LF_MODE_MASK (0x1ff << CG1PLL_LF_MODE_SHIFT) +#define MISC_CLK_CNTL1 0x40 +#define CG1PLL_FBDIV_TEST BIT(26) /* XHCI_PM Registers: 0xfed81c00 */ #define XHCI_PM_INDIRECT_INDEX 0x48 diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 7f0318a..b7ddd57 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -589,15 +589,16 @@ misc_write32(MISC_CGPLL_CONFIG3, cfg3); uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5); - cfg5 &= ~CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK; - cfg5 |= (0x2 << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT) & CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK; + cfg5 &= ~SS_AMOUNT_NFRAC_SLIP_MASK; + cfg5 |= (0x2 << SS_AMOUNT_NFRAC_SLIP_SHIFT) & SS_AMOUNT_NFRAC_SLIP_MASK; misc_write32(MISC_CGPLL_CONFIG5, cfg5); uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4); - cfg4 &= ~CG1PLL_SS_AMOUNT_DSFRAC_MASK; - cfg4 |= (0xd000 << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT) & CG1PLL_SS_AMOUNT_DSFRAC_MASK; - cfg4 &= ~CG1PLL_SS_STEP_SIZE_DSFRAC_MASK; - cfg4 |= (0x02d5 << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT) & CG1PLL_SS_STEP_SIZE_DSFRAC_MASK; + cfg4 &= ~SS_AMOUNT_DSFRAC_MASK; + cfg4 |= (0xd000 << SS_AMOUNT_DSFRAC_SHIFT) & SS_AMOUNT_DSFRAC_MASK; + cfg4 &= ~SS_STEP_SIZE_DSFRAC_MASK; + cfg4 |= (0x02d5 << SS_STEP_SIZE_DSFRAC_SHIFT) + & SS_STEP_SIZE_DSFRAC_MASK; misc_write32(MISC_CGPLL_CONFIG4, cfg4); rstcfg |= TOGGLE_ALL_PWR_GOOD; -- To view, visit https://review.coreboot.org/29015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I71cf1ff6bd4bca7a25484b4da9388c17cfecc043 Gerrit-Change-Number: 29015 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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coreboot-gerrit October 2018