Roy Mingi Park has uploaded this change for review. ( https://review.coreboot.org/29007
Change subject: mb/google/poppy/variants/nocturne: Disable pull-down of GPP_E9/E10
......................................................................
mb/google/poppy/variants/nocturne: Disable pull-down of GPP_E9/E10
While these pins were set to a pull-down 20KOhm, NPCX EC consumes
~2.1mW higher power. Becasue there was leakage current on both GPIO67
and GPIO70 from NPCX EC. With the external pull-up 10KOhm for
USB_OC0#/USB2_OC1#, this wasn't enough to prevent leakage current.
Change-Id: I685d876461c263f07ca4c8f8046635cb7087279c
Signed-off-by: Roy Mingi Park <roy.mingi.park(a)intel.com>
---
M src/mainboard/google/poppy/variants/nocturne/gpio.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/29007/1
diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c
index 8f87705..16ff982 100644
--- a/src/mainboard/google/poppy/variants/nocturne/gpio.c
+++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c
@@ -229,9 +229,9 @@
/* E8 : SATALED# ==> NC */
PAD_CFG_NC(GPP_E8),
/* E9 : USB2_OCO# ==> USB_C0_OC_ODL */
- PAD_CFG_NF(GPP_E9, 20K_PD, DEEP, NF1),
+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
/* E10 : USB2_OC1# ==> USB_C1_OC_ODL */
- PAD_CFG_NF(GPP_E10, 20K_PD, DEEP, NF1),
+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
/* E11 : USB2_OC2# ==> TOUCHSCREEN_RESET_L */
PAD_CFG_TERM_GPO(GPP_E11, 0, 20K_PD, DEEP),
/* E12 : USB2_OC3# ==> NC */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I685d876461c263f07ca4c8f8046635cb7087279c
Gerrit-Change-Number: 29007
Gerrit-PatchSet: 1
Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com>
Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/29005
Change subject: soc/intel/cannonlake: Set PCIEXPWAK_DIS if WAKE# pin is not enabled
......................................................................
soc/intel/cannonlake: Set PCIEXPWAK_DIS if WAKE# pin is not enabled
This change sets PCIEXPWAK_DIS in PM1_EN register if WAKE# pin is not
enabled on the platform. This is required to prevent unnecessary wakes
if the WAKE# pin remains not connected on the platform. Function to
set PCIEXPWAK_DIS gets called in normal boot path (BS_PAYLOAD_LOAD) as
well as S3 resume path (BS_OS_RESUME).
Change-Id: I4ab3bbba1da79dbf1790c99c611195cffbda1511
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/soc/intel/cannonlake/pmc.c
1 file changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/29005/1
diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c
index ecd47e0..02b91cd 100644
--- a/src/soc/intel/cannonlake/pmc.c
+++ b/src/soc/intel/cannonlake/pmc.c
@@ -160,3 +160,28 @@
* allocate resources.
*/
BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_EXIT, pmc_init, NULL);
+
+/*
+ * Check if WAKE# pin is enabled based on DSX_EN_WAKE_PIN setting in
+ * deep_sx_config. If WAKE# pin is not enabled, then PCI Express Wake Disable
+ * bit needs to be set in PM1_EN to avoid unnecessary wakes caused by WAKE#
+ * pin.
+ */
+static void pm1_handle_wake_pin(void *unused)
+{
+ struct device *dev = SA_DEV_ROOT;
+
+ if (!dev || !dev->chip_info)
+ return;
+
+ const config_t *conf = dev->chip_info;
+
+ /* If WAKE# pin is enabled, bail out early. */
+ if (conf->deep_sx_config & DSX_EN_WAKE_PIN)
+ return;
+
+ pmc_update_pm1_enable(PCIEXPWAK_DIS);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_handle_wake_pin, NULL);
+BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_EXIT, pm1_handle_wake_pin, NULL);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4ab3bbba1da79dbf1790c99c611195cffbda1511
Gerrit-Change-Number: 29005
Gerrit-PatchSet: 1
Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>