Hello Chris Wang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/29179
to look at the new patch set (#2).
Change subject: mb/google/kahlee/variants/liara: enable 2T mode for liara.
......................................................................
mb/google/kahlee/variants/liara: enable 2T mode for liara.
To enable 2T mode will help the liara auto restart issue.
So reverting the CL:1243666(Disable NbP-state on Liara)
and using 2T mode instead
BUG=b:116082728
TEST=verify the 2T mode is enabled/boot info ChromOS and no auto
restart/run memtester passed 10 cycle.
Change-Id: I3a96276d88ffb70530d72b15c07b59a01cc6209a
Signed-off-by: chris wang <chris.wang(a)amd.corp-partner.google.com>
---
M src/mainboard/google/kahlee/OemCustomize.c
M src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
2 files changed, 5 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/29179/2
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I3a96276d88ffb70530d72b15c07b59a01cc6209a
Gerrit-Change-Number: 29179
Gerrit-PatchSet: 2
Gerrit-Owner: chris wang <Chris.Wang(a)amd.com>
Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com>
Hello Chris Wang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/29179
to review the following change.
Change subject: mb/google/kahlee/variants/liara: enable 2T mode for liara.
......................................................................
mb/google/kahlee/variants/liara: enable 2T mode for liara.
To enable 2T mode will help the liara auto restart issue.
So reverting the CL:28726(Disable NbP-state on Liara) and using 2T mode
instead
BUG=b:116082728
TEST=verify the 2T mode is enabled/boot info ChromOS and no auto
restart/run memtester passed 10 cycle.
Change-Id: I3a96276d88ffb70530d72b15c07b59a01cc6209a
Signed-off-by: chris wang <chris.wang(a)amd.corp-partner.google.com>
---
M src/mainboard/google/kahlee/OemCustomize.c
M src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
2 files changed, 5 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/29179/1
diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c
index d78f784..f6454df 100644
--- a/src/mainboard/google/kahlee/OemCustomize.c
+++ b/src/mainboard/google/kahlee/OemCustomize.c
@@ -32,6 +32,11 @@
ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL,
0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
+#if IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA)
+ TBLDRV_CONFIG_TO_OVERRIDE(DIMMS_PER_CHANNEL, ANY_SPEED, VOLT_ANY_,
+ ANY_),
+ TBLDRV_CONFIG_ENTRY_SLOWACCMODE(1),
+#endif
PSO_END
};
diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
index e9cf5c8..42d9a49 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
+++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c
@@ -152,7 +152,4 @@
InitEarly->GnbConfig.PsppPolicy = PsppBalanceLow;
InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus;
InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth;
- if ((IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA)) && (board_id() <= 4))
- InitEarly->PlatformConfig.PlatformProfile.NbPstatesSupported =
- FALSE;
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I3a96276d88ffb70530d72b15c07b59a01cc6209a
Gerrit-Change-Number: 29179
Gerrit-PatchSet: 1
Gerrit-Owner: chris wang <Chris.Wang(a)amd.com>
Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com>
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/29169
to look at the new patch set (#3).
Change subject: intel: Use CF9 reset (part 2)
......................................................................
intel: Use CF9 reset (part 2)
Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also
implement board_reset() as a "full reset" (aka. cold reset) as that
is what was used here for hard_reset().
Drop soc_reset_prepare() thereby, as it was only used for APL. Also,
move the global-reset logic.
We leave some comments to remind us that a system_reset() should
be enough, where a full_reset() is called now (to retain current
behaviour) and looks suspicious.
Note, as no global_reset() is implemented for Denverton-NS, we halt
there now instead of issuing a non-global reset. This seems safer;
a non-global reset might result in a reset loop.
Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/drivers/intel/fsp1_1/raminit.c
M src/drivers/intel/fsp1_1/romstage.c
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/intel/fsp2_0/util.c
D src/include/cpu/intel/reset.h
M src/include/reset.h
M src/lib/reset.c
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/apollolake/reset.c
M src/soc/intel/apollolake/romstage.c
M src/soc/intel/braswell/Kconfig
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/reset.c
M src/soc/intel/common/Kconfig
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/common/reset.c
A src/soc/intel/common/reset.h
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/denverton_ns/reset.c
M src/soc/intel/denverton_ns/romstage.c
M src/soc/intel/quark/Kconfig
M src/soc/intel/quark/reset.c
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/reset.c
24 files changed, 83 insertions(+), 108 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29169/3
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53
Gerrit-Change-Number: 29169
Gerrit-PatchSet: 3
Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/29177
to look at the new patch set (#4).
Change subject: src: Move shared amd64 and IA32 MSRs to <cpu/x86/msr.h>
......................................................................
src: Move shared amd64 and IA32 MSRs to <cpu/x86/msr.h>
Change-Id: Ic9022a98878a2fcc85868a64aa9c2ca3eb2e2c4e
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
D src/include/cpu/amd/amdfam15.h
M src/include/cpu/x86/msr.h
M src/soc/amd/stoneyridge/bootblock/bootblock.c
M src/soc/amd/stoneyridge/mca.c
M src/soc/amd/stoneyridge/northbridge.c
5 files changed, 172 insertions(+), 192 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/29177/4
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ic9022a98878a2fcc85868a64aa9c2ca3eb2e2c4e
Gerrit-Change-Number: 29177
Gerrit-PatchSet: 4
Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/29177
to look at the new patch set (#3).
Change subject: src: Move shared amd64 and IA32 MSRs to <cpu/x86/msr.h>
......................................................................
src: Move shared amd64 and IA32 MSRs to <cpu/x86/msr.h>
Change-Id: Ic9022a98878a2fcc85868a64aa9c2ca3eb2e2c4e
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
D src/include/cpu/amd/amdfam15.h
M src/include/cpu/x86/msr.h
M src/soc/amd/stoneyridge/bootblock/bootblock.c
M src/soc/amd/stoneyridge/mca.c
M src/soc/amd/stoneyridge/northbridge.c
5 files changed, 173 insertions(+), 192 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/29177/3
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ic9022a98878a2fcc85868a64aa9c2ca3eb2e2c4e
Gerrit-Change-Number: 29177
Gerrit-PatchSet: 3
Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Elyes HAOUAS has uploaded a new patch set (#2). ( https://review.coreboot.org/29177 )
Change subject: src: Move shared amd64 and IA32 MSRs to <cpu/x86/msr.h>
......................................................................
src: Move shared amd64 and IA32 MSRs to <cpu/x86/msr.h>
Change-Id: Ic9022a98878a2fcc85868a64aa9c2ca3eb2e2c4e
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
D src/include/cpu/amd/amdfam15.h
M src/include/cpu/x86/msr.h
M src/soc/amd/stoneyridge/bootblock/bootblock.c
M src/soc/amd/stoneyridge/mca.c
M src/soc/amd/stoneyridge/northbridge.c
5 files changed, 171 insertions(+), 192 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/29177/2
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ic9022a98878a2fcc85868a64aa9c2ca3eb2e2c4e
Gerrit-Change-Number: 29177
Gerrit-PatchSet: 2
Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>