coreboot-gerrit October 2018

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Change in coreboot[master]: util/inteltool: Fix LynxPoint (non-LP) GPIO register map
by Nico Huber (Code Review) 18 Oct '18

18 Oct '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/29167 ) Change subject: util/inteltool: Fix LynxPoint (non-LP) GPIO register map ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29167/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29167/2//COMMIT_MSG@11 PS2, Line 11: Intel 9 Series > According to what I can see on ark.intel. […] IIRC, those were rebranded Lynx Point chips. A real 9 series (non-lp) was never released, AFAIK. To be clear, LP stands for low power wrt. to Intels PCHs. And that means they are sold with the CPU on a single interposer for ultrabooks, usually called -U or -Y (e.g. Haswell-U, Broadwell-U etc.). OTOH, H97 and Z97 are discrete desktop chips. -- To view, visit https://review.coreboot.org/29167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I394a198bbb6628915cb73cabc5c8ff808579a07f Gerrit-Change-Number: 29167 Gerrit-PatchSet: 2 Gerrit-Owner: Roland Fehér <feherneoh(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Roland Fehér <feherneoh(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 17 Oct 2018 17:31:39 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: util/inteltool: Fix LynxPoint (non-LP) GPIO register map
by Roland Fehér (Code Review) 18 Oct '18

18 Oct '18

Hello build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29167 to look at the new patch set (#3). Change subject: util/inteltool: Fix LynxPoint (non-LP) GPIO register map ...................................................................... util/inteltool: Fix LynxPoint (non-LP) GPIO register map The GPIO register dumper code for the LynxPoint family PCH chips (Intel 8 Series and C220 Series) was incorrectly using a shortened version of the LynxPoint-LP (Intel 9 Series) GPIO register map. Switched to the correct register map for the affected chipsets. Change-Id: I394a198bbb6628915cb73cabc5c8ff808579a07f Signed-off-by: Fehér Roland Ádám <feherneoh(a)gmail.com> --- M util/inteltool/gpio.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29167/3 -- To view, visit https://review.coreboot.org/29167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I394a198bbb6628915cb73cabc5c8ff808579a07f Gerrit-Change-Number: 29167 Gerrit-PatchSet: 3 Gerrit-Owner: Roland Fehér <feherneoh(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Roland Fehér <feherneoh(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: util/inteltool: Fix LynxPoint (non-LP) GPIO register map
by Roland Fehér (Code Review) 18 Oct '18

18 Oct '18

Roland Fehér has posted comments on this change. ( https://review.coreboot.org/29167 ) Change subject: util/inteltool: Fix LynxPoint (non-LP) GPIO register map ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/29167/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29167/2//COMMIT_MSG@11 PS2, Line 11: Intel 9 Series > It's 8 series too. I think Intel refers to it as "4th […] According to what I can see on ark.intel.com the LynxPoint-LP chipsets are supposed to me H97 and Z97, and those are 9 Series chips -- To view, visit https://review.coreboot.org/29167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I394a198bbb6628915cb73cabc5c8ff808579a07f Gerrit-Change-Number: 29167 Gerrit-PatchSet: 2 Gerrit-Owner: Roland Fehér <feherneoh(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Roland Fehér <feherneoh(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 17 Oct 2018 17:22:29 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: util/inteltool: Fix LynxPoint (non-LP) GPIO register map
by Nico Huber (Code Review) 18 Oct '18

18 Oct '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/29167 ) Change subject: util/inteltool: Fix LynxPoint (non-LP) GPIO register map ...................................................................... Patch Set 2: Code-Review+2 (2 comments) https://review.coreboot.org/#/c/29167/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29167/2//COMMIT_MSG@10 PS2, Line 10: incorreclty incorrec*tl*y https://review.coreboot.org/#/c/29167/2//COMMIT_MSG@11 PS2, Line 11: Intel 9 Series It's 8 series too. I think Intel refers to it as "4th generation core i/o", though, as they like to pretend that it's integrated into the CPU. -- To view, visit https://review.coreboot.org/29167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I394a198bbb6628915cb73cabc5c8ff808579a07f Gerrit-Change-Number: 29167 Gerrit-PatchSet: 2 Gerrit-Owner: Roland Fehér <feherneoh(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 17 Oct 2018 17:16:34 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/inteltool: Fix LynxPoint (non-LP) GPIO register map
by Roland Fehér (Code Review) 18 Oct '18

18 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29167 to look at the new patch set (#2). Change subject: util/inteltool: Fix LynxPoint (non-LP) GPIO register map ...................................................................... util/inteltool: Fix LynxPoint (non-LP) GPIO register map The GPIO register dumper code for the LynxPoint family PCH chips (Intel 8 Series and C220 Series) was incorreclty using a shortened version of the LynxPoint-LP (Intel 9 Series) GPIO register map. Switched to the correct register map for the affected chipsets. Change-Id: I394a198bbb6628915cb73cabc5c8ff808579a07f Signed-off-by: Fehér Roland Ádám <feherneoh(a)gmail.com> --- M util/inteltool/gpio.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29167/2 -- To view, visit https://review.coreboot.org/29167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I394a198bbb6628915cb73cabc5c8ff808579a07f Gerrit-Change-Number: 29167 Gerrit-PatchSet: 2 Gerrit-Owner: Roland Fehér <feherneoh(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/amd/stoneyridge: Remove double definition for wideio
by Richard Spiegel (Code Review) 18 Oct '18

18 Oct '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29168 Change subject: soc/amd/stoneyridge: Remove double definition for wideio ...................................................................... soc/amd/stoneyridge: Remove double definition for wideio WIDEIO_RANGE_ERROR and TOTAL_WIDEIO_PORTS are defined twice. Remove the definitions within MMIO definitions, as wideio is not related to MMIO. BUG=b:117814228 TEST=Build grunt. Change-Id: I370a5b387b908fe7a840eb7579d45c1a6a9ca615 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/29168/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index b9dc62a..9f940c0 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -158,9 +158,6 @@ #define DEBUG_PORT_ENABLE BIT(18) #define DEBUG_PORT_MASK (BIT(16) | BIT(17) | BIT(18)) -#define WIDEIO_RANGE_ERROR -1 -#define TOTAL_WIDEIO_PORTS 3 - /* FCH AOAC Registers 0xfed81e00 */ #define FCH_AOAC_D3_CONTROL_CLK_GEN 0x40 #define FCH_AOAC_D3_CONTROL_I2C0 0x4a -- To view, visit https://review.coreboot.org/29168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I370a5b387b908fe7a840eb7579d45c1a6a9ca615 Gerrit-Change-Number: 29168 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: util/inteltool: Fix LynxPoint (non-LP) GPIO register map
by Roland Fehér (Code Review) 18 Oct '18

18 Oct '18

Roland Fehér has uploaded this change for review. ( https://review.coreboot.org/29167 Change subject: util/inteltool: Fix LynxPoint (non-LP) GPIO register map ...................................................................... util/inteltool: Fix LynxPoint (non-LP) GPIO register map The GPIO register dumper code for the LynxPoint family PCH chips (Intel 8 Series and C220 Series) was incorreclty using a shortened version of the LynxPoint-LP (Intel 9 Series) GPIO register map. Added the correct register map for the affected chipsets. Change-Id: I394a198bbb6628915cb73cabc5c8ff808579a07f Signed-off-by: Fehér Roland Ádám <feherneoh(a)gmail.com> --- M util/inteltool/gpio.c 1 file changed, 38 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29167/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index c38051c..38ce8fa 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -344,6 +344,42 @@ }; +static const io_register_t lynxpoint_gpio_registers[] = { + { 0x00, 4, "GPIO_USE_SEL" }, // GPIO Use Select + { 0x04, 4, "GP_IO_SEL" }, // GPIO Input/Output Select + { 0x08, 4, "RESERVED" }, // Reserved + { 0x0C, 4, "GP_LVL" }, // GPIO Level for Input or Output + { 0x10, 4, "RESERVED" }, // Reserved + { 0x14, 4, "RESERVED" }, // Reserved + { 0x18, 4, "GPO_BLINK" }, // GPIO Blink Enable + { 0x1C, 4, "GP_SER_BLINK" }, // GP Serial Blink + { 0x20, 4, "GP_SB_CMDSTS" }, // GP Serial Blink Command Status + { 0x24, 4, "GP_SB_DATA" }, // GP Serial Blink Data + { 0x28, 2, "GPI_NMI_EN" }, // GPI NMI Enable + { 0x2A, 2, "GPI_NMI_STS" }, // GPI NMI Status + { 0x2C, 4, "GPI_INV" }, // GPIO Signal Invert + { 0x30, 4, "GPIO_USE_SEL2" }, // GPIO Use Select 2 + { 0x34, 4, "GP_IO_SEL2" }, // GPIO Input/Output Select 2 + { 0x38, 4, "GP_LVL2" }, // GPIO Level for Input or Output 2 + { 0x3C, 4, "RESERVED" }, // Reserved + { 0x40, 4, "GPIO_USE_SEL3" }, // GPIO Use Select 3 + { 0x44, 4, "GP_IO_SEL3" }, // GPIO Input/Output Select 3 + { 0x48, 4, "GP_LVL3" }, // GPIO Level for Input or Output 3 + { 0x4C, 4, "RESERVED" }, // Reserved + { 0x50, 4, "RESERVED" }, // Reserved + { 0x54, 4, "RESERVED" }, // Reserved + { 0x58, 4, "RESERVED" }, // Reserved + { 0x5C, 4, "RESERVED" }, // Reserved + { 0x60, 4, "GP_RST_SEL1" }, // GPIO Reset Select 1 + { 0x64, 4, "GP_RST_SEL2" }, // GPIO Reset Select 2 + { 0x68, 4, "GP_RST_SEL3" }, // GPIO Reset Select 3 + { 0x6C, 4, "RESERVED" }, // Reserved + { 0x70, 4, "RESERVED" }, // Reserved + { 0x74, 4, "RESERVED" }, // Reserved + { 0x78, 4, "RESERVED" }, // Reserved + { 0x7C, 4, "RESERVED" }, // Reserved +}; + /* Default values for Cougar Point desktop chipsets */ static const gpio_default_t cp_pch_desktop_defaults[] = { { 0x00, 0xb96ba1ff }, @@ -869,9 +905,8 @@ case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_H81: gpiobase = pci_read_word(sb, 0x48) & 0xfffc; - gpio_registers = lynxpoint_lp_gpio_registers; - /* Shares register locations but has less of them */ - size = 29; + gpio_registers = lynxpoint_gpio_registers; + size = ARRAY_SIZE(lynxpoint_gpio_registers); break; case PCI_DEVICE_ID_INTEL_3400: case PCI_DEVICE_ID_INTEL_3420: -- To view, visit https://review.coreboot.org/29167 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I394a198bbb6628915cb73cabc5c8ff808579a07f Gerrit-Change-Number: 29167 Gerrit-PatchSet: 1 Gerrit-Owner: Roland Fehér <feherneoh(a)gmail.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Remove DEV_D18F4 definition
by Richard Spiegel (Code Review) 18 Oct '18

18 Oct '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29166 Change subject: soc/amd/stoneyridge: Remove DEV_D18F4 definition ...................................................................... soc/amd/stoneyridge: Remove DEV_D18F4 definition The definition DEV_D18F4 is only used once, in file tsc_freq.c, and is the same as SOC_PM_DEV. Remove the definition, and replace its use in tsc_freq.c with SOC_PM_DEV. BUG=b:117754424 TEST=Build and boot grunt. Change-Id: I9eeeaa084e5b16280713b8b833b4faa78d277586 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/include/soc/pci_devs.h M src/soc/amd/stoneyridge/tsc_freq.c 2 files changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/29166/1 diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index 865cf71..5fddc52 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -145,12 +145,6 @@ #define PM_DEVID 0x15b4 #define PM_DEVFN PCI_DEVFN(PM_DEV, PM_FUNC) #define SOC_PM_DEV _SOC_DEV(PM_DEV, PM_FUNC) -#if !defined(__SIMPLE_DEVICE__) - #include <device/device.h> - #define DEV_D18F4 dev_find_slot(0, PM_DEVFN) -#else - #define DEV_D18F4 PCI_DEV(0, PM_DEV, PM_FUNC) -#endif /* Northbridge Configuration */ #define NB_DEV 0x18 diff --git a/src/soc/amd/stoneyridge/tsc_freq.c b/src/soc/amd/stoneyridge/tsc_freq.c index 8c18884..a8ed7c6 100644 --- a/src/soc/amd/stoneyridge/tsc_freq.c +++ b/src/soc/amd/stoneyridge/tsc_freq.c @@ -36,7 +36,7 @@ * to the "Software P-state Numbering" section, P0 is the highest * non-boosted state. freq = 100MHz * (CpuFid + 10h) / (2^(CpuDid)). */ - boost_states = (pci_read_config32(DEV_D18F4, CORE_PERF_BOOST_CTRL) + boost_states = (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL) >> 2) & 0x7; msr = rdmsr(PSTATE_0_MSR + boost_states); -- To view, visit https://review.coreboot.org/29166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9eeeaa084e5b16280713b8b833b4faa78d277586 Gerrit-Change-Number: 29166 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: soc/lowrisc: Remove the remains of a LowRISC soc
by Peter Lemenkov (Code Review) 17 Oct '18

17 Oct '18

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/29165 Change subject: soc/lowrisc: Remove the remains of a LowRISC soc ...................................................................... soc/lowrisc: Remove the remains of a LowRISC soc Looks like we've got a race condition between commit ce8763fb (Change-Id I4e3e715106a1a94381a563dc4a56781c35883c2d) and commit 2e38dbe5 (Change-Id I5524732f6eb3841e43afd176644119b03b5e5e27). Let's fix it. Change-Id: I03c5860b27d04b6e1d7868ba8ea7b52d1075aa6a Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- D src/soc/lowrisc/lowrisc/mtime.c 1 file changed, 0 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/29165/1 diff --git a/src/soc/lowrisc/lowrisc/mtime.c b/src/soc/lowrisc/lowrisc/mtime.c deleted file mode 100644 index f8c2717..0000000 --- a/src/soc/lowrisc/lowrisc/mtime.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 HardenedLinux - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <mcall.h> - -/* FIXME: This is an empty implementation, please improve */ -/* This function is used to initialize HLS()->time/HLS()->timecmp */ -void mtime_init(void) -{ -} -- To view, visit https://review.coreboot.org/29165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I03c5860b27d04b6e1d7868ba8ea7b52d1075aa6a Gerrit-Change-Number: 29165 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com>

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Change in coreboot[master]: soc/intel/icelake: Initial SoC commit
by build bot (Jenkins) (Code Review) 17 Oct '18

17 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29162 ) Change subject: soc/intel/icelake: Initial SoC commit ...................................................................... Patch Set 2: (9 comments) https://review.coreboot.org/#/c/29162/2/src/soc/intel/icelake/acpi.c File src/soc/intel/icelake/acpi.c: https://review.coreboot.org/#/c/29162/2/src/soc/intel/icelake/acpi.c@208 PS2, Line 208: if (IS_ENABLED(CONFIG_CONSOLE_CBMEM)) suspect code indent for conditional statements (8, 8) https://review.coreboot.org/#/c/29162/2/src/soc/intel/icelake/bootblock/pch… File src/soc/intel/icelake/bootblock/pch.c: https://review.coreboot.org/#/c/29162/2/src/soc/intel/icelake/bootblock/pch… PS2, Line 53: #define TCOEN (1 << 1) /* Enable TCO I/O range decode. */ line over 80 characters https://review.coreboot.org/#/c/29162/2/src/soc/intel/icelake/bootblock/pch… PS2, Line 124: if (pmc_reg_value != 0xFFFFFFFF) that open brace { should be on the previous line https://review.coreboot.org/#/c/29162/2/src/soc/intel/icelake/bootblock/rep… File src/soc/intel/icelake/bootblock/report_platform.c: https://review.coreboot.org/#/c/29162/2/src/soc/intel/icelake/bootblock/rep… PS2, Line 104: int j=0; spaces required around that '=' (ctx:VxV) https://review.coreboot.org/#/c/29162/2/src/soc/intel/icelake/bootblock/rep… PS2, Line 113: p[12]=0; spaces required around that '=' (ctx:VxV) https://review.coreboot.org/#/c/29162/2/src/soc/intel/icelake/cbmem.c File src/soc/intel/icelake/cbmem.c: https://review.coreboot.org/#/c/29162/2/src/soc/intel/icelake/cbmem.c@20 PS2, Line 20: /* not implemented yet */ code indent should use tabs where possible https://review.coreboot.org/#/c/29162/2/src/soc/intel/icelake/include/soc/r… File src/soc/intel/icelake/include/soc/romstage.h: https://review.coreboot.org/#/c/29162/2/src/soc/intel/icelake/include/soc/r… PS2, Line 22: void mainboard_memory_init_params(FSPM_UPD *mupd); need consistent spacing around '*' (ctx:WxV) https://review.coreboot.org/#/c/29162/2/src/soc/intel/icelake/sd.c File src/soc/intel/icelake/sd.c: https://review.coreboot.org/#/c/29162/2/src/soc/intel/icelake/sd.c@19 PS2, Line 19: int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, struct device *dev) "foo* bar" should be "foo *bar" https://review.coreboot.org/#/c/29162/2/src/soc/intel/icelake/smihandler.c File src/soc/intel/icelake/smihandler.c: https://review.coreboot.org/#/c/29162/2/src/soc/intel/icelake/smihandler.c@… PS2, Line 83: return ; space prohibited before semicolon -- To view, visit https://review.coreboot.org/29162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I756fa7275c4190aebc0695f14484498aaf5662a5 Gerrit-Change-Number: 29162 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 17 Oct 2018 13:23:05 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit October 2018