coreboot-gerrit October 2018

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Change in coreboot[master]: mb/*/*: Clean up FADT checksum assignment
by Patrick Georgi (Code Review) 17 Oct '18

17 Oct '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28988 ) Change subject: mb/*/*: Clean up FADT checksum assignment ...................................................................... mb/*/*: Clean up FADT checksum assignment The assignment of header->checksum was in some cases done twice, or unnecessarily split into two lines. Change-Id: Ib0c0890d7589e6a24b11e9bda10e6969c7d73c56 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-on: https://review.coreboot.org/28988 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marc Jones <marc(a)marcjonesconsulting.com> --- M src/mainboard/adi/rcc-dff/fadt.c M src/mainboard/aopen/dxplplusu/fadt.c M src/mainboard/emulation/qemu-q35/acpi_tables.c M src/mainboard/esd/atom15/fadt.c M src/mainboard/facebook/watson/fadt.c M src/mainboard/google/auron/fadt.c M src/mainboard/google/beltino/fadt.c M src/mainboard/google/cyan/fadt.c M src/mainboard/google/jecht/fadt.c M src/mainboard/google/rambi/fadt.c M src/mainboard/google/slippy/fadt.c M src/mainboard/intel/baskingridge/fadt.c M src/mainboard/intel/bayleybay_fsp/fadt.c M src/mainboard/intel/camelbackmountain_fsp/fadt.c M src/mainboard/intel/littleplains/fadt.c M src/mainboard/intel/minnowmax/fadt.c M src/mainboard/intel/mohonpeak/fadt.c M src/mainboard/intel/strago/fadt.c M src/mainboard/intel/wtm2/fadt.c M src/mainboard/lenovo/t400/fadt.c M src/mainboard/lenovo/x200/fadt.c M src/mainboard/ocp/monolake/fadt.c M src/mainboard/ocp/wedge100s/fadt.c M src/mainboard/opencellular/rotundu/fadt.c M src/mainboard/roda/rk9/fadt.c M src/mainboard/siemens/mc_bdx1/fadt.c M src/mainboard/siemens/mc_tcu3/fadt.c 27 files changed, 26 insertions(+), 70 deletions(-) Approvals: build bot (Jenkins): Verified Marc Jones: Looks good to me, approved diff --git a/src/mainboard/adi/rcc-dff/fadt.c b/src/mainboard/adi/rcc-dff/fadt.c index 83adf85..cc88e58 100644 --- a/src/mainboard/adi/rcc-dff/fadt.c +++ b/src/mainboard/adi/rcc-dff/fadt.c @@ -30,9 +30,7 @@ #if PLATFORM_HAS_FADT_CUSTOMIZATIONS - header->checksum = 0; - header->checksum = - acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); + header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); #endif } diff --git a/src/mainboard/aopen/dxplplusu/fadt.c b/src/mainboard/aopen/dxplplusu/fadt.c index 9e44b85..b78a3ed 100644 --- a/src/mainboard/aopen/dxplplusu/fadt.c +++ b/src/mainboard/aopen/dxplplusu/fadt.c @@ -157,6 +157,5 @@ fadt->x_gpe1_blk.addrl = 0x0; fadt->x_gpe1_blk.addrh = 0x0; - header->checksum = - acpi_checksum((void *) fadt, header->length); + header->checksum = acpi_checksum((void *) fadt, header->length); } diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c index 83d25d7..5a36cb1 100644 --- a/src/mainboard/emulation/qemu-q35/acpi_tables.c +++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c @@ -170,8 +170,7 @@ fadt->x_gpe1_blk.addrl = 0x0; fadt->x_gpe1_blk.addrh = 0x0; - header->checksum = - acpi_checksum((void *) fadt, header->length); + header->checksum = acpi_checksum((void *) fadt, header->length); } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/esd/atom15/fadt.c b/src/mainboard/esd/atom15/fadt.c index 36e4655..49e0d30 100644 --- a/src/mainboard/esd/atom15/fadt.c +++ b/src/mainboard/esd/atom15/fadt.c @@ -25,8 +25,5 @@ /* Platform specific customizations go here */ - header->checksum = 0; - header->checksum = - acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); - + header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); } diff --git a/src/mainboard/facebook/watson/fadt.c b/src/mainboard/facebook/watson/fadt.c index a762227..5af6056 100644 --- a/src/mainboard/facebook/watson/fadt.c +++ b/src/mainboard/facebook/watson/fadt.c @@ -23,6 +23,5 @@ /* Platform specific customizations go here */ - header->checksum = 0; header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); } diff --git a/src/mainboard/google/auron/fadt.c b/src/mainboard/google/auron/fadt.c index c96ae68..9ee5c95 100644 --- a/src/mainboard/google/auron/fadt.c +++ b/src/mainboard/google/auron/fadt.c @@ -42,6 +42,5 @@ acpi_fill_in_fadt(fadt); - header->checksum = - acpi_checksum((void *) fadt, header->length); + header->checksum = acpi_checksum((void *) fadt, header->length); } diff --git a/src/mainboard/google/beltino/fadt.c b/src/mainboard/google/beltino/fadt.c index 806902d..5c2cafd 100644 --- a/src/mainboard/google/beltino/fadt.c +++ b/src/mainboard/google/beltino/fadt.c @@ -147,6 +147,5 @@ fadt->x_gpe1_blk.addrl = 0x0; fadt->x_gpe1_blk.addrh = 0x0; - header->checksum = - acpi_checksum((void *) fadt, header->length); + header->checksum = acpi_checksum((void *) fadt, header->length); } diff --git a/src/mainboard/google/cyan/fadt.c b/src/mainboard/google/cyan/fadt.c index 29e2d2a..7455d4b 100644 --- a/src/mainboard/google/cyan/fadt.c +++ b/src/mainboard/google/cyan/fadt.c @@ -42,6 +42,5 @@ acpi_fill_in_fadt(fadt); - header->checksum = - acpi_checksum((void *) fadt, header->length); + header->checksum = acpi_checksum((void *) fadt, header->length); } diff --git a/src/mainboard/google/jecht/fadt.c b/src/mainboard/google/jecht/fadt.c index c96ae68..9ee5c95 100644 --- a/src/mainboard/google/jecht/fadt.c +++ b/src/mainboard/google/jecht/fadt.c @@ -42,6 +42,5 @@ acpi_fill_in_fadt(fadt); - header->checksum = - acpi_checksum((void *) fadt, header->length); + header->checksum = acpi_checksum((void *) fadt, header->length); } diff --git a/src/mainboard/google/rambi/fadt.c b/src/mainboard/google/rambi/fadt.c index 4aa4ec6..d02609b 100644 --- a/src/mainboard/google/rambi/fadt.c +++ b/src/mainboard/google/rambi/fadt.c @@ -41,6 +41,5 @@ acpi_fill_in_fadt(fadt); - header->checksum = - acpi_checksum((void *) fadt, header->length); + header->checksum = acpi_checksum((void *) fadt, header->length); } diff --git a/src/mainboard/google/slippy/fadt.c b/src/mainboard/google/slippy/fadt.c index 8a04591..52a099f 100644 --- a/src/mainboard/google/slippy/fadt.c +++ b/src/mainboard/google/slippy/fadt.c @@ -147,6 +147,5 @@ fadt->x_gpe1_blk.addrl = 0x0; fadt->x_gpe1_blk.addrh = 0x0; - header->checksum = - acpi_checksum((void *) fadt, header->length); + header->checksum = acpi_checksum((void *) fadt, header->length); } diff --git a/src/mainboard/intel/baskingridge/fadt.c b/src/mainboard/intel/baskingridge/fadt.c index e32e9f2..54e95f8 100644 --- a/src/mainboard/intel/baskingridge/fadt.c +++ b/src/mainboard/intel/baskingridge/fadt.c @@ -147,6 +147,5 @@ fadt->x_gpe1_blk.addrl = 0x0; fadt->x_gpe1_blk.addrh = 0x0; - header->checksum = - acpi_checksum((void *) fadt, header->length); + header->checksum = acpi_checksum((void *) fadt, header->length); } diff --git a/src/mainboard/intel/bayleybay_fsp/fadt.c b/src/mainboard/intel/bayleybay_fsp/fadt.c index 8e8de51..8fee54b 100644 --- a/src/mainboard/intel/bayleybay_fsp/fadt.c +++ b/src/mainboard/intel/bayleybay_fsp/fadt.c @@ -25,7 +25,5 @@ /* Platform specific customizations go here */ - header->checksum = 0; - header->checksum = - acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); + header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); } diff --git a/src/mainboard/intel/camelbackmountain_fsp/fadt.c b/src/mainboard/intel/camelbackmountain_fsp/fadt.c index b274531..5af6056 100644 --- a/src/mainboard/intel/camelbackmountain_fsp/fadt.c +++ b/src/mainboard/intel/camelbackmountain_fsp/fadt.c @@ -23,7 +23,5 @@ /* Platform specific customizations go here */ - header->checksum = 0; - header->checksum = - acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); + header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); } diff --git a/src/mainboard/intel/littleplains/fadt.c b/src/mainboard/intel/littleplains/fadt.c index 83adf85..3d8db00 100644 --- a/src/mainboard/intel/littleplains/fadt.c +++ b/src/mainboard/intel/littleplains/fadt.c @@ -30,9 +30,6 @@ #if PLATFORM_HAS_FADT_CUSTOMIZATIONS - header->checksum = 0; - header->checksum = - acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); + header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); #endif - } diff --git a/src/mainboard/intel/minnowmax/fadt.c b/src/mainboard/intel/minnowmax/fadt.c index cd8eefd..4194bfc 100644 --- a/src/mainboard/intel/minnowmax/fadt.c +++ b/src/mainboard/intel/minnowmax/fadt.c @@ -25,8 +25,5 @@ /* Platform specific customizations go here */ - header->checksum = 0; - header->checksum = - acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); - + header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); } diff --git a/src/mainboard/intel/mohonpeak/fadt.c b/src/mainboard/intel/mohonpeak/fadt.c index 83adf85..3d8db00 100644 --- a/src/mainboard/intel/mohonpeak/fadt.c +++ b/src/mainboard/intel/mohonpeak/fadt.c @@ -30,9 +30,6 @@ #if PLATFORM_HAS_FADT_CUSTOMIZATIONS - header->checksum = 0; - header->checksum = - acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); + header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); #endif - } diff --git a/src/mainboard/intel/strago/fadt.c b/src/mainboard/intel/strago/fadt.c index af222b5..e0e7d44 100644 --- a/src/mainboard/intel/strago/fadt.c +++ b/src/mainboard/intel/strago/fadt.c @@ -42,6 +42,5 @@ acpi_fill_in_fadt(fadt); - header->checksum = - acpi_checksum((void *) fadt, header->length); + header->checksum = acpi_checksum((void *) fadt, header->length); } diff --git a/src/mainboard/intel/wtm2/fadt.c b/src/mainboard/intel/wtm2/fadt.c index d474fc4..6f1553c 100644 --- a/src/mainboard/intel/wtm2/fadt.c +++ b/src/mainboard/intel/wtm2/fadt.c @@ -41,6 +41,5 @@ acpi_fill_in_fadt(fadt); - header->checksum = - acpi_checksum((void *) fadt, header->length); + header->checksum = acpi_checksum((void *) fadt, header->length); } diff --git a/src/mainboard/lenovo/t400/fadt.c b/src/mainboard/lenovo/t400/fadt.c index fe988d6..5596115 100644 --- a/src/mainboard/lenovo/t400/fadt.c +++ b/src/mainboard/lenovo/t400/fadt.c @@ -148,6 +148,5 @@ fadt->x_gpe1_blk.addrl = 0x0; fadt->x_gpe1_blk.addrh = 0x0; - header->checksum = - acpi_checksum((void *) fadt, header->length); + header->checksum = acpi_checksum((void *) fadt, header->length); } diff --git a/src/mainboard/lenovo/x200/fadt.c b/src/mainboard/lenovo/x200/fadt.c index fe988d6..5596115 100644 --- a/src/mainboard/lenovo/x200/fadt.c +++ b/src/mainboard/lenovo/x200/fadt.c @@ -148,6 +148,5 @@ fadt->x_gpe1_blk.addrl = 0x0; fadt->x_gpe1_blk.addrh = 0x0; - header->checksum = - acpi_checksum((void *) fadt, header->length); + header->checksum = acpi_checksum((void *) fadt, header->length); } diff --git a/src/mainboard/ocp/monolake/fadt.c b/src/mainboard/ocp/monolake/fadt.c index b274531..5af6056 100644 --- a/src/mainboard/ocp/monolake/fadt.c +++ b/src/mainboard/ocp/monolake/fadt.c @@ -23,7 +23,5 @@ /* Platform specific customizations go here */ - header->checksum = 0; - header->checksum = - acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); + header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); } diff --git a/src/mainboard/ocp/wedge100s/fadt.c b/src/mainboard/ocp/wedge100s/fadt.c index b274531..5af6056 100644 --- a/src/mainboard/ocp/wedge100s/fadt.c +++ b/src/mainboard/ocp/wedge100s/fadt.c @@ -23,7 +23,5 @@ /* Platform specific customizations go here */ - header->checksum = 0; - header->checksum = - acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); + header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); } diff --git a/src/mainboard/opencellular/rotundu/fadt.c b/src/mainboard/opencellular/rotundu/fadt.c index cd8eefd..4194bfc 100644 --- a/src/mainboard/opencellular/rotundu/fadt.c +++ b/src/mainboard/opencellular/rotundu/fadt.c @@ -25,8 +25,5 @@ /* Platform specific customizations go here */ - header->checksum = 0; - header->checksum = - acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); - + header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); } diff --git a/src/mainboard/roda/rk9/fadt.c b/src/mainboard/roda/rk9/fadt.c index fe988d6..5596115 100644 --- a/src/mainboard/roda/rk9/fadt.c +++ b/src/mainboard/roda/rk9/fadt.c @@ -148,6 +148,5 @@ fadt->x_gpe1_blk.addrl = 0x0; fadt->x_gpe1_blk.addrh = 0x0; - header->checksum = - acpi_checksum((void *) fadt, header->length); + header->checksum = acpi_checksum((void *) fadt, header->length); } diff --git a/src/mainboard/siemens/mc_bdx1/fadt.c b/src/mainboard/siemens/mc_bdx1/fadt.c index b274531..5af6056 100644 --- a/src/mainboard/siemens/mc_bdx1/fadt.c +++ b/src/mainboard/siemens/mc_bdx1/fadt.c @@ -23,7 +23,5 @@ /* Platform specific customizations go here */ - header->checksum = 0; - header->checksum = - acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); + header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); } diff --git a/src/mainboard/siemens/mc_tcu3/fadt.c b/src/mainboard/siemens/mc_tcu3/fadt.c index 8e8de51..8fee54b 100644 --- a/src/mainboard/siemens/mc_tcu3/fadt.c +++ b/src/mainboard/siemens/mc_tcu3/fadt.c @@ -25,7 +25,5 @@ /* Platform specific customizations go here */ - header->checksum = 0; - header->checksum = - acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); + header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); } -- To view, visit https://review.coreboot.org/28988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ib0c0890d7589e6a24b11e9bda10e6969c7d73c56 Gerrit-Change-Number: 28988 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: src: Remove unneeded whitespace
by build bot (Jenkins) (Code Review) 17 Oct '18

17 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29161 ) Change subject: src: Remove unneeded whitespace ...................................................................... Patch Set 7: (111 comments) https://review.coreboot.org/#/c/29161/7/src/cpu/amd/family_10h-family_15h/f… File src/cpu/amd/family_10h-family_15h/fidvid.c: https://review.coreboot.org/#/c/29161/7/src/cpu/amd/family_10h-family_15h/f… PS7, Line 499: if (cpuRev & (AMD_DA_Cx | AMD_RB_C3)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/7/src/cpu/amd/family_10h-family_15h/f… PS7, Line 504: if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/7/src/cpu/amd/family_10h-family_15h/f… PS7, Line 667: if ((((u32)0xffffffff) - initial_msr.lo) < corrected_timeout) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/7/src/cpu/amd/family_10h-family_15h/f… PS7, Line 676: || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo)); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/cpu/amd/family_10h-family_15h/f… PS7, Line 843: vid_max = (reg1fc & SINGLE_PLANE_NB_VID_MASK) >> SINGLE_PLANE_NB_VID_SHIFT; line over 80 characters https://review.coreboot.org/#/c/29161/7/src/cpu/amd/family_10h-family_15h/f… PS7, Line 844: fid_max = (reg1fc & SINGLE_PLANE_NB_FID_MASK) >> SINGLE_PLANE_NB_FID_SHIFT; line over 80 characters https://review.coreboot.org/#/c/29161/7/src/cpu/amd/family_10h-family_15h/f… PS7, Line 847: vid_max = vid_max - ((reg1fc & DUAL_PLANE_NB_VID_OFF_MASK) >> DUAL_PLANE_NB_VID_SHIFT); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/cpu/amd/family_10h-family_15h/f… PS7, Line 848: fid_max = fid_max + ((reg1fc & DUAL_PLANE_NB_FID_OFF_MASK) >> DUAL_PLANE_NB_FID_SHIFT); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/cpu/amd/family_10h-family_15h/p… File src/cpu/amd/family_10h-family_15h/powernow_acpi.c: https://review.coreboot.org/#/c/29161/7/src/cpu/amd/family_10h-family_15h/p… PS7, Line 229: * Based on the CPU socket type, cmp_cap and pwr_lmt, get the power limit. line over 80 characters https://review.coreboot.org/#/c/29161/7/src/cpu/via/nano/nano_init.c File src/cpu/via/nano/nano_init.c: https://review.coreboot.org/#/c/29161/7/src/cpu/via/nano/nano_init.c@125 PS7, Line 125: msr.lo |= ((1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */ line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/db-ft3b-lc/BiosCa… File src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/db-ft3b-lc/BiosCa… PS7, Line 145: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/lamar/BiosCallOut… File src/mainboard/amd/lamar/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/lamar/BiosCallOut… PS7, Line 162: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/olivehill/BiosCal… File src/mainboard/amd/olivehill/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/olivehill/BiosCal… PS7, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/olivehillplus/Bio… File src/mainboard/amd/olivehillplus/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/olivehillplus/Bio… PS7, Line 128: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/parmer/BiosCallOu… File src/mainboard/amd/parmer/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/parmer/BiosCallOu… PS7, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/serengeti_cheetah… File src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/serengeti_cheetah… PS7, Line 109: current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 5); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/serengeti_cheetah… File src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/serengeti_cheetah… PS7, Line 147: for (i = 1; i< sysconf.hc_possible_num; i++) { spaces required around that '<' (ctx:VxW) https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/serengeti_cheetah… File src/mainboard/amd/serengeti_cheetah_fam10/mptable.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/serengeti_cheetah… PS7, Line 110: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/serengeti_cheetah… PS7, Line 116: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/serengeti_cheetah… PS7, Line 122: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/serengeti_cheetah… PS7, Line 128: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/serengeti_cheetah… PS7, Line 150: for (ii = 0; ii < 4; ii++) { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/serengeti_cheetah… PS7, Line 150: for (ii = 0; ii < 4; ii++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/serengeti_cheetah… PS7, Line 163: for (ii = 0; ii < 4; ii++) { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/serengeti_cheetah… PS7, Line 163: for (ii = 0; ii < 4; ii++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/thatcher/BiosCall… File src/mainboard/amd/thatcher/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/thatcher/BiosCall… PS7, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/torpedo/gpio.c File src/mainboard/amd/torpedo/gpio.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/amd/torpedo/gpio.c@94 PS7, Line 94: if (BoardType == 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/7/src/mainboard/bap/ode_e20XX/BiosCal… File src/mainboard/bap/ode_e20XX/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/bap/ode_e20XX/BiosCal… PS7, Line 117: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/bap/ode_e21XX/BiosCal… File src/mainboard/bap/ode_e21XX/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/bap/ode_e21XX/BiosCal… PS7, Line 130: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/biostar/a68n_5200/Bio… File src/mainboard/biostar/a68n_5200/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/biostar/a68n_5200/Bio… PS7, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/gizmosphere/gizmo/Oem… File src/mainboard/gizmosphere/gizmo/OemCustomize.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/gizmosphere/gizmo/Oem… PS7, Line 126: HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/gizmosphere/gizmo2/Bi… File src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/gizmosphere/gizmo2/Bi… PS7, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/hp/pavilion_m6_1035dx… File src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/hp/pavilion_m6_1035dx… PS7, Line 115: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/lenovo/g505s/BiosCall… File src/mainboard/lenovo/g505s/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/lenovo/g505s/BiosCall… PS7, Line 115: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/lenovo/t60/smihandler… File src/mainboard/lenovo/t60/smihandler.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/lenovo/t60/smihandler… PS7, Line 52: printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/lenovo/z61t/smihandle… File src/mainboard/lenovo/z61t/smihandler.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/lenovo/z61t/smihandle… PS7, Line 53: printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/lippert/frontrunner-a… File src/mainboard/lippert/frontrunner-af/mainboard.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/lippert/frontrunner-a… PS7, Line 68: FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/lippert/frontrunner-a… PS7, Line 69: FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/7/src/mainboard/lippert/frontrunner-a… PS7, Line 72: FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/7/src/mainboard/lippert/frontrunner-a… PS7, Line 74: FCH_GPIO (57) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/7/src/mainboard/lippert/frontrunner-a… PS7, Line 76: FCH_GPIO (58) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/7/src/mainboard/lippert/frontrunner-a… PS7, Line 77: FCH_IOMUX(96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU) line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/lippert/frontrunner-a… PS7, Line 78: FCH_IOMUX(52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/lippert/toucan-af/mai… File src/mainboard/lippert/toucan-af/mainboard.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/lippert/toucan-af/mai… PS7, Line 36: FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/lippert/toucan-af/mai… PS7, Line 37: FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/7/src/mainboard/lippert/toucan-af/mai… PS7, Line 41: FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/7/src/mainboard/lippert/toucan-af/mai… PS7, Line 43: FCH_GPIO (57) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/7/src/mainboard/lippert/toucan-af/mai… PS7, Line 45: FCH_GPIO (58) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/7/src/mainboard/msi/ms9652_fam10/get_… File src/mainboard/msi/ms9652_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/msi/ms9652_fam10/get_… PS7, Line 104: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/msi/ms9652_fam10/get_… PS7, Line 109: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/pcengines/apu1/OemCus… File src/mainboard/pcengines/apu1/OemCustomize.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/pcengines/apu1/OemCus… PS7, Line 111: HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/pcengines/apu2/mainbo… File src/mainboard/pcengines/apu2/mainboard.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/pcengines/apu2/mainbo… PS7, Line 175: pm_write16(PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14)); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/supermicro/h8dmr_fam1… File src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/supermicro/h8dmr_fam1… PS7, Line 102: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/supermicro/h8dmr_fam1… PS7, Line 107: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/supermicro/h8qme_fam1… File src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/supermicro/h8qme_fam1… PS7, Line 108: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/supermicro/h8qme_fam1… PS7, Line 113: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/tyan/s2912_fam10/get_… File src/mainboard/tyan/s2912_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/7/src/mainboard/tyan/s2912_fam10/get_… PS7, Line 101: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/mainboard/tyan/s2912_fam10/get_… PS7, Line 106: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/northbridge/amd/agesa/family12/… File src/northbridge/amd/agesa/family12/dimmSpd.c: https://review.coreboot.org/#/c/29161/7/src/northbridge/amd/agesa/family12/… PS7, Line 58: ) please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/7/src/northbridge/intel/fsp_rangeley/… File src/northbridge/intel/fsp_rangeley/northbridge.c: https://review.coreboot.org/#/c/29161/7/src/northbridge/intel/fsp_rangeley/… PS7, Line 134: ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c File src/soc/broadcom/cygnus/ddr_init.c: https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 73: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 75: (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R))); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 78: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 83: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 85: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE))); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 87: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 91: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 93: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ))); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 96: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 98: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE))); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 100: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 104: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 106: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ))); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 113: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 118: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 131: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 137: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 143: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL) & 0xffff0fff)); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 149: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) & line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 156: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) & line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 167: #define SET_OVR_STEP(v) (0x30000 | ((v) & 0x3F)) /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */ line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 473: reg32_write((volatile uint32_t *)DDR_DENALI_CTL_43, (1 << 17) | (1 << 24) | (1 << 25)); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 479: if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) { line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 479: if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 485: if (j == 0 && (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) == 0) { line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 989: if ((((uint32_t)reg >= DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + 0x114))) line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 1007: if (CONFIG_SHMOO_REUSE_MEMTEST_LENGTH > 0) { please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 1140: reg32_write((uint32_t *)DDR_BistConfig,reg32_read((uint32_t *)DDR_BistConfig) & ~0x1); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 1140: reg32_write((uint32_t *)DDR_BistConfig,reg32_read((uint32_t *)DDR_BistConfig) & ~0x1); space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 1142: for (i = 0; i < 1000; i++); trailing statements should be on next line https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/ddr_init.c@… PS7, Line 1402: printk(BIOS_INFO, "PHY revision version: 0x%08x\n", val); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/phy_reg_acc… File src/soc/broadcom/cygnus/phy_reg_access.c: https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/phy_reg_acc… PS7, Line 20: data = (* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/broadcom/cygnus/phy_reg_acc… PS7, Line 27: ((* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))) = data); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/intel/baytrail/perf_power.c File src/soc/intel/baytrail/perf_power.c: https://review.coreboot.org/#/c/29161/7/src/soc/intel/baytrail/perf_power.c… PS7, Line 224: E(CCU, 0x1c, MASK_VAL(1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en line over 80 characters https://review.coreboot.org/#/c/29161/7/src/soc/intel/fsp_baytrail/northclu… File src/soc/intel/fsp_baytrail/northcluster.c: https://review.coreboot.org/#/c/29161/7/src/soc/intel/fsp_baytrail/northclu… PS7, Line 161: ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/southbridge/amd/cimx/sb800/fan.c File src/southbridge/amd/cimx/sb800/fan.c: https://review.coreboot.org/#/c/29161/7/src/southbridge/amd/cimx/sb800/fan.… PS7, Line 234: sb_config.Pecstruct.MSGFun89zone0MSGREG2 = (sb_chip->imc_tempin0_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/southbridge/amd/cimx/sb800/fan.… PS7, Line 238: sb_config.Pecstruct.MSGFun89zone0MSGREG6 = (sb_chip->imc_tempin0_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/southbridge/amd/cimx/sb800/fan.… PS7, Line 252: sb_config.Pecstruct.MSGFun89zone1MSGREG2 = (sb_chip->imc_tempin1_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/southbridge/amd/cimx/sb800/fan.… PS7, Line 256: sb_config.Pecstruct.MSGFun89zone1MSGREG6 = (sb_chip->imc_tempin1_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/southbridge/amd/cimx/sb800/fan.… PS7, Line 270: sb_config.Pecstruct.MSGFun89zone2MSGREG2 = (sb_chip->imc_tempin2_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/southbridge/amd/cimx/sb800/fan.… PS7, Line 274: sb_config.Pecstruct.MSGFun89zone2MSGREG6 = (sb_chip->imc_tempin2_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/southbridge/amd/cimx/sb800/fan.… PS7, Line 288: sb_config.Pecstruct.MSGFun89zone3MSGREG2 = (sb_chip->imc_tempin3_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/southbridge/amd/cimx/sb800/fan.… PS7, Line 292: sb_config.Pecstruct.MSGFun89zone3MSGREG6 = (sb_chip->imc_tempin3_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/southbridge/amd/rs780/gfx.c File src/southbridge/amd/rs780/gfx.c: https://review.coreboot.org/#/c/29161/7/src/southbridge/amd/rs780/gfx.c@250 PS7, Line 250: if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) { line over 80 characters https://review.coreboot.org/#/c/29161/7/src/southbridge/amd/rs780/gfx.c@250 PS7, Line 250: if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/7/src/southbridge/amd/sb700/sata.c File src/southbridge/amd/sb700/sata.c: https://review.coreboot.org/#/c/29161/7/src/southbridge/amd/sb700/sata.c@473 PS7, Line 473: (i % 2) ? "Slave" : "Master", i); line over 80 characters https://review.coreboot.org/#/c/29161/7/src/southbridge/amd/sr5650/pcie.c File src/southbridge/amd/sr5650/pcie.c: https://review.coreboot.org/#/c/29161/7/src/southbridge/amd/sr5650/pcie.c@8… PS7, Line 809: if (!((pci_read_config32(dev, 0x6C) >> 6) & 0x01)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/7/src/southbridge/intel/bd82x6x/early… File src/southbridge/intel/bd82x6x/early_usb.c: https://review.coreboot.org/#/c/29161/7/src/southbridge/intel/bd82x6x/early… PS7, Line 38: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/7/src/southbridge/intel/fsp_bd82x6x/e… File src/southbridge/intel/fsp_bd82x6x/early_init.c: https://review.coreboot.org/#/c/29161/7/src/southbridge/intel/fsp_bd82x6x/e… PS7, Line 145: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/7/src/southbridge/intel/fsp_i89xx/ear… File src/southbridge/intel/fsp_i89xx/early_init.c: https://review.coreboot.org/#/c/29161/7/src/southbridge/intel/fsp_i89xx/ear… PS7, Line 32: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/7/src/southbridge/nvidia/ck804/early_… File src/southbridge/nvidia/ck804/early_setup.c: https://review.coreboot.org/#/c/29161/7/src/southbridge/nvidia/ck804/early_… PS7, Line 258: RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23), line over 80 characters -- To view, visit https://review.coreboot.org/29161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Gerrit-Change-Number: 29161 Gerrit-PatchSet: 7 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 17 Oct 2018 11:09:44 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: src: Remove unneeded whitespace
by build bot (Jenkins) (Code Review) 17 Oct '18

17 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29161 ) Change subject: src: Remove unneeded whitespace ...................................................................... Patch Set 6: (110 comments) https://review.coreboot.org/#/c/29161/6/src/cpu/amd/family_10h-family_15h/f… File src/cpu/amd/family_10h-family_15h/fidvid.c: https://review.coreboot.org/#/c/29161/6/src/cpu/amd/family_10h-family_15h/f… PS6, Line 499: if (cpuRev & (AMD_DA_Cx | AMD_RB_C3)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/6/src/cpu/amd/family_10h-family_15h/f… PS6, Line 504: if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/6/src/cpu/amd/family_10h-family_15h/f… PS6, Line 667: if ((((u32)0xffffffff) - initial_msr.lo) < corrected_timeout) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/6/src/cpu/amd/family_10h-family_15h/f… PS6, Line 676: || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo)); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/cpu/amd/family_10h-family_15h/f… PS6, Line 843: vid_max = (reg1fc & SINGLE_PLANE_NB_VID_MASK) >> SINGLE_PLANE_NB_VID_SHIFT; line over 80 characters https://review.coreboot.org/#/c/29161/6/src/cpu/amd/family_10h-family_15h/f… PS6, Line 844: fid_max = (reg1fc & SINGLE_PLANE_NB_FID_MASK) >> SINGLE_PLANE_NB_FID_SHIFT; line over 80 characters https://review.coreboot.org/#/c/29161/6/src/cpu/amd/family_10h-family_15h/f… PS6, Line 847: vid_max = vid_max - ((reg1fc & DUAL_PLANE_NB_VID_OFF_MASK) >> DUAL_PLANE_NB_VID_SHIFT); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/cpu/amd/family_10h-family_15h/f… PS6, Line 848: fid_max = fid_max + ((reg1fc & DUAL_PLANE_NB_FID_OFF_MASK) >> DUAL_PLANE_NB_FID_SHIFT); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/cpu/amd/family_10h-family_15h/p… File src/cpu/amd/family_10h-family_15h/powernow_acpi.c: https://review.coreboot.org/#/c/29161/6/src/cpu/amd/family_10h-family_15h/p… PS6, Line 229: * Based on the CPU socket type, cmp_cap and pwr_lmt, get the power limit. line over 80 characters https://review.coreboot.org/#/c/29161/6/src/cpu/via/nano/nano_init.c File src/cpu/via/nano/nano_init.c: https://review.coreboot.org/#/c/29161/6/src/cpu/via/nano/nano_init.c@125 PS6, Line 125: msr.lo |= ((1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */ line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/db-ft3b-lc/BiosCa… File src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/db-ft3b-lc/BiosCa… PS6, Line 145: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/lamar/BiosCallOut… File src/mainboard/amd/lamar/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/lamar/BiosCallOut… PS6, Line 162: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/olivehill/BiosCal… File src/mainboard/amd/olivehill/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/olivehill/BiosCal… PS6, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/olivehillplus/Bio… File src/mainboard/amd/olivehillplus/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/olivehillplus/Bio… PS6, Line 128: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/parmer/BiosCallOu… File src/mainboard/amd/parmer/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/parmer/BiosCallOu… PS6, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah… File src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah… PS6, Line 109: current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 5); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah… File src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah… PS6, Line 147: for (i = 1; i< sysconf.hc_possible_num; i++) { spaces required around that '<' (ctx:VxW) https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah… File src/mainboard/amd/serengeti_cheetah_fam10/mptable.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah… PS6, Line 110: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah… PS6, Line 116: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah… PS6, Line 122: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah… PS6, Line 128: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah… PS6, Line 150: for (ii = 0; ii < 4; ii++) { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah… PS6, Line 150: for (ii = 0; ii < 4; ii++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah… PS6, Line 163: for (ii = 0; ii < 4; ii++) { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/serengeti_cheetah… PS6, Line 163: for (ii = 0; ii < 4; ii++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/thatcher/BiosCall… File src/mainboard/amd/thatcher/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/thatcher/BiosCall… PS6, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/torpedo/gpio.c File src/mainboard/amd/torpedo/gpio.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/amd/torpedo/gpio.c@94 PS6, Line 94: if (BoardType == 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/6/src/mainboard/bap/ode_e20XX/BiosCal… File src/mainboard/bap/ode_e20XX/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/bap/ode_e20XX/BiosCal… PS6, Line 117: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/bap/ode_e21XX/BiosCal… File src/mainboard/bap/ode_e21XX/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/bap/ode_e21XX/BiosCal… PS6, Line 130: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/biostar/a68n_5200/Bio… File src/mainboard/biostar/a68n_5200/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/biostar/a68n_5200/Bio… PS6, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/gizmosphere/gizmo/Oem… File src/mainboard/gizmosphere/gizmo/OemCustomize.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/gizmosphere/gizmo/Oem… PS6, Line 126: HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/gizmosphere/gizmo2/Bi… File src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/gizmosphere/gizmo2/Bi… PS6, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/hp/pavilion_m6_1035dx… File src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/hp/pavilion_m6_1035dx… PS6, Line 115: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/lenovo/g505s/BiosCall… File src/mainboard/lenovo/g505s/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/lenovo/g505s/BiosCall… PS6, Line 115: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/lenovo/t60/smihandler… File src/mainboard/lenovo/t60/smihandler.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/lenovo/t60/smihandler… PS6, Line 52: printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/lenovo/z61t/smihandle… File src/mainboard/lenovo/z61t/smihandler.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/lenovo/z61t/smihandle… PS6, Line 53: printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/frontrunner-a… File src/mainboard/lippert/frontrunner-af/mainboard.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/frontrunner-a… PS6, Line 68: FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/frontrunner-a… PS6, Line 69: FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/frontrunner-a… PS6, Line 72: FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/frontrunner-a… PS6, Line 74: FCH_GPIO (57) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/frontrunner-a… PS6, Line 76: FCH_GPIO (58) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/frontrunner-a… PS6, Line 77: FCH_IOMUX(96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU) line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/frontrunner-a… PS6, Line 78: FCH_IOMUX(52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/toucan-af/mai… File src/mainboard/lippert/toucan-af/mainboard.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/toucan-af/mai… PS6, Line 36: FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/toucan-af/mai… PS6, Line 37: FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/toucan-af/mai… PS6, Line 41: FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/toucan-af/mai… PS6, Line 43: FCH_GPIO (57) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/6/src/mainboard/lippert/toucan-af/mai… PS6, Line 45: FCH_GPIO (58) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/6/src/mainboard/msi/ms9652_fam10/get_… File src/mainboard/msi/ms9652_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/msi/ms9652_fam10/get_… PS6, Line 104: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/msi/ms9652_fam10/get_… PS6, Line 109: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/pcengines/apu1/OemCus… File src/mainboard/pcengines/apu1/OemCustomize.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/pcengines/apu1/OemCus… PS6, Line 111: HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/pcengines/apu2/mainbo… File src/mainboard/pcengines/apu2/mainboard.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/pcengines/apu2/mainbo… PS6, Line 175: pm_write16(PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14)); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/supermicro/h8dmr_fam1… File src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/supermicro/h8dmr_fam1… PS6, Line 102: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/supermicro/h8dmr_fam1… PS6, Line 107: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/supermicro/h8qme_fam1… File src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/supermicro/h8qme_fam1… PS6, Line 108: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/supermicro/h8qme_fam1… PS6, Line 113: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/tyan/s2912_fam10/get_… File src/mainboard/tyan/s2912_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/6/src/mainboard/tyan/s2912_fam10/get_… PS6, Line 101: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/mainboard/tyan/s2912_fam10/get_… PS6, Line 106: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/northbridge/amd/agesa/family12/… File src/northbridge/amd/agesa/family12/dimmSpd.c: https://review.coreboot.org/#/c/29161/6/src/northbridge/amd/agesa/family12/… PS6, Line 58: ) please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/6/src/northbridge/intel/fsp_rangeley/… File src/northbridge/intel/fsp_rangeley/northbridge.c: https://review.coreboot.org/#/c/29161/6/src/northbridge/intel/fsp_rangeley/… PS6, Line 134: ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c File src/soc/broadcom/cygnus/ddr_init.c: https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 73: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 75: (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R))); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 78: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 83: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 85: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE))); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 87: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 91: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 93: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ))); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 96: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 98: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE))); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 100: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 104: readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 106: (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ))); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 113: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 118: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 131: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 137: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) & line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 143: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL) & 0xffff0fff)); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 149: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) & line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 156: (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) & line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 167: #define SET_OVR_STEP(v) (0x30000 | ((v) & 0x3F)) /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */ line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 473: reg32_write((volatile uint32_t *)DDR_DENALI_CTL_43, (1 << 17) | (1 << 24) | (1 << 25)); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 479: if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) { line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 479: if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 485: if (j == 0 && (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) == 0) { line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 989: if ((((uint32_t)reg >= DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + 0x114))) line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 1007: if (CONFIG_SHMOO_REUSE_MEMTEST_LENGTH > 0) { please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 1142: for (i = 0; i < 1000; i++); please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 1142: for (i = 0; i < 1000; i++); trailing statements should be on next line https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/ddr_init.c@… PS6, Line 1402: printk(BIOS_INFO, "PHY revision version: 0x%08x\n", val); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/phy_reg_acc… File src/soc/broadcom/cygnus/phy_reg_access.c: https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/phy_reg_acc… PS6, Line 20: data = (* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/broadcom/cygnus/phy_reg_acc… PS6, Line 27: ((* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))) = data); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/intel/baytrail/perf_power.c File src/soc/intel/baytrail/perf_power.c: https://review.coreboot.org/#/c/29161/6/src/soc/intel/baytrail/perf_power.c… PS6, Line 224: E(CCU, 0x1c, MASK_VAL(1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en line over 80 characters https://review.coreboot.org/#/c/29161/6/src/soc/intel/fsp_baytrail/northclu… File src/soc/intel/fsp_baytrail/northcluster.c: https://review.coreboot.org/#/c/29161/6/src/soc/intel/fsp_baytrail/northclu… PS6, Line 161: ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/cimx/sb800/fan.c File src/southbridge/amd/cimx/sb800/fan.c: https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/cimx/sb800/fan.… PS6, Line 234: sb_config.Pecstruct.MSGFun89zone0MSGREG2 = (sb_chip->imc_tempin0_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/cimx/sb800/fan.… PS6, Line 238: sb_config.Pecstruct.MSGFun89zone0MSGREG6 = (sb_chip->imc_tempin0_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/cimx/sb800/fan.… PS6, Line 252: sb_config.Pecstruct.MSGFun89zone1MSGREG2 = (sb_chip->imc_tempin1_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/cimx/sb800/fan.… PS6, Line 256: sb_config.Pecstruct.MSGFun89zone1MSGREG6 = (sb_chip->imc_tempin1_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/cimx/sb800/fan.… PS6, Line 270: sb_config.Pecstruct.MSGFun89zone2MSGREG2 = (sb_chip->imc_tempin2_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/cimx/sb800/fan.… PS6, Line 274: sb_config.Pecstruct.MSGFun89zone2MSGREG6 = (sb_chip->imc_tempin2_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/cimx/sb800/fan.… PS6, Line 288: sb_config.Pecstruct.MSGFun89zone3MSGREG2 = (sb_chip->imc_tempin3_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/cimx/sb800/fan.… PS6, Line 292: sb_config.Pecstruct.MSGFun89zone3MSGREG6 = (sb_chip->imc_tempin3_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/rs780/gfx.c File src/southbridge/amd/rs780/gfx.c: https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/rs780/gfx.c@250 PS6, Line 250: if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) { line over 80 characters https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/rs780/gfx.c@250 PS6, Line 250: if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/sb700/sata.c File src/southbridge/amd/sb700/sata.c: https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/sb700/sata.c@473 PS6, Line 473: (i % 2) ? "Slave" : "Master", i); line over 80 characters https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/sr5650/pcie.c File src/southbridge/amd/sr5650/pcie.c: https://review.coreboot.org/#/c/29161/6/src/southbridge/amd/sr5650/pcie.c@8… PS6, Line 809: if (!((pci_read_config32(dev, 0x6C) >> 6) & 0x01)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/6/src/southbridge/intel/bd82x6x/early… File src/southbridge/intel/bd82x6x/early_usb.c: https://review.coreboot.org/#/c/29161/6/src/southbridge/intel/bd82x6x/early… PS6, Line 38: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/6/src/southbridge/intel/fsp_bd82x6x/e… File src/southbridge/intel/fsp_bd82x6x/early_init.c: https://review.coreboot.org/#/c/29161/6/src/southbridge/intel/fsp_bd82x6x/e… PS6, Line 145: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/6/src/southbridge/intel/fsp_i89xx/ear… File src/southbridge/intel/fsp_i89xx/early_init.c: https://review.coreboot.org/#/c/29161/6/src/southbridge/intel/fsp_i89xx/ear… PS6, Line 32: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/6/src/southbridge/nvidia/ck804/early_… File src/southbridge/nvidia/ck804/early_setup.c: https://review.coreboot.org/#/c/29161/6/src/southbridge/nvidia/ck804/early_… PS6, Line 258: RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23), line over 80 characters -- To view, visit https://review.coreboot.org/29161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Gerrit-Change-Number: 29161 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 17 Oct 2018 11:03:40 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: src: Remove unneeded whitespace
by build bot (Jenkins) (Code Review) 17 Oct '18

17 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29161 ) Change subject: src: Remove unneeded whitespace ...................................................................... Patch Set 5: (98 comments) https://review.coreboot.org/#/c/29161/5/src/cpu/amd/family_10h-family_15h/f… File src/cpu/amd/family_10h-family_15h/fidvid.c: https://review.coreboot.org/#/c/29161/5/src/cpu/amd/family_10h-family_15h/f… PS5, Line 499: if (cpuRev & (AMD_DA_Cx | AMD_RB_C3)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/5/src/cpu/amd/family_10h-family_15h/f… PS5, Line 504: if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/5/src/cpu/amd/family_10h-family_15h/f… PS5, Line 667: if ((((u32)0xffffffff) - initial_msr.lo) < corrected_timeout) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/5/src/cpu/amd/family_10h-family_15h/f… PS5, Line 676: || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo)); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/cpu/amd/family_10h-family_15h/f… PS5, Line 843: vid_max = (reg1fc & SINGLE_PLANE_NB_VID_MASK) >> SINGLE_PLANE_NB_VID_SHIFT; line over 80 characters https://review.coreboot.org/#/c/29161/5/src/cpu/amd/family_10h-family_15h/f… PS5, Line 844: fid_max = (reg1fc & SINGLE_PLANE_NB_FID_MASK) >> SINGLE_PLANE_NB_FID_SHIFT; line over 80 characters https://review.coreboot.org/#/c/29161/5/src/cpu/amd/family_10h-family_15h/f… PS5, Line 847: vid_max = vid_max - ((reg1fc & DUAL_PLANE_NB_VID_OFF_MASK) >> DUAL_PLANE_NB_VID_SHIFT); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/cpu/amd/family_10h-family_15h/f… PS5, Line 848: fid_max = fid_max + ((reg1fc & DUAL_PLANE_NB_FID_OFF_MASK) >> DUAL_PLANE_NB_FID_SHIFT); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/cpu/amd/family_10h-family_15h/p… File src/cpu/amd/family_10h-family_15h/powernow_acpi.c: https://review.coreboot.org/#/c/29161/5/src/cpu/amd/family_10h-family_15h/p… PS5, Line 229: * Based on the CPU socket type, cmp_cap and pwr_lmt, get the power limit. line over 80 characters https://review.coreboot.org/#/c/29161/5/src/cpu/via/nano/nano_init.c File src/cpu/via/nano/nano_init.c: https://review.coreboot.org/#/c/29161/5/src/cpu/via/nano/nano_init.c@125 PS5, Line 125: msr.lo |= ((1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */ line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/db-ft3b-lc/BiosCa… File src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/db-ft3b-lc/BiosCa… PS5, Line 145: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/lamar/BiosCallOut… File src/mainboard/amd/lamar/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/lamar/BiosCallOut… PS5, Line 162: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/olivehill/BiosCal… File src/mainboard/amd/olivehill/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/olivehill/BiosCal… PS5, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/olivehillplus/Bio… File src/mainboard/amd/olivehillplus/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/olivehillplus/Bio… PS5, Line 128: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/parmer/BiosCallOu… File src/mainboard/amd/parmer/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/parmer/BiosCallOu… PS5, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah… File src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah… PS5, Line 109: current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 5); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah… File src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah… PS5, Line 147: for (i = 1; i< sysconf.hc_possible_num; i++) { spaces required around that '<' (ctx:VxW) https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah… File src/mainboard/amd/serengeti_cheetah_fam10/mptable.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah… PS5, Line 110: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah… PS5, Line 116: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah… PS5, Line 122: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah… PS5, Line 128: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah… PS5, Line 150: for (ii = 0; ii < 4; ii++) { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah… PS5, Line 150: for (ii = 0; ii < 4; ii++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah… PS5, Line 163: for (ii = 0; ii < 4; ii++) { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/serengeti_cheetah… PS5, Line 163: for (ii = 0; ii < 4; ii++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/thatcher/BiosCall… File src/mainboard/amd/thatcher/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/thatcher/BiosCall… PS5, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/torpedo/gpio.c File src/mainboard/amd/torpedo/gpio.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/amd/torpedo/gpio.c@94 PS5, Line 94: if (BoardType == 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/5/src/mainboard/bap/ode_e20XX/BiosCal… File src/mainboard/bap/ode_e20XX/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/bap/ode_e20XX/BiosCal… PS5, Line 117: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/bap/ode_e21XX/BiosCal… File src/mainboard/bap/ode_e21XX/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/bap/ode_e21XX/BiosCal… PS5, Line 130: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/biostar/a68n_5200/Bio… File src/mainboard/biostar/a68n_5200/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/biostar/a68n_5200/Bio… PS5, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/gizmosphere/gizmo/Oem… File src/mainboard/gizmosphere/gizmo/OemCustomize.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/gizmosphere/gizmo/Oem… PS5, Line 126: HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/gizmosphere/gizmo2/Bi… File src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/gizmosphere/gizmo2/Bi… PS5, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/hp/pavilion_m6_1035dx… File src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/hp/pavilion_m6_1035dx… PS5, Line 115: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/lenovo/g505s/BiosCall… File src/mainboard/lenovo/g505s/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/lenovo/g505s/BiosCall… PS5, Line 115: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/lenovo/t60/smihandler… File src/mainboard/lenovo/t60/smihandler.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/lenovo/t60/smihandler… PS5, Line 52: printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/lenovo/z61t/smihandle… File src/mainboard/lenovo/z61t/smihandler.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/lenovo/z61t/smihandle… PS5, Line 53: printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/frontrunner-a… File src/mainboard/lippert/frontrunner-af/mainboard.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/frontrunner-a… PS5, Line 68: FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/frontrunner-a… PS5, Line 69: FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/frontrunner-a… PS5, Line 72: FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/frontrunner-a… PS5, Line 74: FCH_GPIO (57) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/frontrunner-a… PS5, Line 76: FCH_GPIO (58) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/frontrunner-a… PS5, Line 77: FCH_IOMUX(96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU) line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/frontrunner-a… PS5, Line 78: FCH_IOMUX(52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/toucan-af/mai… File src/mainboard/lippert/toucan-af/mainboard.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/toucan-af/mai… PS5, Line 36: FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/toucan-af/mai… PS5, Line 37: FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/toucan-af/mai… PS5, Line 41: FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/toucan-af/mai… PS5, Line 43: FCH_GPIO (57) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/5/src/mainboard/lippert/toucan-af/mai… PS5, Line 45: FCH_GPIO (58) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/5/src/mainboard/msi/ms9652_fam10/get_… File src/mainboard/msi/ms9652_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/msi/ms9652_fam10/get_… PS5, Line 104: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/msi/ms9652_fam10/get_… PS5, Line 109: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/pcengines/apu1/OemCus… File src/mainboard/pcengines/apu1/OemCustomize.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/pcengines/apu1/OemCus… PS5, Line 111: HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/pcengines/apu2/mainbo… File src/mainboard/pcengines/apu2/mainboard.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/pcengines/apu2/mainbo… PS5, Line 175: pm_write16(PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14)); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/supermicro/h8dmr_fam1… File src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/supermicro/h8dmr_fam1… PS5, Line 102: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/supermicro/h8dmr_fam1… PS5, Line 107: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/supermicro/h8qme_fam1… File src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/supermicro/h8qme_fam1… PS5, Line 108: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/supermicro/h8qme_fam1… PS5, Line 113: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/tyan/s2912_fam10/get_… File src/mainboard/tyan/s2912_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/5/src/mainboard/tyan/s2912_fam10/get_… PS5, Line 101: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/mainboard/tyan/s2912_fam10/get_… PS5, Line 106: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/northbridge/amd/agesa/family12/… File src/northbridge/amd/agesa/family12/dimmSpd.c: https://review.coreboot.org/#/c/29161/5/src/northbridge/amd/agesa/family12/… PS5, Line 58: ) please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/5/src/northbridge/intel/fsp_rangeley/… File src/northbridge/intel/fsp_rangeley/northbridge.c: https://review.coreboot.org/#/c/29161/5/src/northbridge/intel/fsp_rangeley/… PS5, Line 134: ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c File src/soc/broadcom/cygnus/ddr_init.c: https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@… PS5, Line 74: reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL, (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R))); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@… PS5, Line 78: reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL, (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ))); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@… PS5, Line 82: reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE))); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@… PS5, Line 85: reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, (readvalue & 0xffff800f)); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@… PS5, Line 88: reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ))); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@… PS5, Line 92: reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE))); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@… PS5, Line 95: reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, (readvalue & 0xffff800f)); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@… PS5, Line 98: reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ))); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@… PS5, Line 146: #define SET_OVR_STEP(v) (0x30000 | ((v) & 0x3F)) /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */ line over 80 characters https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@… PS5, Line 452: reg32_write((volatile uint32_t *)DDR_DENALI_CTL_43, (1 << 17) | (1 << 24) | (1 << 25)); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@… PS5, Line 458: if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) { line over 80 characters https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@… PS5, Line 458: if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@… PS5, Line 464: if (j == 0 && (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) == 0) { line over 80 characters https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@… PS5, Line 968: if ((((uint32_t)reg >= DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + 0x114))) line over 80 characters https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@… PS5, Line 986: if (CONFIG_SHMOO_REUSE_MEMTEST_LENGTH > 0) { please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@… PS5, Line 1121: for (i = 0; i < 1000; i++); please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@… PS5, Line 1121: for (i = 0; i < 1000; i++); trailing statements should be on next line https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/ddr_init.c@… PS5, Line 1381: printk(BIOS_INFO, "PHY revision version: 0x%08x\n", val); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/phy_reg_acc… File src/soc/broadcom/cygnus/phy_reg_access.c: https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/phy_reg_acc… PS5, Line 20: data = (* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/soc/broadcom/cygnus/phy_reg_acc… PS5, Line 27: ((* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))) = data); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/soc/intel/baytrail/perf_power.c File src/soc/intel/baytrail/perf_power.c: https://review.coreboot.org/#/c/29161/5/src/soc/intel/baytrail/perf_power.c… PS5, Line 224: E(CCU, 0x1c, MASK_VAL(1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en line over 80 characters https://review.coreboot.org/#/c/29161/5/src/soc/intel/fsp_baytrail/northclu… File src/soc/intel/fsp_baytrail/northcluster.c: https://review.coreboot.org/#/c/29161/5/src/soc/intel/fsp_baytrail/northclu… PS5, Line 161: ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/cimx/sb800/fan.c File src/southbridge/amd/cimx/sb800/fan.c: https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/cimx/sb800/fan.… PS5, Line 234: sb_config.Pecstruct.MSGFun89zone0MSGREG2 = (sb_chip->imc_tempin0_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/cimx/sb800/fan.… PS5, Line 238: sb_config.Pecstruct.MSGFun89zone0MSGREG6 = (sb_chip->imc_tempin0_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/cimx/sb800/fan.… PS5, Line 252: sb_config.Pecstruct.MSGFun89zone1MSGREG2 = (sb_chip->imc_tempin1_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/cimx/sb800/fan.… PS5, Line 256: sb_config.Pecstruct.MSGFun89zone1MSGREG6 = (sb_chip->imc_tempin1_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/cimx/sb800/fan.… PS5, Line 270: sb_config.Pecstruct.MSGFun89zone2MSGREG2 = (sb_chip->imc_tempin2_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/cimx/sb800/fan.… PS5, Line 274: sb_config.Pecstruct.MSGFun89zone2MSGREG6 = (sb_chip->imc_tempin2_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/cimx/sb800/fan.… PS5, Line 288: sb_config.Pecstruct.MSGFun89zone3MSGREG2 = (sb_chip->imc_tempin3_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/cimx/sb800/fan.… PS5, Line 292: sb_config.Pecstruct.MSGFun89zone3MSGREG6 = (sb_chip->imc_tempin3_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/rs780/gfx.c File src/southbridge/amd/rs780/gfx.c: https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/rs780/gfx.c@250 PS5, Line 250: if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) { line over 80 characters https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/rs780/gfx.c@250 PS5, Line 250: if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/sb700/sata.c File src/southbridge/amd/sb700/sata.c: https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/sb700/sata.c@473 PS5, Line 473: (i % 2) ? "Slave" : "Master", i); line over 80 characters https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/sr5650/pcie.c File src/southbridge/amd/sr5650/pcie.c: https://review.coreboot.org/#/c/29161/5/src/southbridge/amd/sr5650/pcie.c@8… PS5, Line 809: if (!((pci_read_config32(dev, 0x6C) >> 6) & 0x01)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/5/src/southbridge/intel/bd82x6x/early… File src/southbridge/intel/bd82x6x/early_usb.c: https://review.coreboot.org/#/c/29161/5/src/southbridge/intel/bd82x6x/early… PS5, Line 38: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/5/src/southbridge/intel/fsp_bd82x6x/e… File src/southbridge/intel/fsp_bd82x6x/early_init.c: https://review.coreboot.org/#/c/29161/5/src/southbridge/intel/fsp_bd82x6x/e… PS5, Line 145: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/5/src/southbridge/intel/fsp_i89xx/ear… File src/southbridge/intel/fsp_i89xx/early_init.c: https://review.coreboot.org/#/c/29161/5/src/southbridge/intel/fsp_i89xx/ear… PS5, Line 32: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/5/src/southbridge/nvidia/ck804/early_… File src/southbridge/nvidia/ck804/early_setup.c: https://review.coreboot.org/#/c/29161/5/src/southbridge/nvidia/ck804/early_… PS5, Line 258: RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23), line over 80 characters -- To view, visit https://review.coreboot.org/29161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Gerrit-Change-Number: 29161 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 17 Oct 2018 10:52:42 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: src: Remove unneeded whitespace
by build bot (Jenkins) (Code Review) 17 Oct '18

17 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29161 ) Change subject: src: Remove unneeded whitespace ...................................................................... Patch Set 4: (113 comments) https://review.coreboot.org/#/c/29161/4/src/cpu/amd/family_10h-family_15h/f… File src/cpu/amd/family_10h-family_15h/fidvid.c: https://review.coreboot.org/#/c/29161/4/src/cpu/amd/family_10h-family_15h/f… PS4, Line 499: if (cpuRev & (AMD_DA_Cx | AMD_RB_C3)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/4/src/cpu/amd/family_10h-family_15h/f… PS4, Line 504: if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/4/src/cpu/amd/family_10h-family_15h/f… PS4, Line 667: if ((((u32)0xffffffff) - initial_msr.lo) < corrected_timeout) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/4/src/cpu/amd/family_10h-family_15h/f… PS4, Line 676: || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo)); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/cpu/amd/family_10h-family_15h/f… PS4, Line 843: vid_max = (reg1fc & SINGLE_PLANE_NB_VID_MASK) >> SINGLE_PLANE_NB_VID_SHIFT; line over 80 characters https://review.coreboot.org/#/c/29161/4/src/cpu/amd/family_10h-family_15h/f… PS4, Line 844: fid_max = (reg1fc & SINGLE_PLANE_NB_FID_MASK) >> SINGLE_PLANE_NB_FID_SHIFT; line over 80 characters https://review.coreboot.org/#/c/29161/4/src/cpu/amd/family_10h-family_15h/f… PS4, Line 847: vid_max = vid_max - ((reg1fc & DUAL_PLANE_NB_VID_OFF_MASK) >> DUAL_PLANE_NB_VID_SHIFT); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/cpu/amd/family_10h-family_15h/f… PS4, Line 848: fid_max = fid_max + ((reg1fc & DUAL_PLANE_NB_FID_OFF_MASK) >> DUAL_PLANE_NB_FID_SHIFT); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/cpu/amd/family_10h-family_15h/p… File src/cpu/amd/family_10h-family_15h/powernow_acpi.c: https://review.coreboot.org/#/c/29161/4/src/cpu/amd/family_10h-family_15h/p… PS4, Line 229: * Based on the CPU socket type, cmp_cap and pwr_lmt, get the power limit. line over 80 characters https://review.coreboot.org/#/c/29161/4/src/cpu/via/nano/nano_init.c File src/cpu/via/nano/nano_init.c: https://review.coreboot.org/#/c/29161/4/src/cpu/via/nano/nano_init.c@125 PS4, Line 125: msr.lo |= ((1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */ line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/db-ft3b-lc/BiosCa… File src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/db-ft3b-lc/BiosCa… PS4, Line 145: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/lamar/BiosCallOut… File src/mainboard/amd/lamar/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/lamar/BiosCallOut… PS4, Line 162: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/olivehill/BiosCal… File src/mainboard/amd/olivehill/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/olivehill/BiosCal… PS4, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/olivehillplus/Bio… File src/mainboard/amd/olivehillplus/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/olivehillplus/Bio… PS4, Line 128: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/parmer/BiosCallOu… File src/mainboard/amd/parmer/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/parmer/BiosCallOu… PS4, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/serengeti_cheetah… File src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/serengeti_cheetah… PS4, Line 109: current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 5); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/serengeti_cheetah… PS4, Line 141: if ((sysconf.pci1234[i] & 1) != 1) continue; trailing statements should be on next line https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/serengeti_cheetah… File src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/serengeti_cheetah… PS4, Line 148: if(!(sysconf.pci1234[i] & 0x1)) continue; space required before the open parenthesis '(' https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/serengeti_cheetah… PS4, Line 148: if(!(sysconf.pci1234[i] & 0x1)) continue; trailing statements should be on next line https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/serengeti_cheetah… File src/mainboard/amd/serengeti_cheetah_fam10/mptable.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/serengeti_cheetah… PS4, Line 70: for (i = 1; i< sysconf.hc_possible_num; i++) { spaces required around that '<' (ctx:VxW) https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/serengeti_cheetah… PS4, Line 110: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/serengeti_cheetah… PS4, Line 116: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/serengeti_cheetah… PS4, Line 122: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/serengeti_cheetah… PS4, Line 128: for (i = 0; i < 4; i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/serengeti_cheetah… PS4, Line 135: if(!(sysconf.pci1234[i] & 0x1)) continue; space required before the open parenthesis '(' https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/serengeti_cheetah… PS4, Line 135: if(!(sysconf.pci1234[i] & 0x1)) continue; trailing statements should be on next line https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/serengeti_cheetah… PS4, Line 149: for (ii = 0; ii < 4; ii++) { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/serengeti_cheetah… PS4, Line 149: for (ii = 0; ii < 4; ii++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/serengeti_cheetah… PS4, Line 162: for (ii = 0; ii < 4; ii++) { Too many leading tabs - consider code refactoring https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/serengeti_cheetah… PS4, Line 162: for (ii = 0; ii < 4; ii++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/thatcher/BiosCall… File src/mainboard/amd/thatcher/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/thatcher/BiosCall… PS4, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/torpedo/gpio.c File src/mainboard/amd/torpedo/gpio.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/amd/torpedo/gpio.c@94 PS4, Line 94: if (BoardType == 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/4/src/mainboard/bap/ode_e20XX/BiosCal… File src/mainboard/bap/ode_e20XX/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/bap/ode_e20XX/BiosCal… PS4, Line 117: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/bap/ode_e21XX/BiosCal… File src/mainboard/bap/ode_e21XX/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/bap/ode_e21XX/BiosCal… PS4, Line 130: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/biostar/a68n_5200/Bio… File src/mainboard/biostar/a68n_5200/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/biostar/a68n_5200/Bio… PS4, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/gizmosphere/gizmo/Oem… File src/mainboard/gizmosphere/gizmo/OemCustomize.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/gizmosphere/gizmo/Oem… PS4, Line 126: HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/gizmosphere/gizmo2/Bi… File src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/gizmosphere/gizmo2/Bi… PS4, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/hp/pavilion_m6_1035dx… File src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/hp/pavilion_m6_1035dx… PS4, Line 115: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/lenovo/g505s/BiosCall… File src/mainboard/lenovo/g505s/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/lenovo/g505s/BiosCall… PS4, Line 115: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/lenovo/t60/smihandler… File src/mainboard/lenovo/t60/smihandler.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/lenovo/t60/smihandler… PS4, Line 52: printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/lenovo/z61t/smihandle… File src/mainboard/lenovo/z61t/smihandler.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/lenovo/z61t/smihandle… PS4, Line 53: printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/lippert/frontrunner-a… File src/mainboard/lippert/frontrunner-af/mainboard.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/lippert/frontrunner-a… PS4, Line 68: FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/lippert/frontrunner-a… PS4, Line 69: FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/4/src/mainboard/lippert/frontrunner-a… PS4, Line 72: FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/4/src/mainboard/lippert/frontrunner-a… PS4, Line 74: FCH_GPIO (57) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/4/src/mainboard/lippert/frontrunner-a… PS4, Line 76: FCH_GPIO (58) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/4/src/mainboard/lippert/frontrunner-a… PS4, Line 77: FCH_IOMUX(96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU) line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/lippert/frontrunner-a… PS4, Line 78: FCH_IOMUX(52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/lippert/toucan-af/mai… File src/mainboard/lippert/toucan-af/mainboard.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/lippert/toucan-af/mai… PS4, Line 36: FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/lippert/toucan-af/mai… PS4, Line 37: FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/4/src/mainboard/lippert/toucan-af/mai… PS4, Line 41: FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/4/src/mainboard/lippert/toucan-af/mai… PS4, Line 43: FCH_GPIO (57) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/4/src/mainboard/lippert/toucan-af/mai… PS4, Line 45: FCH_GPIO (58) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/4/src/mainboard/msi/ms9652_fam10/get_… File src/mainboard/msi/ms9652_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/msi/ms9652_fam10/get_… PS4, Line 104: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/msi/ms9652_fam10/get_… PS4, Line 109: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/pcengines/apu1/OemCus… File src/mainboard/pcengines/apu1/OemCustomize.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/pcengines/apu1/OemCus… PS4, Line 111: HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/pcengines/apu2/mainbo… File src/mainboard/pcengines/apu2/mainboard.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/pcengines/apu2/mainbo… PS4, Line 175: pm_write16(PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14)); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/supermicro/h8dmr_fam1… File src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/supermicro/h8dmr_fam1… PS4, Line 102: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/supermicro/h8dmr_fam1… PS4, Line 107: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/supermicro/h8qme_fam1… File src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/supermicro/h8qme_fam1… PS4, Line 108: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/supermicro/h8qme_fam1… PS4, Line 113: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/tyan/s2912_fam10/get_… File src/mainboard/tyan/s2912_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/4/src/mainboard/tyan/s2912_fam10/get_… PS4, Line 101: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/mainboard/tyan/s2912_fam10/get_… PS4, Line 106: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/northbridge/amd/agesa/family12/… File src/northbridge/amd/agesa/family12/dimmSpd.c: https://review.coreboot.org/#/c/29161/4/src/northbridge/amd/agesa/family12/… PS4, Line 58: ) please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/4/src/northbridge/intel/fsp_rangeley/… File src/northbridge/intel/fsp_rangeley/northbridge.c: https://review.coreboot.org/#/c/29161/4/src/northbridge/intel/fsp_rangeley/… PS4, Line 134: ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/ddr_init.c File src/soc/broadcom/cygnus/ddr_init.c: https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/ddr_init.c@… PS4, Line 74: reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL, (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R))); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/ddr_init.c@… PS4, Line 78: reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL, (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ))); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/ddr_init.c@… PS4, Line 82: reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE))); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/ddr_init.c@… PS4, Line 85: reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, (readvalue & 0xffff800f)); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/ddr_init.c@… PS4, Line 88: reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ))); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/ddr_init.c@… PS4, Line 92: reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE))); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/ddr_init.c@… PS4, Line 95: reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, (readvalue & 0xffff800f)); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/ddr_init.c@… PS4, Line 98: reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ))); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/ddr_init.c@… PS4, Line 146: #define SET_OVR_STEP(v) (0x30000 | ((v) & 0x3F)) /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */ line over 80 characters https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/ddr_init.c@… PS4, Line 452: reg32_write((volatile uint32_t *)DDR_DENALI_CTL_43, (1 << 17) | (1 << 24) | (1 << 25)); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/ddr_init.c@… PS4, Line 458: if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) { line over 80 characters https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/ddr_init.c@… PS4, Line 458: if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/ddr_init.c@… PS4, Line 464: if (j == 0 && (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) == 0) { line over 80 characters https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/ddr_init.c@… PS4, Line 968: if ((((uint32_t)reg >= DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + 0x114))) line over 80 characters https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/ddr_init.c@… PS4, Line 986: if (CONFIG_SHMOO_REUSE_MEMTEST_LENGTH > 0) { please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/ddr_init.c@… PS4, Line 1121: for (i = 0; i < 1000; i++); please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/ddr_init.c@… PS4, Line 1121: for (i = 0; i < 1000; i++); trailing statements should be on next line https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/ddr_init.c@… PS4, Line 1381: printk(BIOS_INFO, "PHY revision version: 0x%08x\n", val); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/ddr_init.c@… PS4, Line 1383: } code indent should use tabs where possible https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/ddr_init.c@… PS4, Line 1383: } please, no space before tabs https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/ddr_init.c@… PS4, Line 1383: } please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/phy_reg_acc… File src/soc/broadcom/cygnus/phy_reg_access.c: https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/phy_reg_acc… PS4, Line 20: data = (* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/phy_reg_acc… PS4, Line 20: data = (* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))); code indent should use tabs where possible https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/phy_reg_acc… PS4, Line 20: data = (* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))); please, no space before tabs https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/phy_reg_acc… PS4, Line 20: data = (* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))); please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/phy_reg_acc… PS4, Line 21: //printf("REGRD %08X=%08X\n", address, data); code indent should use tabs where possible https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/phy_reg_acc… PS4, Line 21: //printf("REGRD %08X=%08X\n", address, data); please, no space before tabs https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/phy_reg_acc… PS4, Line 21: //printf("REGRD %08X=%08X\n", address, data); please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/4/src/soc/broadcom/cygnus/phy_reg_acc… PS4, Line 27: ((* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))) = data); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/soc/intel/baytrail/perf_power.c File src/soc/intel/baytrail/perf_power.c: https://review.coreboot.org/#/c/29161/4/src/soc/intel/baytrail/perf_power.c… PS4, Line 224: E(CCU, 0x1c, MASK_VAL(1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en line over 80 characters https://review.coreboot.org/#/c/29161/4/src/soc/intel/fsp_baytrail/northclu… File src/soc/intel/fsp_baytrail/northcluster.c: https://review.coreboot.org/#/c/29161/4/src/soc/intel/fsp_baytrail/northclu… PS4, Line 161: ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/southbridge/amd/agesa/hudson/ea… File src/southbridge/amd/agesa/hudson/early_setup.c: https://review.coreboot.org/#/c/29161/4/src/southbridge/amd/agesa/hudson/ea… PS4, Line 99: outb((dword >>(8 * i)) & 0xff, BIOSRAM_DATA); need consistent spacing around '>>' (ctx:WxV) https://review.coreboot.org/#/c/29161/4/src/southbridge/amd/cimx/sb800/fan.c File src/southbridge/amd/cimx/sb800/fan.c: https://review.coreboot.org/#/c/29161/4/src/southbridge/amd/cimx/sb800/fan.… PS4, Line 234: sb_config.Pecstruct.MSGFun89zone0MSGREG2 = (sb_chip->imc_tempin0_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/southbridge/amd/cimx/sb800/fan.… PS4, Line 238: sb_config.Pecstruct.MSGFun89zone0MSGREG6 = (sb_chip->imc_tempin0_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/southbridge/amd/cimx/sb800/fan.… PS4, Line 252: sb_config.Pecstruct.MSGFun89zone1MSGREG2 = (sb_chip->imc_tempin1_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/southbridge/amd/cimx/sb800/fan.… PS4, Line 256: sb_config.Pecstruct.MSGFun89zone1MSGREG6 = (sb_chip->imc_tempin1_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/southbridge/amd/cimx/sb800/fan.… PS4, Line 270: sb_config.Pecstruct.MSGFun89zone2MSGREG2 = (sb_chip->imc_tempin2_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/southbridge/amd/cimx/sb800/fan.… PS4, Line 274: sb_config.Pecstruct.MSGFun89zone2MSGREG6 = (sb_chip->imc_tempin2_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/southbridge/amd/cimx/sb800/fan.… PS4, Line 288: sb_config.Pecstruct.MSGFun89zone3MSGREG2 = (sb_chip->imc_tempin3_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/southbridge/amd/cimx/sb800/fan.… PS4, Line 292: sb_config.Pecstruct.MSGFun89zone3MSGREG6 = (sb_chip->imc_tempin3_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/southbridge/amd/rs780/gfx.c File src/southbridge/amd/rs780/gfx.c: https://review.coreboot.org/#/c/29161/4/src/southbridge/amd/rs780/gfx.c@250 PS4, Line 250: if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) { line over 80 characters https://review.coreboot.org/#/c/29161/4/src/southbridge/amd/rs780/gfx.c@250 PS4, Line 250: if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/4/src/southbridge/amd/sb700/sata.c File src/southbridge/amd/sb700/sata.c: https://review.coreboot.org/#/c/29161/4/src/southbridge/amd/sb700/sata.c@473 PS4, Line 473: (i % 2) ? "Slave" : "Master", i); line over 80 characters https://review.coreboot.org/#/c/29161/4/src/southbridge/amd/sr5650/pcie.c File src/southbridge/amd/sr5650/pcie.c: https://review.coreboot.org/#/c/29161/4/src/southbridge/amd/sr5650/pcie.c@8… PS4, Line 809: if (!((pci_read_config32(dev, 0x6C) >> 6) & 0x01)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/4/src/southbridge/intel/bd82x6x/early… File src/southbridge/intel/bd82x6x/early_usb.c: https://review.coreboot.org/#/c/29161/4/src/southbridge/intel/bd82x6x/early… PS4, Line 38: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/4/src/southbridge/intel/fsp_bd82x6x/e… File src/southbridge/intel/fsp_bd82x6x/early_init.c: https://review.coreboot.org/#/c/29161/4/src/southbridge/intel/fsp_bd82x6x/e… PS4, Line 145: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/4/src/southbridge/intel/fsp_i89xx/ear… File src/southbridge/intel/fsp_i89xx/early_init.c: https://review.coreboot.org/#/c/29161/4/src/southbridge/intel/fsp_i89xx/ear… PS4, Line 32: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/4/src/southbridge/nvidia/ck804/early_… File src/southbridge/nvidia/ck804/early_setup.c: https://review.coreboot.org/#/c/29161/4/src/southbridge/nvidia/ck804/early_… PS4, Line 258: RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23), line over 80 characters -- To view, visit https://review.coreboot.org/29161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Gerrit-Change-Number: 29161 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 17 Oct 2018 10:33:07 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: cpu/amd: Use common AMD's MSR
by build bot (Jenkins) (Code Review) 17 Oct '18

17 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29065 ) Change subject: cpu/amd: Use common AMD's MSR ...................................................................... Patch Set 20: (8 comments) https://review.coreboot.org/#/c/29065/20/src/cpu/amd/family_10h-family_15h/… File src/cpu/amd/family_10h-family_15h/defaults.h: https://review.coreboot.org/#/c/29065/20/src/cpu/amd/family_10h-family_15h/… PS20, Line 77: { NB_CFG_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC | AMD_PTYPE_MC, line over 80 characters https://review.coreboot.org/#/c/29065/20/src/cpu/amd/family_10h-family_15h/… PS20, Line 107: 1 << 21, 0x00000000 }, /* Erratum #254 DR B1 BU_CFG_MSR[21]=1 */ line over 80 characters https://review.coreboot.org/#/c/29065/20/src/cpu/amd/family_10h-family_15h/… PS20, Line 118: { CPU_ID_FEATURES_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC | AMD_PTYPE_MC, line over 80 characters https://review.coreboot.org/#/c/29065/20/src/include/cpu/amd/msr.h File src/include/cpu/amd/msr.h: https://review.coreboot.org/#/c/29065/20/src/include/cpu/amd/msr.h@40 PS20, Line 40: #define PS_CTL_REG 0xC0010062 /* P-state Control Register */ line over 80 characters https://review.coreboot.org/#/c/29065/20/src/include/cpu/amd/msr.h@41 PS20, Line 41: #define PS_CMD_MASK_OFF 0xfffffff8 /* P-state Control Register CMD Mask OFF */ line over 80 characters https://review.coreboot.org/#/c/29065/20/src/include/cpu/amd/msr.h@43 PS20, Line 43: #define PS_MAX_REG 0xC0010068 /* Maximum P-State Register */ line over 80 characters https://review.coreboot.org/#/c/29065/20/src/include/cpu/amd/msr.h@44 PS20, Line 44: #define PS_MIN_REG 0xC0010064 /* Mimimum P-State Register */ line over 80 characters https://review.coreboot.org/#/c/29065/20/src/northbridge/amd/amdmct/mct_ddr… File src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c: https://review.coreboot.org/#/c/29065/20/src/northbridge/amd/amdmct/mct_ddr… PS20, Line 672: wrmsr(HWCR_MSR, msr); /* Setting wrap32dis allows 64-bit memory references in real mode */ line over 80 characters -- To view, visit https://review.coreboot.org/29065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Gerrit-Change-Number: 29065 Gerrit-PatchSet: 20 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Comment-Date: Wed, 17 Oct 2018 09:54:25 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src: Remove unneeded whitespace before and after parenthesis
by build bot (Jenkins) (Code Review) 17 Oct '18

17 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29161 ) Change subject: src: Remove unneeded whitespace before and after parenthesis ...................................................................... Patch Set 2: (147 comments) https://review.coreboot.org/#/c/29161/2/src/cpu/amd/family_10h-family_15h/f… File src/cpu/amd/family_10h-family_15h/fidvid.c: https://review.coreboot.org/#/c/29161/2/src/cpu/amd/family_10h-family_15h/f… PS2, Line 173: if (nbPState){ space required before the open brace '{' https://review.coreboot.org/#/c/29161/2/src/cpu/amd/family_10h-family_15h/f… PS2, Line 178: if (msr.hi & PS_EN_MASK) { suspect code indent for conditional statements (32, 32) https://review.coreboot.org/#/c/29161/2/src/cpu/amd/family_10h-family_15h/f… PS2, Line 383: if (AMD_CpuFindCapability(node, 0, &offset)) { suspect code indent for conditional statements (8, 10) https://review.coreboot.org/#/c/29161/2/src/cpu/amd/family_10h-family_15h/f… PS2, Line 415: for (j=0; (j<4) && (!isocEn); j++) { spaces required around that '=' (ctx:VxV) https://review.coreboot.org/#/c/29161/2/src/cpu/amd/family_10h-family_15h/f… PS2, Line 415: for (j=0; (j<4) && (!isocEn); j++) { spaces required around that '<' (ctx:VxV) https://review.coreboot.org/#/c/29161/2/src/cpu/amd/family_10h-family_15h/f… PS2, Line 498: if (cpuRev & (AMD_DA_Cx | AMD_RB_C3)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/2/src/cpu/amd/family_10h-family_15h/f… PS2, Line 503: if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/2/src/cpu/amd/family_10h-family_15h/f… PS2, Line 666: if ((((u32)0xffffffff) - initial_msr.lo) < corrected_timeout) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/2/src/cpu/amd/family_10h-family_15h/f… PS2, Line 675: || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo)); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/cpu/amd/family_10h-family_15h/f… PS2, Line 676: } while ((pstate_msr.lo != target_pstate) && (! timedout)); space prohibited after that '!' (ctx:BxW) https://review.coreboot.org/#/c/29161/2/src/cpu/amd/family_10h-family_15h/f… PS2, Line 685: } while (pstate_msr.lo != target_pstate ); space prohibited before that close parenthesis ')' https://review.coreboot.org/#/c/29161/2/src/cpu/amd/family_10h-family_15h/f… PS2, Line 842: vid_max = (reg1fc & SINGLE_PLANE_NB_VID_MASK) >> SINGLE_PLANE_NB_VID_SHIFT; line over 80 characters https://review.coreboot.org/#/c/29161/2/src/cpu/amd/family_10h-family_15h/f… PS2, Line 843: fid_max = (reg1fc & SINGLE_PLANE_NB_FID_MASK) >> SINGLE_PLANE_NB_FID_SHIFT; line over 80 characters https://review.coreboot.org/#/c/29161/2/src/cpu/amd/family_10h-family_15h/f… PS2, Line 846: vid_max = vid_max - ((reg1fc & DUAL_PLANE_NB_VID_OFF_MASK) >> DUAL_PLANE_NB_VID_SHIFT); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/cpu/amd/family_10h-family_15h/f… PS2, Line 847: fid_max = fid_max + ((reg1fc & DUAL_PLANE_NB_FID_OFF_MASK) >> DUAL_PLANE_NB_FID_SHIFT); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/cpu/amd/family_10h-family_15h/f… PS2, Line 951: if ( (msr.hi & PS_IDD_VALUE_MASK) space prohibited after that open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/cpu/amd/family_10h-family_15h/p… File src/cpu/amd/family_10h-family_15h/powernow_acpi.c: https://review.coreboot.org/#/c/29161/2/src/cpu/amd/family_10h-family_15h/p… PS2, Line 229: * Based on the CPU socket type, cmp_cap and pwr_lmt, get the power limit. line over 80 characters https://review.coreboot.org/#/c/29161/2/src/cpu/via/nano/nano_init.c File src/cpu/via/nano/nano_init.c: https://review.coreboot.org/#/c/29161/2/src/cpu/via/nano/nano_init.c@120 PS2, Line 120: u8 stepping = (cpuid_eax(0x1)) &0xf; need consistent spacing around '&' (ctx:WxV) https://review.coreboot.org/#/c/29161/2/src/cpu/via/nano/nano_init.c@125 PS2, Line 125: msr.lo |= ((1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */ line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/db-ft3b-lc/BiosCa… File src/mainboard/amd/db-ft3b-lc/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/db-ft3b-lc/BiosCa… PS2, Line 145: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/lamar/BiosCallOut… File src/mainboard/amd/lamar/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/lamar/BiosCallOut… PS2, Line 162: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/olivehill/BiosCal… File src/mainboard/amd/olivehill/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/olivehill/BiosCal… PS2, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/olivehillplus/Bio… File src/mainboard/amd/olivehillplus/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/olivehillplus/Bio… PS2, Line 128: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/parmer/BiosCallOu… File src/mainboard/amd/parmer/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/parmer/BiosCallOu… PS2, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/serengeti_cheetah… File src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/serengeti_cheetah… PS2, Line 71: if(!(sysconf.pci1234[i] & 0x1)) continue; space required before the open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/serengeti_cheetah… PS2, Line 71: if(!(sysconf.pci1234[i] & 0x1)) continue; trailing statements should be on next line https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/serengeti_cheetah… PS2, Line 108: current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 5); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/serengeti_cheetah… PS2, Line 140: if((sysconf.pci1234[i] & 1) != 1) continue; space required before the open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/serengeti_cheetah… PS2, Line 140: if((sysconf.pci1234[i] & 1) != 1) continue; trailing statements should be on next line https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/serengeti_cheetah… File src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/serengeti_cheetah… PS2, Line 148: if(!(sysconf.pci1234[i] & 0x1)) continue; space required before the open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/serengeti_cheetah… PS2, Line 148: if(!(sysconf.pci1234[i] & 0x1)) continue; trailing statements should be on next line https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/serengeti_cheetah… File src/mainboard/amd/serengeti_cheetah_fam10/mptable.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/serengeti_cheetah… PS2, Line 71: if(!(sysconf.pci1234[i] & 0x1)) continue; space required before the open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/serengeti_cheetah… PS2, Line 71: if(!(sysconf.pci1234[i] & 0x1)) continue; trailing statements should be on next line https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/serengeti_cheetah… PS2, Line 134: if(!(sysconf.pci1234[i] & 0x1)) continue; space required before the open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/serengeti_cheetah… PS2, Line 134: if(!(sysconf.pci1234[i] & 0x1)) continue; trailing statements should be on next line https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/thatcher/BiosCall… File src/mainboard/amd/thatcher/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/thatcher/BiosCall… PS2, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/torpedo/gpio.c File src/mainboard/amd/torpedo/gpio.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/amd/torpedo/gpio.c@94 PS2, Line 94: if (BoardType == 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/2/src/mainboard/bap/ode_e20XX/BiosCal… File src/mainboard/bap/ode_e20XX/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/bap/ode_e20XX/BiosCal… PS2, Line 117: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/bap/ode_e21XX/BiosCal… File src/mainboard/bap/ode_e21XX/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/bap/ode_e21XX/BiosCal… PS2, Line 130: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/biostar/a68n_5200/Bio… File src/mainboard/biostar/a68n_5200/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/biostar/a68n_5200/Bio… PS2, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/biostar/am1ml/romstag… File src/mainboard/biostar/am1ml/romstage.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/biostar/am1ml/romstag… PS2, Line 75: it_sio_write (dev, 0x25, 0x80); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/biostar/am1ml/romstag… PS2, Line 76: it_sio_write (dev, 0x26, 0x07); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/biostar/am1ml/romstag… PS2, Line 77: it_sio_write (dev, 0x28, 0x81); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/biostar/am1ml/romstag… PS2, Line 78: it_sio_write (dev, 0x2c, 0x06); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/biostar/am1ml/romstag… PS2, Line 79: it_sio_write (dev, 0x72, 0x00); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/biostar/am1ml/romstag… PS2, Line 80: it_sio_write (dev, 0x73, 0x00); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/biostar/am1ml/romstag… PS2, Line 81: it_sio_write (dev, 0xb3, 0x01); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/biostar/am1ml/romstag… PS2, Line 82: it_sio_write (dev, 0xb8, 0x00); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/biostar/am1ml/romstag… PS2, Line 83: it_sio_write (dev, 0xc0, 0x00); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/biostar/am1ml/romstag… PS2, Line 84: it_sio_write (dev, 0xc3, 0x00); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/biostar/am1ml/romstag… PS2, Line 85: it_sio_write (dev, 0xc8, 0x00); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/biostar/am1ml/romstag… PS2, Line 86: it_sio_write (dev, 0xc9, 0x07); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/biostar/am1ml/romstag… PS2, Line 87: it_sio_write (dev, 0xcb, 0x01); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/biostar/am1ml/romstag… PS2, Line 88: it_sio_write (dev, 0xf0, 0x10); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/biostar/am1ml/romstag… PS2, Line 89: it_sio_write (dev, 0xf4, 0x27); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/biostar/am1ml/romstag… PS2, Line 90: it_sio_write (dev, 0xf8, 0x20); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/biostar/am1ml/romstag… PS2, Line 91: it_sio_write (dev, 0xf9, 0x01); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/gizmosphere/gizmo/Oem… File src/mainboard/gizmosphere/gizmo/OemCustomize.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/gizmosphere/gizmo/Oem… PS2, Line 126: HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/gizmosphere/gizmo2/Bi… File src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/gizmosphere/gizmo2/Bi… PS2, Line 114: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/hp/pavilion_m6_1035dx… File src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/hp/pavilion_m6_1035dx… PS2, Line 115: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/lenovo/g505s/BiosCall… File src/mainboard/lenovo/g505s/BiosCallOuts.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/lenovo/g505s/BiosCall… PS2, Line 115: FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */ line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/lenovo/t60/smihandler… File src/mainboard/lenovo/t60/smihandler.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/lenovo/t60/smihandler… PS2, Line 52: printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/lenovo/z61t/smihandle… File src/mainboard/lenovo/z61t/smihandler.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/lenovo/z61t/smihandle… PS2, Line 53: printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/lippert/frontrunner-a… File src/mainboard/lippert/frontrunner-af/mainboard.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/lippert/frontrunner-a… PS2, Line 68: FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/lippert/frontrunner-a… PS2, Line 69: FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/lippert/frontrunner-a… PS2, Line 72: FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/lippert/frontrunner-a… PS2, Line 74: FCH_GPIO (57) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/lippert/frontrunner-a… PS2, Line 76: FCH_GPIO (58) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/lippert/frontrunner-a… PS2, Line 77: FCH_IOMUX(96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU) line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/lippert/frontrunner-a… PS2, Line 78: FCH_IOMUX(52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/lippert/toucan-af/mai… File src/mainboard/lippert/toucan-af/mainboard.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/lippert/toucan-af/mai… PS2, Line 36: FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/lippert/toucan-af/mai… PS2, Line 37: FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/lippert/toucan-af/mai… PS2, Line 41: FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/lippert/toucan-af/mai… PS2, Line 43: FCH_GPIO (57) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/lippert/toucan-af/mai… PS2, Line 45: FCH_GPIO (58) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/msi/ms9652_fam10/get_… File src/mainboard/msi/ms9652_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/msi/ms9652_fam10/get_… PS2, Line 104: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/msi/ms9652_fam10/get_… PS2, Line 109: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/pcengines/apu1/OemCus… File src/mainboard/pcengines/apu1/OemCustomize.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/pcengines/apu1/OemCus… PS2, Line 111: HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/pcengines/apu2/mainbo… File src/mainboard/pcengines/apu2/mainboard.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/pcengines/apu2/mainbo… PS2, Line 170: pm_write16 (PM_RTC_CONTROL, pm_read16(PM_RTC_CONTROL) | (1 << 11)); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/pcengines/apu2/mainbo… PS2, Line 175: pm_write16 (PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14)); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/pcengines/apu2/mainbo… PS2, Line 175: pm_write16 (PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14)); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/2/src/mainboard/siemens/mc_tcu3/ptn34… File src/mainboard/siemens/mc_tcu3/ptn3460.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/siemens/mc_tcu3/ptn34… PS2, Line 56: if (hwilib_get_field(PF_Color_Depth,&color_depth, 1) != 1) { space required after that ',' (ctx:VxO) https://review.coreboot.org/#/c/29161/2/src/mainboard/siemens/mc_tcu3/ptn34… PS2, Line 56: if (hwilib_get_field(PF_Color_Depth,&color_depth, 1) != 1) { space required before that '&' (ctx:OxV) https://review.coreboot.org/#/c/29161/2/src/mainboard/supermicro/h8dmr_fam1… File src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/supermicro/h8dmr_fam1… PS2, Line 102: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/supermicro/h8dmr_fam1… PS2, Line 107: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/supermicro/h8qme_fam1… File src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/supermicro/h8qme_fam1… PS2, Line 108: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/supermicro/h8qme_fam1… PS2, Line 113: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/supermicro/h8qme_fam1… File src/mainboard/supermicro/h8qme_fam10/romstage.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/supermicro/h8qme_fam1… PS2, Line 115: RC03, DIMM4, DIMM6,0, 0, DIMM5, DIMM7, 0, 0, space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29161/2/src/mainboard/tyan/s2912_fam10/get_… File src/mainboard/tyan/s2912_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/2/src/mainboard/tyan/s2912_fam10/get_… PS2, Line 101: dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2, 0)); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/mainboard/tyan/s2912_fam10/get_… PS2, Line 106: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/northbridge/amd/agesa/family12/… File src/northbridge/amd/agesa/family12/dimmSpd.c: https://review.coreboot.org/#/c/29161/2/src/northbridge/amd/agesa/family12/… PS2, Line 58: ) please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/2/src/northbridge/amd/amdmct/mct/mct_… File src/northbridge/amd/amdmct/mct/mct_d.c: https://review.coreboot.org/#/c/29161/2/src/northbridge/amd/amdmct/mct/mct_… PS2, Line 1740: u8 ChipSel, Rows, Cols, Ranks,Banks, DevWidth; space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29161/2/src/northbridge/amd/pi/00730F01/dim… File src/northbridge/amd/pi/00730F01/dimmSpd.c: https://review.coreboot.org/#/c/29161/2/src/northbridge/amd/pi/00730F01/dim… PS2, Line 37: if (info->SocketId >= DIMENSION(config->spdAddrLookup )) space prohibited before that close parenthesis ')' https://review.coreboot.org/#/c/29161/2/src/northbridge/amd/pi/00730F01/dim… PS2, Line 39: if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0] )) space prohibited before that close parenthesis ')' https://review.coreboot.org/#/c/29161/2/src/northbridge/intel/e7505/debug.c File src/northbridge/intel/e7505/debug.c: https://review.coreboot.org/#/c/29161/2/src/northbridge/intel/e7505/debug.c… PS2, Line 151: if (spd_read_byte(device, 0) < 0) continue; trailing statements should be on next line https://review.coreboot.org/#/c/29161/2/src/northbridge/intel/fsp_rangeley/… File src/northbridge/intel/fsp_rangeley/northbridge.c: https://review.coreboot.org/#/c/29161/2/src/northbridge/intel/fsp_rangeley/… PS2, Line 134: ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/soc/broadcom/cygnus/ddr_init.c File src/soc/broadcom/cygnus/ddr_init.c: https://review.coreboot.org/#/c/29161/2/src/soc/broadcom/cygnus/ddr_init.c@… PS2, Line 74: reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL, (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R))); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/soc/broadcom/cygnus/ddr_init.c@… PS2, Line 78: reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL, (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ))); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/soc/broadcom/cygnus/ddr_init.c@… PS2, Line 82: reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE))); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/soc/broadcom/cygnus/ddr_init.c@… PS2, Line 85: reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, (readvalue & 0xffff800f)); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/soc/broadcom/cygnus/ddr_init.c@… PS2, Line 88: reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ))); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/soc/broadcom/cygnus/ddr_init.c@… PS2, Line 92: reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE))); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/soc/broadcom/cygnus/ddr_init.c@… PS2, Line 95: reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, (readvalue & 0xffff800f)); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/soc/broadcom/cygnus/ddr_init.c@… PS2, Line 98: reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ))); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/soc/broadcom/cygnus/ddr_init.c@… PS2, Line 146: #define SET_OVR_STEP(v) (0x30000 | ((v) & 0x3F)) /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */ line over 80 characters https://review.coreboot.org/#/c/29161/2/src/soc/broadcom/cygnus/ddr_init.c@… PS2, Line 452: reg32_write((volatile uint32_t *)DDR_DENALI_CTL_43, (1 << 17) | (1 << 24) | (1 << 25)); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/soc/broadcom/cygnus/ddr_init.c@… PS2, Line 458: if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) { line over 80 characters https://review.coreboot.org/#/c/29161/2/src/soc/broadcom/cygnus/ddr_init.c@… PS2, Line 458: if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/2/src/soc/broadcom/cygnus/ddr_init.c@… PS2, Line 464: if (j == 0 && (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) == 0) { line over 80 characters https://review.coreboot.org/#/c/29161/2/src/soc/broadcom/cygnus/ddr_init.c@… PS2, Line 968: if ((((uint32_t)reg >= DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + 0x114))) line over 80 characters https://review.coreboot.org/#/c/29161/2/src/soc/broadcom/cygnus/ddr_init.c@… PS2, Line 986: if (CONFIG_SHMOO_REUSE_MEMTEST_LENGTH > 0) { please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/2/src/soc/broadcom/cygnus/ddr_init.c@… PS2, Line 1121: for (i = 0; i < 1000; i++); please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/2/src/soc/broadcom/cygnus/ddr_init.c@… PS2, Line 1121: for (i = 0; i < 1000; i++); trailing statements should be on next line https://review.coreboot.org/#/c/29161/2/src/soc/broadcom/cygnus/ddr_init.c@… PS2, Line 1380: if (val != 0) { suspect code indent for conditional statements (16, 12) https://review.coreboot.org/#/c/29161/2/src/soc/broadcom/cygnus/phy_reg_acc… File src/soc/broadcom/cygnus/phy_reg_access.c: https://review.coreboot.org/#/c/29161/2/src/soc/broadcom/cygnus/phy_reg_acc… PS2, Line 20: data = (* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))); please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/2/src/soc/broadcom/cygnus/phy_reg_acc… PS2, Line 27: ((* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))) = data); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/soc/broadcom/cygnus/phy_reg_acc… PS2, Line 27: ((* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))) = data); please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/2/src/soc/intel/baytrail/perf_power.c File src/soc/intel/baytrail/perf_power.c: https://review.coreboot.org/#/c/29161/2/src/soc/intel/baytrail/perf_power.c… PS2, Line 224: E(CCU, 0x1c, MASK_VAL(1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en line over 80 characters https://review.coreboot.org/#/c/29161/2/src/soc/intel/fsp_baytrail/fsp/chip… File src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c: https://review.coreboot.org/#/c/29161/2/src/soc/intel/fsp_baytrail/fsp/chip… PS2, Line 325: printk(BIOS_WARNING,"Rebooting..\n"); space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29161/2/src/soc/intel/fsp_baytrail/northclu… File src/soc/intel/fsp_baytrail/northcluster.c: https://review.coreboot.org/#/c/29161/2/src/soc/intel/fsp_baytrail/northclu… PS2, Line 161: ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/agesa/hudson/ea… File src/southbridge/amd/agesa/hudson/early_setup.c: https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/agesa/hudson/ea… PS2, Line 99: outb((dword >>(8 * i)) & 0xff, BIOSRAM_DATA); need consistent spacing around '>>' (ctx:WxV) https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/amd8111/acpi.c File src/southbridge/amd/amd8111/acpi.c: https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/amd8111/acpi.c@… PS2, Line 172: outl(((on<<1)+0x10) ,(pm10_bar + 0x10)); space prohibited before that ',' (ctx:WxV) https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/amd8111/acpi.c@… PS2, Line 172: outl(((on<<1)+0x10) ,(pm10_bar + 0x10)); space required after that ',' (ctx:WxV) https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/amd8132/bridge.c File src/southbridge/amd/amd8132/bridge.c: https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/amd8132/bridge.… PS2, Line 388: if ((chip_rev == 0x11) ||(chip_rev == 0x12)) { spaces required around that '||' (ctx:WxV) https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/cimx/sb800/fan.c File src/southbridge/amd/cimx/sb800/fan.c: https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/cimx/sb800/fan.… PS2, Line 234: sb_config.Pecstruct.MSGFun89zone0MSGREG2 = (sb_chip->imc_tempin0_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/cimx/sb800/fan.… PS2, Line 238: sb_config.Pecstruct.MSGFun89zone0MSGREG6 = (sb_chip->imc_tempin0_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/cimx/sb800/fan.… PS2, Line 252: sb_config.Pecstruct.MSGFun89zone1MSGREG2 = (sb_chip->imc_tempin1_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/cimx/sb800/fan.… PS2, Line 256: sb_config.Pecstruct.MSGFun89zone1MSGREG6 = (sb_chip->imc_tempin1_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/cimx/sb800/fan.… PS2, Line 270: sb_config.Pecstruct.MSGFun89zone2MSGREG2 = (sb_chip->imc_tempin2_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/cimx/sb800/fan.… PS2, Line 274: sb_config.Pecstruct.MSGFun89zone2MSGREG6 = (sb_chip->imc_tempin2_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/cimx/sb800/fan.… PS2, Line 288: sb_config.Pecstruct.MSGFun89zone3MSGREG2 = (sb_chip->imc_tempin3_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/cimx/sb800/fan.… PS2, Line 292: sb_config.Pecstruct.MSGFun89zone3MSGREG6 = (sb_chip->imc_tempin3_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/pi/hudson/early… File src/southbridge/amd/pi/hudson/early_setup.c: https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/pi/hudson/early… PS2, Line 238: outb((dword >>(8 * i)) & 0xff, BIOSRAM_DATA); need consistent spacing around '>>' (ctx:WxV) https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/rs780/gfx.c File src/southbridge/amd/rs780/gfx.c: https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/rs780/gfx.c@250 PS2, Line 250: if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) { line over 80 characters https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/rs780/gfx.c@250 PS2, Line 250: if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/sb700/early_set… File src/southbridge/amd/sb700/early_setup.c: https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/sb700/early_set… PS2, Line 819: outb((dword >>(8 * i)) & 0xff, BIOSRAM_DATA); need consistent spacing around '>>' (ctx:WxV) https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/sb700/ramtop.c File src/southbridge/amd/sb700/ramtop.c: https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/sb700/ramtop.c@… PS2, Line 35: outb((dword >>(8 * i)) & 0xff, BIOSRAM_DATA); need consistent spacing around '>>' (ctx:WxV) https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/sb700/sata.c File src/southbridge/amd/sb700/sata.c: https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/sb700/sata.c@473 PS2, Line 473: (i % 2) ? "Slave" : "Master", i); line over 80 characters https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/sb800/early_set… File src/southbridge/amd/sb800/early_setup.c: https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/sb800/early_set… PS2, Line 636: outb((dword >>(8 * i)) & 0xff, BIOSRAM_DATA); need consistent spacing around '>>' (ctx:WxV) https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/sr5650/pcie.c File src/southbridge/amd/sr5650/pcie.c: https://review.coreboot.org/#/c/29161/2/src/southbridge/amd/sr5650/pcie.c@8… PS2, Line 809: if (!((pci_read_config32(dev, 0x6C) >> 6) & 0x01)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/2/src/southbridge/intel/bd82x6x/early… File src/southbridge/intel/bd82x6x/early_usb.c: https://review.coreboot.org/#/c/29161/2/src/southbridge/intel/bd82x6x/early… PS2, Line 38: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/2/src/southbridge/intel/fsp_bd82x6x/e… File src/southbridge/intel/fsp_bd82x6x/early_init.c: https://review.coreboot.org/#/c/29161/2/src/southbridge/intel/fsp_bd82x6x/e… PS2, Line 145: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/2/src/southbridge/intel/fsp_i89xx/ear… File src/southbridge/intel/fsp_i89xx/early_init.c: https://review.coreboot.org/#/c/29161/2/src/southbridge/intel/fsp_i89xx/ear… PS2, Line 32: pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */ line over 80 characters https://review.coreboot.org/#/c/29161/2/src/southbridge/nvidia/ck804/early_… File src/southbridge/nvidia/ck804/early_setup.c: https://review.coreboot.org/#/c/29161/2/src/southbridge/nvidia/ck804/early_… PS2, Line 258: RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE + 1, 0, 0xe4), ~(1 << 23), (1 << 23), line over 80 characters https://review.coreboot.org/#/c/29161/2/src/southbridge/ricoh/rl5c476/rl5c4… File src/southbridge/ricoh/rl5c476/rl5c476.c: https://review.coreboot.org/#/c/29161/2/src/southbridge/ricoh/rl5c476/rl5c4… PS2, Line 169: if (enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ space required before the open brace '{' https://review.coreboot.org/#/c/29161/2/src/southbridge/ricoh/rl5c476/rl5c4… PS2, Line 184: if (enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ space required before the open brace '{' https://review.coreboot.org/#/c/29161/2/src/southbridge/ricoh/rl5c476/rl5c4… PS2, Line 186: if (!(resource->flags & IORESOURCE_STORED)){ space required before the open brace '{' -- To view, visit https://review.coreboot.org/29161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Gerrit-Change-Number: 29161 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 17 Oct 2018 09:54:25 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: src: Remove unneeded whitespace before and after parenthesis
by build bot (Jenkins) (Code Review) 17 Oct '18

17 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29161 ) Change subject: src: Remove unneeded whitespace before and after parenthesis ...................................................................... Patch Set 1: (150 comments) https://review.coreboot.org/#/c/29161/1/src/cpu/amd/family_10h-family_15h/f… File src/cpu/amd/family_10h-family_15h/fidvid.c: https://review.coreboot.org/#/c/29161/1/src/cpu/amd/family_10h-family_15h/f… PS1, Line 173: if (nbPState){ space required before the open brace '{' https://review.coreboot.org/#/c/29161/1/src/cpu/amd/family_10h-family_15h/f… PS1, Line 178: if (msr.hi & PS_EN_MASK) { suspect code indent for conditional statements (32, 32) https://review.coreboot.org/#/c/29161/1/src/cpu/amd/family_10h-family_15h/f… PS1, Line 383: if (AMD_CpuFindCapability(node, 0, &offset)) { suspect code indent for conditional statements (8, 10) https://review.coreboot.org/#/c/29161/1/src/cpu/amd/family_10h-family_15h/f… PS1, Line 415: for (j=0; (j<4) && (!isocEn); j++) { spaces required around that '=' (ctx:VxV) https://review.coreboot.org/#/c/29161/1/src/cpu/amd/family_10h-family_15h/f… PS1, Line 415: for (j=0; (j<4) && (!isocEn); j++) { spaces required around that '<' (ctx:VxV) https://review.coreboot.org/#/c/29161/1/src/cpu/amd/family_10h-family_15h/f… PS1, Line 498: if (cpuRev & (AMD_DA_Cx | AMD_RB_C3)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/1/src/cpu/amd/family_10h-family_15h/f… PS1, Line 503: if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/1/src/cpu/amd/family_10h-family_15h/f… PS1, Line 666: if ((((u32)0xffffffff) - initial_msr.lo) < corrected_timeout) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/1/src/cpu/amd/family_10h-family_15h/f… PS1, Line 675: || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo)); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/cpu/amd/family_10h-family_15h/f… PS1, Line 676: } while ((pstate_msr.lo != target_pstate) && (! timedout)); space prohibited after that '!' (ctx:BxW) https://review.coreboot.org/#/c/29161/1/src/cpu/amd/family_10h-family_15h/f… PS1, Line 685: } while (pstate_msr.lo != target_pstate ); space prohibited before that close parenthesis ')' https://review.coreboot.org/#/c/29161/1/src/cpu/amd/family_10h-family_15h/f… PS1, Line 842: vid_max = (reg1fc & SINGLE_PLANE_NB_VID_MASK) >> SINGLE_PLANE_NB_VID_SHIFT; line over 80 characters https://review.coreboot.org/#/c/29161/1/src/cpu/amd/family_10h-family_15h/f… PS1, Line 843: fid_max = (reg1fc & SINGLE_PLANE_NB_FID_MASK) >> SINGLE_PLANE_NB_FID_SHIFT; line over 80 characters https://review.coreboot.org/#/c/29161/1/src/cpu/amd/family_10h-family_15h/f… PS1, Line 846: vid_max = vid_max - ((reg1fc & DUAL_PLANE_NB_VID_OFF_MASK) >> DUAL_PLANE_NB_VID_SHIFT); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/cpu/amd/family_10h-family_15h/f… PS1, Line 847: fid_max = fid_max + ((reg1fc & DUAL_PLANE_NB_FID_OFF_MASK) >> DUAL_PLANE_NB_FID_SHIFT); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/cpu/amd/family_10h-family_15h/f… PS1, Line 951: if ( (msr.hi & PS_IDD_VALUE_MASK) space prohibited after that open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/cpu/via/nano/nano_init.c File src/cpu/via/nano/nano_init.c: https://review.coreboot.org/#/c/29161/1/src/cpu/via/nano/nano_init.c@120 PS1, Line 120: u8 stepping = (cpuid_eax(0x1)) &0xf; need consistent spacing around '&' (ctx:WxV) https://review.coreboot.org/#/c/29161/1/src/cpu/via/nano/nano_init.c@125 PS1, Line 125: msr.lo |= ((1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */ line over 80 characters https://review.coreboot.org/#/c/29161/1/src/mainboard/amd/serengeti_cheetah… File src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c: https://review.coreboot.org/#/c/29161/1/src/mainboard/amd/serengeti_cheetah… PS1, Line 71: if(!(sysconf.pci1234[i] & 0x1)) continue; space required before the open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/amd/serengeti_cheetah… PS1, Line 71: if(!(sysconf.pci1234[i] & 0x1)) continue; trailing statements should be on next line https://review.coreboot.org/#/c/29161/1/src/mainboard/amd/serengeti_cheetah… PS1, Line 108: current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 5); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/mainboard/amd/serengeti_cheetah… PS1, Line 140: if((sysconf.pci1234[i] & 1) != 1) continue; space required before the open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/amd/serengeti_cheetah… PS1, Line 140: if((sysconf.pci1234[i] & 1) != 1) continue; trailing statements should be on next line https://review.coreboot.org/#/c/29161/1/src/mainboard/amd/serengeti_cheetah… File src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/1/src/mainboard/amd/serengeti_cheetah… PS1, Line 148: if(!(sysconf.pci1234[i] & 0x1)) continue; space required before the open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/amd/serengeti_cheetah… PS1, Line 148: if(!(sysconf.pci1234[i] & 0x1)) continue; trailing statements should be on next line https://review.coreboot.org/#/c/29161/1/src/mainboard/amd/serengeti_cheetah… File src/mainboard/amd/serengeti_cheetah_fam10/mptable.c: https://review.coreboot.org/#/c/29161/1/src/mainboard/amd/serengeti_cheetah… PS1, Line 71: if(!(sysconf.pci1234[i] & 0x1)) continue; space required before the open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/amd/serengeti_cheetah… PS1, Line 71: if(!(sysconf.pci1234[i] & 0x1)) continue; trailing statements should be on next line https://review.coreboot.org/#/c/29161/1/src/mainboard/amd/serengeti_cheetah… PS1, Line 134: if(!(sysconf.pci1234[i] & 0x1)) continue; space required before the open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/amd/serengeti_cheetah… PS1, Line 134: if(!(sysconf.pci1234[i] & 0x1)) continue; trailing statements should be on next line https://review.coreboot.org/#/c/29161/1/src/mainboard/amd/torpedo/gpio.c File src/mainboard/amd/torpedo/gpio.c: https://review.coreboot.org/#/c/29161/1/src/mainboard/amd/torpedo/gpio.c@94 PS1, Line 94: if (BoardType == 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… File src/mainboard/biostar/am1ml/romstage.c: https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 62: it_sio_write(dev, 0xf1 , 0x40); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 63: it_sio_write(dev, 0xf4 , 0x80); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 64: it_sio_write(dev, 0xf5 , 0x00); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 65: it_sio_write(dev, 0xf6 , 0xf0); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 66: it_sio_write(dev, 0xf9 , 0x48); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 67: it_sio_write(dev, 0xfa , 0x00); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 68: it_sio_write(dev, 0xfb , 0x00); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 75: it_sio_write (dev, 0x25 , 0x80); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 75: it_sio_write (dev, 0x25 , 0x80); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 76: it_sio_write (dev, 0x26 , 0x07); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 76: it_sio_write (dev, 0x26 , 0x07); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 77: it_sio_write (dev, 0x28 , 0x81); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 77: it_sio_write (dev, 0x28 , 0x81); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 78: it_sio_write (dev, 0x2c , 0x06); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 78: it_sio_write (dev, 0x2c , 0x06); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 79: it_sio_write (dev, 0x72 , 0x00); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 79: it_sio_write (dev, 0x72 , 0x00); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 80: it_sio_write (dev, 0x73 , 0x00); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 80: it_sio_write (dev, 0x73 , 0x00); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 81: it_sio_write (dev, 0xb3 , 0x01); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 81: it_sio_write (dev, 0xb3 , 0x01); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 82: it_sio_write (dev, 0xb8 , 0x00); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 82: it_sio_write (dev, 0xb8 , 0x00); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 83: it_sio_write (dev, 0xc0 , 0x00); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 83: it_sio_write (dev, 0xc0 , 0x00); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 84: it_sio_write (dev, 0xc3 , 0x00); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 84: it_sio_write (dev, 0xc3 , 0x00); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 85: it_sio_write (dev, 0xc8 , 0x00); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 85: it_sio_write (dev, 0xc8 , 0x00); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 86: it_sio_write (dev, 0xc9 , 0x07); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 86: it_sio_write (dev, 0xc9 , 0x07); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 87: it_sio_write (dev, 0xcb , 0x01); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 87: it_sio_write (dev, 0xcb , 0x01); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 88: it_sio_write (dev, 0xf0 , 0x10); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 88: it_sio_write (dev, 0xf0 , 0x10); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 89: it_sio_write (dev, 0xf4 , 0x27); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 89: it_sio_write (dev, 0xf4 , 0x27); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 90: it_sio_write (dev, 0xf8 , 0x20); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 90: it_sio_write (dev, 0xf8 , 0x20); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 91: it_sio_write (dev, 0xf9 , 0x01); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/biostar/am1ml/romstag… PS1, Line 91: it_sio_write (dev, 0xf9 , 0x01); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/mainboard/gizmosphere/gizmo/Oem… File src/mainboard/gizmosphere/gizmo/OemCustomize.c: https://review.coreboot.org/#/c/29161/1/src/mainboard/gizmosphere/gizmo/Oem… PS1, Line 126: HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), line over 80 characters https://review.coreboot.org/#/c/29161/1/src/mainboard/lenovo/t60/smihandler… File src/mainboard/lenovo/t60/smihandler.c: https://review.coreboot.org/#/c/29161/1/src/mainboard/lenovo/t60/smihandler… PS1, Line 52: printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/mainboard/lenovo/z61t/smihandle… File src/mainboard/lenovo/z61t/smihandler.c: https://review.coreboot.org/#/c/29161/1/src/mainboard/lenovo/z61t/smihandle… PS1, Line 53: printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, line over 80 characters https://review.coreboot.org/#/c/29161/1/src/mainboard/lippert/frontrunner-a… File src/mainboard/lippert/frontrunner-af/mainboard.c: https://review.coreboot.org/#/c/29161/1/src/mainboard/lippert/frontrunner-a… PS1, Line 68: FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices line over 80 characters https://review.coreboot.org/#/c/29161/1/src/mainboard/lippert/frontrunner-a… PS1, Line 69: FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/lippert/frontrunner-a… PS1, Line 72: FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/lippert/frontrunner-a… PS1, Line 74: FCH_GPIO (57) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/lippert/frontrunner-a… PS1, Line 76: FCH_GPIO (58) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/lippert/frontrunner-a… PS1, Line 77: FCH_IOMUX(96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU) line over 80 characters https://review.coreboot.org/#/c/29161/1/src/mainboard/lippert/frontrunner-a… PS1, Line 78: FCH_IOMUX(52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector line over 80 characters https://review.coreboot.org/#/c/29161/1/src/mainboard/lippert/toucan-af/mai… File src/mainboard/lippert/toucan-af/mainboard.c: https://review.coreboot.org/#/c/29161/1/src/mainboard/lippert/toucan-af/mai… PS1, Line 36: FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices line over 80 characters https://review.coreboot.org/#/c/29161/1/src/mainboard/lippert/toucan-af/mai… PS1, Line 37: FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/lippert/toucan-af/mai… PS1, Line 41: FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/lippert/toucan-af/mai… PS1, Line 43: FCH_GPIO (57) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/lippert/toucan-af/mai… PS1, Line 45: FCH_GPIO (58) = 0x28; space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/msi/ms9652_fam10/get_… File src/mainboard/msi/ms9652_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/1/src/mainboard/msi/ms9652_fam10/get_… PS1, Line 109: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/mainboard/pcengines/apu1/OemCus… File src/mainboard/pcengines/apu1/OemCustomize.c: https://review.coreboot.org/#/c/29161/1/src/mainboard/pcengines/apu1/OemCus… PS1, Line 111: HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), line over 80 characters https://review.coreboot.org/#/c/29161/1/src/mainboard/pcengines/apu2/mainbo… File src/mainboard/pcengines/apu2/mainboard.c: https://review.coreboot.org/#/c/29161/1/src/mainboard/pcengines/apu2/mainbo… PS1, Line 170: pm_write16 (PM_RTC_CONTROL, pm_read16(PM_RTC_CONTROL) | (1 << 11)); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/pcengines/apu2/mainbo… PS1, Line 175: pm_write16 (PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14)); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/mainboard/pcengines/apu2/mainbo… PS1, Line 175: pm_write16 (PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14)); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/mainboard/supermicro/h8dmr_fam1… File src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/1/src/mainboard/supermicro/h8dmr_fam1… PS1, Line 107: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/mainboard/supermicro/h8qme_fam1… File src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/1/src/mainboard/supermicro/h8qme_fam1… PS1, Line 113: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/mainboard/tyan/s2912_fam10/get_… File src/mainboard/tyan/s2912_fam10/get_bus_conf.c: https://review.coreboot.org/#/c/29161/1/src/mainboard/tyan/s2912_fam10/get_… PS1, Line 106: printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/northbridge/amd/agesa/family12/… File src/northbridge/amd/agesa/family12/dimmSpd.c: https://review.coreboot.org/#/c/29161/1/src/northbridge/amd/agesa/family12/… PS1, Line 58: ) please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/1/src/northbridge/amd/pi/00730F01/dim… File src/northbridge/amd/pi/00730F01/dimmSpd.c: https://review.coreboot.org/#/c/29161/1/src/northbridge/amd/pi/00730F01/dim… PS1, Line 37: if (info->SocketId >= DIMENSION(config->spdAddrLookup )) space prohibited before that close parenthesis ')' https://review.coreboot.org/#/c/29161/1/src/northbridge/amd/pi/00730F01/dim… PS1, Line 39: if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0] )) space prohibited before that close parenthesis ')' https://review.coreboot.org/#/c/29161/1/src/northbridge/intel/e7505/debug.c File src/northbridge/intel/e7505/debug.c: https://review.coreboot.org/#/c/29161/1/src/northbridge/intel/e7505/debug.c… PS1, Line 151: if (spd_read_byte(device, 0) < 0) continue; trailing statements should be on next line https://review.coreboot.org/#/c/29161/1/src/northbridge/intel/fsp_rangeley/… File src/northbridge/intel/fsp_rangeley/northbridge.c: https://review.coreboot.org/#/c/29161/1/src/northbridge/intel/fsp_rangeley/… PS1, Line 134: ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c File src/soc/broadcom/cygnus/ddr_init.c: https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 74: reg32_write ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL, (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R))); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 74: reg32_write ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL, (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R))); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 78: reg32_write ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL, (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ))); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 78: reg32_write ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL, (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ))); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 82: reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE))); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 82: reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE))); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 85: reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, (readvalue & 0xffff800f)); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 85: reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, (readvalue & 0xffff800f)); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 88: reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ))); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 88: reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ))); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 92: reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE))); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 92: reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE))); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 95: reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, (readvalue & 0xffff800f)); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 95: reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, (readvalue & 0xffff800f)); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 98: reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ))); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 98: reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ))); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 146: #define SET_OVR_STEP(v) (0x30000 | ((v) & 0x3F)) /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */ line over 80 characters https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 449: reg32_clear_bits((volatile uint32_t *)DDR_DENALI_CTL_89 , 1 << 18); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 452: reg32_write((volatile uint32_t *)DDR_DENALI_CTL_43 , (1 << 17) | (1 << 24) | (1 << 25)); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 452: reg32_write((volatile uint32_t *)DDR_DENALI_CTL_43 , (1 << 17) | (1 << 24) | (1 << 25)); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 455: reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_43 , 1 << 25); space prohibited before that ',' (ctx:WxW) https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 458: if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) { line over 80 characters https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 458: if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 464: if (j == 0 && (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) == 0) { line over 80 characters https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 968: if ((((uint32_t)reg >= DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + 0x114))) line over 80 characters https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 986: if (CONFIG_SHMOO_REUSE_MEMTEST_LENGTH > 0) { please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 1121: for (i = 0; i < 1000; i++); please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 1121: for (i = 0; i < 1000; i++); trailing statements should be on next line https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/ddr_init.c@… PS1, Line 1380: if (val != 0) { suspect code indent for conditional statements (16, 12) https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/phy_reg_acc… File src/soc/broadcom/cygnus/phy_reg_access.c: https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/phy_reg_acc… PS1, Line 20: data = (* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))); please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/phy_reg_acc… PS1, Line 27: ((* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))) = data); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/soc/broadcom/cygnus/phy_reg_acc… PS1, Line 27: ((* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))) = data); please, no spaces at the start of a line https://review.coreboot.org/#/c/29161/1/src/soc/intel/baytrail/perf_power.c File src/soc/intel/baytrail/perf_power.c: https://review.coreboot.org/#/c/29161/1/src/soc/intel/baytrail/perf_power.c… PS1, Line 224: E(CCU, 0x1c, MASK_VAL(1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en line over 80 characters https://review.coreboot.org/#/c/29161/1/src/soc/intel/fsp_baytrail/fsp/chip… File src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c: https://review.coreboot.org/#/c/29161/1/src/soc/intel/fsp_baytrail/fsp/chip… PS1, Line 325: printk(BIOS_WARNING,"Rebooting..\n"); space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/29161/1/src/soc/intel/fsp_baytrail/northclu… File src/soc/intel/fsp_baytrail/northcluster.c: https://review.coreboot.org/#/c/29161/1/src/soc/intel/fsp_baytrail/northclu… PS1, Line 161: ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/southbridge/amd/amd8132/bridge.c File src/southbridge/amd/amd8132/bridge.c: https://review.coreboot.org/#/c/29161/1/src/southbridge/amd/amd8132/bridge.… PS1, Line 388: if ((chip_rev == 0x11) ||(chip_rev == 0x12)) { spaces required around that '||' (ctx:WxV) https://review.coreboot.org/#/c/29161/1/src/southbridge/amd/cimx/sb800/fan.c File src/southbridge/amd/cimx/sb800/fan.c: https://review.coreboot.org/#/c/29161/1/src/southbridge/amd/cimx/sb800/fan.… PS1, Line 234: sb_config.Pecstruct.MSGFun89zone0MSGREG2 = (sb_chip->imc_tempin0_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/southbridge/amd/cimx/sb800/fan.… PS1, Line 238: sb_config.Pecstruct.MSGFun89zone0MSGREG6 = (sb_chip->imc_tempin0_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/southbridge/amd/cimx/sb800/fan.… PS1, Line 252: sb_config.Pecstruct.MSGFun89zone1MSGREG2 = (sb_chip->imc_tempin1_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/southbridge/amd/cimx/sb800/fan.… PS1, Line 256: sb_config.Pecstruct.MSGFun89zone1MSGREG6 = (sb_chip->imc_tempin1_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/southbridge/amd/cimx/sb800/fan.… PS1, Line 270: sb_config.Pecstruct.MSGFun89zone2MSGREG2 = (sb_chip->imc_tempin2_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/southbridge/amd/cimx/sb800/fan.… PS1, Line 274: sb_config.Pecstruct.MSGFun89zone2MSGREG6 = (sb_chip->imc_tempin2_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/southbridge/amd/cimx/sb800/fan.… PS1, Line 288: sb_config.Pecstruct.MSGFun89zone3MSGREG2 = (sb_chip->imc_tempin3_at & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/southbridge/amd/cimx/sb800/fan.… PS1, Line 292: sb_config.Pecstruct.MSGFun89zone3MSGREG6 = (sb_chip->imc_tempin3_ct & 0xff); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/southbridge/amd/rs780/gfx.c File src/southbridge/amd/rs780/gfx.c: https://review.coreboot.org/#/c/29161/1/src/southbridge/amd/rs780/gfx.c@250 PS1, Line 250: if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) { line over 80 characters https://review.coreboot.org/#/c/29161/1/src/southbridge/amd/rs780/gfx.c@250 PS1, Line 250: if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/1/src/southbridge/amd/sb700/sata.c File src/southbridge/amd/sb700/sata.c: https://review.coreboot.org/#/c/29161/1/src/southbridge/amd/sb700/sata.c@473 PS1, Line 473: (i % 2) ? "Slave" : "Master", i); line over 80 characters https://review.coreboot.org/#/c/29161/1/src/southbridge/amd/sr5650/pcie.c File src/southbridge/amd/sr5650/pcie.c: https://review.coreboot.org/#/c/29161/1/src/southbridge/amd/sr5650/pcie.c@8… PS1, Line 809: if (!((pci_read_config32(dev, 0x6C) >> 6) & 0x01)) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/29161/1/src/southbridge/ricoh/rl5c476/rl5c4… File src/southbridge/ricoh/rl5c476/rl5c476.c: https://review.coreboot.org/#/c/29161/1/src/southbridge/ricoh/rl5c476/rl5c4… PS1, Line 169: if (enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ space required before the open brace '{' https://review.coreboot.org/#/c/29161/1/src/southbridge/ricoh/rl5c476/rl5c4… PS1, Line 184: if (enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ space required before the open brace '{' https://review.coreboot.org/#/c/29161/1/src/southbridge/ricoh/rl5c476/rl5c4… PS1, Line 186: if (!(resource->flags & IORESOURCE_STORED)){ space required before the open brace '{' -- To view, visit https://review.coreboot.org/29161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Gerrit-Change-Number: 29161 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 17 Oct 2018 08:59:57 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: cpu/amd: Use common AMD's MSR
by build bot (Jenkins) (Code Review) 17 Oct '18

17 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29065 ) Change subject: cpu/amd: Use common AMD's MSR ...................................................................... Patch Set 19: (8 comments) https://review.coreboot.org/#/c/29065/19/src/cpu/amd/family_10h-family_15h/… File src/cpu/amd/family_10h-family_15h/defaults.h: https://review.coreboot.org/#/c/29065/19/src/cpu/amd/family_10h-family_15h/… PS19, Line 77: { NB_CFG_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC | AMD_PTYPE_MC, line over 80 characters https://review.coreboot.org/#/c/29065/19/src/cpu/amd/family_10h-family_15h/… PS19, Line 107: 1 << 21, 0x00000000 }, /* Erratum #254 DR B1 BU_CFG_MSR[21]=1 */ line over 80 characters https://review.coreboot.org/#/c/29065/19/src/cpu/amd/family_10h-family_15h/… PS19, Line 118: { CPU_ID_FEATURES_MSR, (AMD_FAM10_ALL | AMD_FAM15_ALL), AMD_PTYPE_DC | AMD_PTYPE_MC, line over 80 characters https://review.coreboot.org/#/c/29065/19/src/include/cpu/amd/msr.h File src/include/cpu/amd/msr.h: https://review.coreboot.org/#/c/29065/19/src/include/cpu/amd/msr.h@40 PS19, Line 40: #define PS_CTL_REG 0xC0010062 /* P-state Control Register */ line over 80 characters https://review.coreboot.org/#/c/29065/19/src/include/cpu/amd/msr.h@41 PS19, Line 41: #define PS_CMD_MASK_OFF 0xfffffff8 /* P-state Control Register CMD Mask OFF */ line over 80 characters https://review.coreboot.org/#/c/29065/19/src/include/cpu/amd/msr.h@43 PS19, Line 43: #define PS_MAX_REG 0xC0010068 /* Maximum P-State Register */ line over 80 characters https://review.coreboot.org/#/c/29065/19/src/include/cpu/amd/msr.h@44 PS19, Line 44: #define PS_MIN_REG 0xC0010064 /* Mimimum P-State Register */ line over 80 characters https://review.coreboot.org/#/c/29065/19/src/northbridge/amd/amdmct/mct_ddr… File src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c: https://review.coreboot.org/#/c/29065/19/src/northbridge/amd/amdmct/mct_ddr… PS19, Line 672: wrmsr(HWCR_MSR, msr); /* Setting wrap32dis allows 64-bit memory references in real mode */ line over 80 characters -- To view, visit https://review.coreboot.org/29065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Gerrit-Change-Number: 29065 Gerrit-PatchSet: 19 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Comment-Date: Wed, 17 Oct 2018 08:58:45 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: src: Remove unneeded whitespace before and after parenthesis
by Elyes HAOUAS (Code Review) 17 Oct '18

17 Oct '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29161 Change subject: src: Remove unneeded whitespace before and after parenthesis ...................................................................... src: Remove unneeded whitespace before and after parenthesis Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/commonlib/storage/storage_write.c M src/cpu/amd/family_10h-family_15h/fidvid.c M src/cpu/via/nano/nano_init.c M src/cpu/via/nano/update_ucode.c M src/device/device.c M src/device/hypertransport.c M src/drivers/emulation/qemu/bochs.c M src/drivers/intel/fsp1_0/hob.c M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/intel/fsp2_0/hob_display.c M src/drivers/intel/gma/edid.c M src/drivers/intel/wifi/wifi.c M src/drivers/net/ne2k.c M src/drivers/smmstore/store.c M src/drivers/spi/flashconsole.c M src/lib/edid.c M src/lib/stack.c M src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c M src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c M src/mainboard/amd/serengeti_cheetah_fam10/mptable.c M src/mainboard/amd/torpedo/gpio.c M src/mainboard/asus/am1i-a/BiosCallOuts.c M src/mainboard/asus/m4a785-m/mainboard.c M src/mainboard/biostar/am1ml/romstage.c M src/mainboard/esd/atom15/romstage.c M src/mainboard/gigabyte/ma785gmt/mainboard.c M src/mainboard/gizmosphere/gizmo/OemCustomize.c M src/mainboard/google/gru/boardid.c M src/mainboard/google/link/i915.c M src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c M src/mainboard/intel/bayleybay_fsp/romstage.c M src/mainboard/lenovo/g505s/buildOpts.c M src/mainboard/lenovo/t60/smihandler.c M src/mainboard/lenovo/z61t/smihandler.c M src/mainboard/lippert/frontrunner-af/mainboard.c M src/mainboard/lippert/toucan-af/mainboard.c M src/mainboard/msi/ms9652_fam10/get_bus_conf.c M src/mainboard/pcengines/alix1c/romstage.c M src/mainboard/pcengines/alix2d/romstage.c M src/mainboard/pcengines/apu1/OemCustomize.c M src/mainboard/pcengines/apu1/gpio_ftns.c M src/mainboard/pcengines/apu2/BiosCallOuts.c M src/mainboard/pcengines/apu2/mainboard.c M src/mainboard/siemens/mc_tcu3/romstage.c M src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c M src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c M src/mainboard/tyan/s2912_fam10/get_bus_conf.c M src/northbridge/amd/agesa/family12/dimmSpd.c M src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c M src/northbridge/amd/pi/00730F01/dimmSpd.c M src/northbridge/intel/e7505/debug.c M src/northbridge/intel/fsp_rangeley/northbridge.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/via/vx900/chrome9hd.c M src/soc/broadcom/cygnus/ddr_init.c M src/soc/broadcom/cygnus/phy_reg_access.c M src/soc/intel/baytrail/perf_power.c M src/soc/intel/braswell/chip.c M src/soc/intel/braswell/cpu.c M src/soc/intel/braswell/emmc.c M src/soc/intel/braswell/gfx.c M src/soc/intel/braswell/lpe.c M src/soc/intel/braswell/lpss.c M src/soc/intel/braswell/pcie.c M src/soc/intel/braswell/sata.c M src/soc/intel/braswell/scc.c M src/soc/intel/braswell/sd.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/fsp_baytrail/bootblock/bootblock.c M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c M src/soc/intel/fsp_baytrail/northcluster.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/nvidia/tegra124/sdram_lp0.c M src/soc/nvidia/tegra210/sdram_lp0.c M src/soc/samsung/exynos5250/clock.c M src/soc/samsung/exynos5420/clock.c M src/southbridge/amd/agesa/hudson/sm.c M src/southbridge/amd/amd8111/early_ctrl.c M src/southbridge/amd/amd8132/bridge.c M src/southbridge/amd/cimx/sb800/fan.c M src/southbridge/amd/rs780/early_setup.c M src/southbridge/amd/rs780/gfx.c M src/southbridge/amd/sb700/sata.c M src/southbridge/amd/sb800/sata.c M src/southbridge/amd/sb800/sm.c M src/southbridge/amd/sr5650/pcie.c M src/southbridge/intel/i82371eb/smbus.c M src/southbridge/ricoh/rl5c476/rl5c476.c M src/superio/serverengines/pilot/early_init.c M src/superio/smsc/sch4037/sch4037_early_init.c 90 files changed, 305 insertions(+), 305 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/29161/1 diff --git a/src/commonlib/storage/storage_write.c b/src/commonlib/storage/storage_write.c index ba60b41..aef8624 100644 --- a/src/commonlib/storage/storage_write.c +++ b/src/commonlib/storage/storage_write.c @@ -130,7 +130,7 @@ uint32_t *buffer = malloc(buffer_bytes); uint32_t *ptr = buffer; - for ( ; buffer_words ; buffer_words--) + for (; buffer_words ; buffer_words--) *ptr++ = fill_pattern; uint64_t todo = count; diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 0882ae5..476ef37 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -54,7 +54,7 @@ 7.- TODO (Core Performance Boost is only available in revision E cpus, and we don't seem to support those yet, at least they don't have any - constant in amddefs.h ) + constant in amddefs.h) 8.- FIXME ? Transition to min Pstate according to 2.4.2.15.3 is required by 2.4.2.6 after warm reset. But 2.4.2.15 states that it is not required @@ -144,7 +144,7 @@ // BKDG 2.4.2.8 // Fam10h revision E only, but E is apparently not supported yet, therefore untested if ((cpuid_edx(0x80000007) & CPB_MASK) - && ((cpuid_ecx(0x80000008) & NC_MASK) == 5) ) { + && ((cpuid_ecx(0x80000008) & NC_MASK) == 5)) { u32 core = get_node_core_id_x().coreid; u32 asymetricBoostThisCore = ((pci_read_config32(dev, 0x10C) >> (core*2))) & 3; msr_t msr = rdmsr(PSTATE_0_MSR); @@ -170,15 +170,15 @@ uint64_t cpuRev = mctGetLogicalCPUID(0xFF); if (cpuRev & AMD_FAM10_C3) { u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK); - if ( nbPState){ + if (nbPState){ u32 nbVid1 = (pci_read_config32(dev, 0x1F4) & NB_VID1_MASK) >> NB_VID1_SHIFT; u32 i; for (i = nbPState; i < NM_PS_REG; i++) { msr_t msr = rdmsr(PSTATE_0_MSR + i); - if (msr.hi & PS_EN_MASK ) { + if (msr.hi & PS_EN_MASK) { msr.hi |= NB_DID_M_ON; msr.lo &= NB_VID_MASK_OFF; - msr.lo |= ( nbVid1 << NB_VID_POS); + msr.lo |= (nbVid1 << NB_VID_POS); wrmsr(PSTATE_0_MSR + i, msr); } } @@ -281,7 +281,7 @@ * voltages instead of a hardcoded 200us. * Note: his function is called only from prep_fid_change, * and that from init_cpus.c finalize_node_setup() - * (after set AMD MSRs and init ht ) + * (after set AMD MSRs and init ht) */ /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */ @@ -381,7 +381,7 @@ uint8_t link0isGen3 = 0; uint8_t offset; if (AMD_CpuFindCapability(node, 0, &offset)) { - link0isGen3 = (AMD_checkLinkType(node, offset) & HTPHY_LINKTYPE_HT3 ); + link0isGen3 = (AMD_checkLinkType(node, offset) & HTPHY_LINKTYPE_HT3); } /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package S1g3 in link Gen3 mode, but I don't know how to tell @@ -412,7 +412,7 @@ uint32_t dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1; uint32_t isocEn = 0; int j; - for (j=0; (j<4) && (!isocEn); j++ ) { + for (j=0; (j<4) && (!isocEn); j++) { u8 offset; if (AMD_CpuFindCapability(node, j, &offset)) { isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1; @@ -495,12 +495,12 @@ } /* set the rest of A0 since we're at it... */ - if (cpuRev & (AMD_DA_Cx | AMD_RB_C3 )) { + if (cpuRev & (AMD_DA_Cx | AMD_RB_C3)) { dword |= NB_PSTATE_FORCE_ON; } // else should we clear it ? - if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32) ) { + if ((procPkg == AMD_PKGTYPE_G34) || (procPkg == AMD_PKGTYPE_C32)) { dword |= BP_INS_TRI_EN_ON; } @@ -522,7 +522,7 @@ values (min latency) */ uint32_t nbPstate = pci_read_config32(dev,0x1f0) & NB_PSTATE_MASK; uint8_t nbSynPtrAdj; - if ((cpuRev & (AMD_DR_Bx | AMD_DA_Cx | AMD_FAM15_ALL) ) + if ((cpuRev & (AMD_DR_Bx | AMD_DA_Cx | AMD_FAM15_ALL)) || ((cpuRev & AMD_RB_C3) && (nbPstate != 0))) { nbSynPtrAdj = 5; } else { @@ -555,8 +555,8 @@ // or should we configure for what we'll set up later ? dword = pci_read_config32(dev, 0x58); uint32_t scrubbingCache = dword & - ( (0x1F << 16) // DCacheScrub - | (0x1F << 8) ); // L2Scrub + ((0x1F << 16) // DCacheScrub + | (0x1F << 8)); // L2Scrub if (scrubbingCache) { c1 = 0x80; } else { @@ -582,7 +582,7 @@ */ uint32_t smaf001 = 0xE6; - if (cpuRev & AMD_DR_Bx ) { + if (cpuRev & AMD_DR_Bx) { smaf001 = 0xA6; } else { #if IS_ENABLED(CONFIG_SVI_HIGH_FREQ) @@ -593,7 +593,7 @@ } uint32_t fidvidChange = 0; if (((cpuRev & AMD_DA_Cx) && (procPkg & AMD_PKGTYPE_S1gX)) - || (cpuRev & AMD_RB_C3) ) { + || (cpuRev & AMD_RB_C3)) { fidvidChange=0x0B; } dword = (0xE6 << 24) | (fidvidChange << 16) @@ -657,13 +657,13 @@ * misunderstand this... */ u32 corrected_timeout = ((pstate_msr.lo==1) - && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ? + && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON))) ? WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT; msr_t timeout; timeout.lo = initial_msr.lo + corrected_timeout; timeout.hi = initial_msr.hi; - if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) { + if ((((u32)0xffffffff) - initial_msr.lo) < corrected_timeout) { timeout.hi++; } @@ -672,8 +672,8 @@ pstate_msr = rdmsr(CUR_PSTATE_MSR); tsc_msr = rdmsr(TSC_MSR); timedout = (tsc_msr.hi > timeout.hi) - || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo )); - } while ( (pstate_msr.lo != target_pstate) && (! timedout) ); + || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo)); + } while ((pstate_msr.lo != target_pstate) && (! timedout)); if (pstate_msr.lo != target_pstate) { msr_t limit_msr = rdmsr(0xc0010061); @@ -682,7 +682,7 @@ do { // should we just go on instead ? pstate_msr = rdmsr(CUR_PSTATE_MSR); - } while ( pstate_msr.lo != target_pstate ); + } while (pstate_msr.lo != target_pstate ); } } @@ -765,7 +765,7 @@ wrmsr(PSTATE_0_MSR, msr); /* missing step 2 from BDKG , F3xDC[PstateMaxVal] = - * max(1,F3xDC[PstateMaxVal] ) because it would take + * max(1,F3xDC[PstateMaxVal]) because it would take * synchronization between cores and we don't think * PstatMaxVal is going to be 0 on cold reset anyway ? */ @@ -839,12 +839,12 @@ reg1fc = pci_read_config32(dev, 0x1FC); if (nb_cof_vid_update) { - vid_max = (reg1fc & SINGLE_PLANE_NB_VID_MASK ) >> SINGLE_PLANE_NB_VID_SHIFT; - fid_max = (reg1fc & SINGLE_PLANE_NB_FID_MASK ) >> SINGLE_PLANE_NB_FID_SHIFT; + vid_max = (reg1fc & SINGLE_PLANE_NB_VID_MASK) >> SINGLE_PLANE_NB_VID_SHIFT; + fid_max = (reg1fc & SINGLE_PLANE_NB_FID_MASK) >> SINGLE_PLANE_NB_FID_SHIFT; if (!pvimode) { /* SVI, dual power plane */ - vid_max = vid_max - ((reg1fc & DUAL_PLANE_NB_VID_OFF_MASK ) >> DUAL_PLANE_NB_VID_SHIFT ); - fid_max = fid_max + ((reg1fc & DUAL_PLANE_NB_FID_OFF_MASK ) >> DUAL_PLANE_NB_FID_SHIFT ); + vid_max = vid_max - ((reg1fc & DUAL_PLANE_NB_VID_OFF_MASK) >> DUAL_PLANE_NB_VID_SHIFT); + fid_max = fid_max + ((reg1fc & DUAL_PLANE_NB_FID_OFF_MASK) >> DUAL_PLANE_NB_FID_SHIFT); } /* write newNbVid to P-state Reg's NbVid always if NbVidUpdatedAll=1 */ fixPsNbVidBeforeWR(vid_max, coreid, dev, pvimode); @@ -948,7 +948,7 @@ for (i = 0; i < 5; i++) { msr = rdmsr(PSTATE_0_MSR + i); /* NbDid (bit 22 of P-state Reg) == 0 or NbVidUpdatedAll = 1 */ - if ( (msr.hi & PS_IDD_VALUE_MASK) + if ( (msr.hi & PS_IDD_VALUE_MASK) && (msr.hi & PS_EN_MASK) &&(((msr.lo & PS_NB_DID_MASK) == 0) || NbVidUpdatedAll)) { msr.lo &= PS_NB_VID_M_OFF; diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c index 985a3c7..2e9d0e2 100644 --- a/src/cpu/via/nano/nano_init.c +++ b/src/cpu/via/nano/nano_init.c @@ -71,7 +71,7 @@ printk(BIOS_INFO, "Voltage ID : %dx (min %dx; max %dx)\n", cur_vid, min_vid, max_vid); - if ( (cur_fid != max_fid) || (cur_vid != max_vid) ) { + if ((cur_fid != max_fid) || (cur_vid != max_vid)) { /* Set highest frequency and VID */ msr.lo = msr.hi; msr.hi = 0; @@ -101,7 +101,7 @@ * This MSR is not documented by VIA docs, other than setting these * bits */ msr = rdmsr(NANO_MYSTERIOUS_MSR); - msr.lo |= ( (1 << 7) | (1 << 4) ); + msr.lo |= ((1 << 7) | (1 << 4)); /* FIXME: Do we have a 6-bit or 7-bit VRM? * set bit [5] for 7-bit, or don't set it for 6 bit VRM * This will probably require a Kconfig option @@ -114,15 +114,15 @@ /* Enable TM3 */ msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= ( (1 << 3) | (1 << 13) ); + msr.lo |= ((1 << 3) | (1 << 13)); wrmsr(IA32_MISC_ENABLE, msr); - u8 stepping = ( cpuid_eax(0x1) ) &0xf; + u8 stepping = (cpuid_eax(0x1)) &0xf; if (stepping >= MODEL_NANO_3000_B0) { /* Hello Nano 3000. The Terminator needs a CPU upgrade */ /* Enable C1e, C2e, C3e, and C4e states */ msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= ( (1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */ + msr.lo |= ((1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */ msr.hi |= (1 << 0); /* C4e */ wrmsr(IA32_MISC_ENABLE, msr); } diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c index b8bfd7d..efabac6 100644 --- a/src/cpu/via/nano/update_ucode.c +++ b/src/cpu/via/nano/update_ucode.c @@ -43,9 +43,9 @@ static void nano_print_ucode_info(const nano_ucode_header *ucode) { printk(BIOS_SPEW, "Microcode update information:\n"); - printk(BIOS_SPEW, "Name: %8s\n", ucode->name ); + printk(BIOS_SPEW, "Name: %8s\n", ucode->name); printk(BIOS_SPEW, "Date: %u/%u/%u\n", ucode->month, - ucode->day, ucode->year ); + ucode->day, ucode->year); } static ucode_validity nano_ucode_is_valid(const nano_ucode_header *ucode) @@ -54,7 +54,7 @@ if (ucode->signature != NANO_UCODE_SIGNATURE) return NANO_UCODE_SIGNATURE_ERROR; /* The size of the head must be exactly 12 double words */ - if ( (ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE) + if ((ucode->total_size - ucode->payload_size) != NANO_UCODE_HEADER_SIZE) return NANO_UCODE_WRONG_SIZE; /* How about a checksum ? Checksum must be 0 @@ -119,7 +119,7 @@ /* We might do a lot of loops searching for the microcode updates, but * keep in mind, nano_ucode_is_valid searches for the signature before * doing anything else. */ - for ( i = 0; i < (ucode_len >> 2); /* don't increment i here */ ) + for (i = 0; i < (ucode_len >> 2); /* don't increment i here */) { ucode_update_status stat; const nano_ucode_header * ucode = (void *)(&ucode_data[i]); diff --git a/src/device/device.c b/src/device/device.c index dcbaef1..7836af1 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -123,7 +123,7 @@ struct device *dev, *child; /* Find the last child of our parent. */ - for (child = parent->children; child && child->sibling; /* */ ) + for (child = parent->children; child && child->sibling; /* */) child = child->sibling; dev = malloc(sizeof(*dev)); diff --git a/src/device/hypertransport.c b/src/device/hypertransport.c index 66ff9d2..4a4609d 100644 --- a/src/device/hypertransport.c +++ b/src/device/hypertransport.c @@ -61,7 +61,7 @@ /* Now add the device to the list of devices on the bus. */ /* Find the last child of our parent. */ - for (child = first->bus->children; child && child->sibling; ) + for (child = first->bus->children; child && child->sibling;) child = child->sibling; /* Place the chain on the list of children of their parent. */ diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index 3fcbb7c..cdd2c20 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -99,7 +99,7 @@ return; printk(BIOS_DEBUG, "QEMU VGA: bochs dispi interface found, " - "%d MiB video memory\n", mem / ( 1024 * 1024)); + "%d MiB video memory\n", mem / (1024 * 1024)); printk(BIOS_DEBUG, "QEMU VGA: framebuffer @ %x (pci bar %d)\n", addr, bar); diff --git a/src/drivers/intel/fsp1_0/hob.c b/src/drivers/intel/fsp1_0/hob.c index 9334893..9cf6f60 100644 --- a/src/drivers/intel/fsp1_0/hob.c +++ b/src/drivers/intel/fsp1_0/hob.c @@ -33,7 +33,7 @@ guid->Data4[0], guid->Data4[1], guid->Data4[2], guid->Data4[3], guid->Data4[4], guid->Data4[5], - guid->Data4[6], guid->Data4[7] ); + guid->Data4[6], guid->Data4[7]); } void print_hob_mem_attributes(void *Hobptr) diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index ee44250..4070a1f 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -139,7 +139,7 @@ { const struct hob_resource *res; - for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; + for (; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = fsp_next_hob(hob)) { if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR) @@ -202,7 +202,7 @@ if (!hob) return NULL; - for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; + for (; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = fsp_next_hob(hob)) { if (hob->type != HOB_TYPE_GUID_EXTENSION) @@ -281,7 +281,7 @@ if (!hob) return; - for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; + for (; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = fsp_next_hob(hob)) { if (hob->type != HOB_TYPE_GUID_EXTENSION) continue; diff --git a/src/drivers/intel/fsp2_0/hob_display.c b/src/drivers/intel/fsp2_0/hob_display.c index 24a340f..10c2f12 100644 --- a/src/drivers/intel/fsp2_0/hob_display.c +++ b/src/drivers/intel/fsp2_0/hob_display.c @@ -116,7 +116,7 @@ { const struct hob_header *hob = fsp_get_hob_list(); - for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; + for (; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = fsp_next_hob(hob)) { if (hob->type == HOB_TYPE_RESOURCE_DESCRIPTOR) fsp_print_resource_descriptor(hob); diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c index 13b301f..74bb6c6 100644 --- a/src/drivers/intel/gma/edid.c +++ b/src/drivers/intel/gma/edid.c @@ -46,15 +46,15 @@ wait_rdy(mmio); write32(GMBUS5_ADDR, 0); write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_INDEX - | GMBUS_CYCLE_STOP | ( 0x4 << GMBUS_BYTE_COUNT_SHIFT ) - | GMBUS_SLAVE_READ | (AT24_ADDR << 1) ); + | GMBUS_CYCLE_STOP | (0x4 << GMBUS_BYTE_COUNT_SHIFT) + | GMBUS_SLAVE_READ | (AT24_ADDR << 1)); wait_rdy(mmio); write32(GMBUS5_ADDR, 0); write32(GMBUS1_ADDR, GMBUS_SW_CLR_INT); write32(GMBUS1_ADDR, 0); wait_rdy(mmio); write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP | GMBUS_SLAVE_WRITE - | (AT24_ADDR << 1) ); + | (AT24_ADDR << 1)); wait_rdy(mmio); write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP); write32(GMBUS2_ADDR, GMBUS_INUSE); @@ -80,13 +80,13 @@ /* Ensure index bits are disabled. */ write32(GMBUS5_ADDR, 0); write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_INDEX - | (slave << 1) ); + | (slave << 1)); wait_rdy(mmio); /* Ensure index bits are disabled. */ write32(GMBUS5_ADDR, 0); write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_SLAVE_READ | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_STOP - | (edid_size << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1) ); + | (edid_size << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1)); for (i = 0; i < edid_size / 4; i++) { u32 reg32; wait_rdy(mmio); @@ -99,9 +99,9 @@ wait_rdy(mmio); write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_SLAVE_WRITE | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_STOP - | (128 << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1) ); + | (128 << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1)); wait_rdy(mmio); - write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP ); + write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP); write32(GMBUS2_ADDR, GMBUS_INUSE); printk (BIOS_SPEW, "EDID:\n"); diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index 97c97a2..e197114 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -173,7 +173,7 @@ acpigen_write_package(2); acpigen_write_dword(wgds->version); /* Emit 'Domain Type' + - * Group specific delta of power ( 6 bytes * NUM_WGDS_SAR_GROUPS ) + * Group specific delta of power (6 bytes * NUM_WGDS_SAR_GROUPS) */ package_size = sizeof(sar_limits.wgds.group) + 1; acpigen_write_package(package_size); diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c index 75f3357..e02a331 100644 --- a/src/drivers/net/ne2k.c +++ b/src/drivers/net/ne2k.c @@ -287,7 +287,7 @@ if (dev == PCI_DEV_INVALID) return 0; - pci_write_config32(dev, 0x10, eth_nic_base | 1 ); + pci_write_config32(dev, 0x10, eth_nic_base | 1); pci_write_config8(dev, 0x4, 0x1); c = inb(eth_nic_base + NE_ASIC_OFFSET + NE_RESET); diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index 67d38ee..4463bad 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -29,7 +29,7 @@ * uint8_t value[value_sz] * uint8_t active * align to 4 bytes - * )* + * )* * uint32le_t endmarker = 0xffffffff * * active needs to be set to 0x00 for the entry to be valid. This satisfies diff --git a/src/drivers/spi/flashconsole.c b/src/drivers/spi/flashconsole.c index aea6872..2626ec5 100644 --- a/src/drivers/spi/flashconsole.c +++ b/src/drivers/spi/flashconsole.c @@ -55,7 +55,7 @@ * the sector is already erased, so we would need to read * anyways to check if it's all 0xff). */ - for (i = 0; i < len && offset < size; ) { + for (i = 0; i < len && offset < size;) { // Fill the buffer on first iteration if (i == 0) { len = min(READ_BUFFER_SIZE, size - offset); diff --git a/src/lib/edid.c b/src/lib/edid.c index 37939eb..fbd8ef6 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -155,7 +155,7 @@ printk(BIOS_SPEW, " (broken)\n"); } else { printk(BIOS_SPEW, - " %dx%d @ ( %s%s%s%s%s) Hz (%s%s preferred)\n", + " %dx%d @ (%s%s%s%s%s) Hz (%s%s preferred)\n", width, height, fifty ? "50 " : "", sixty ? "60 " : "", diff --git a/src/lib/stack.c b/src/lib/stack.c index a66b6a1..ef45e2a 100644 --- a/src/lib/stack.c +++ b/src/lib/stack.c @@ -1,5 +1,5 @@ /* -This software and ancillary information (herein called SOFTWARE ) +This software and ancillary information (herein called SOFTWARE) called LinuxBIOS is made available under the terms described here. The SOFTWARE has been approved for release with associated LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c index e355aae..5f3cd82 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c @@ -49,7 +49,7 @@ res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1, - res->base, gsi_base ); + res->base, gsi_base); gsi_base+=7; } } @@ -58,7 +58,7 @@ res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2, - res->base, gsi_base ); + res->base, gsi_base); gsi_base+=7; } } @@ -68,7 +68,7 @@ for(i = 1; i < sysconf.hc_possible_num; i++) { u32 d = 0; - if(!(sysconf.pci1234[i] & 0x1) ) continue; + if(!(sysconf.pci1234[i] & 0x1)) continue; /* 8131 need to use +4 */ switch (sysconf.hcid[i]) { case 1: @@ -86,7 +86,7 @@ res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0], - res->base, gsi_base ); + res->base, gsi_base); gsi_base+=d; } } @@ -95,7 +95,7 @@ res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1], - res->base, gsi_base ); + res->base, gsi_base); gsi_base+=d; } } @@ -105,7 +105,7 @@ } } - current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *) current, 0, 0, 2, 5 ); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 5); /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */ /* 2: APIC 2 */ @@ -137,7 +137,7 @@ for(i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */ const char *file_name; - if((sysconf.pci1234[i] & 1) != 1 ) continue; + if((sysconf.pci1234[i] & 1) != 1) continue; u8 c; if(i < 7) { c = (u8) ('4' + i - 1); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c index 97a06ab..0c0e773 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c @@ -145,7 +145,7 @@ /* HT chain 1 */ j = 0; for(i = 1; i< sysconf.hc_possible_num; i++) { - if(!(sysconf.pci1234[i] & 0x1) ) continue; + if(!(sysconf.pci1234[i] & 0x1)) continue; /* check hcid type here */ sysconf.hcid[i] = get_hcid(i); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c index 0927199..f8d9021 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c @@ -68,7 +68,7 @@ j = 0; for(i = 1; i< sysconf.hc_possible_num; i++) { - if(!(sysconf.pci1234[i] & 0x1) ) continue; + if(!(sysconf.pci1234[i] & 0x1)) continue; switch(sysconf.hcid[i]) { case 1: @@ -131,7 +131,7 @@ j = 0; for(i = 1; i< sysconf.hc_possible_num; i++) { - if(!(sysconf.pci1234[i] & 0x1) ) continue; + if(!(sysconf.pci1234[i] & 0x1)) continue; int ii; int jj; struct device *dev; diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c index e26052a..da05002 100644 --- a/src/mainboard/amd/torpedo/gpio.c +++ b/src/mainboard/amd/torpedo/gpio.c @@ -91,7 +91,7 @@ Mmio8_And_Or (GpioMmioAddr, Index, 0xA3, gpio_table[Index].value); } if (Index == GPIO_65) { - if ( BoardType == 0 ) { + if (BoardType == 0) { Mmio8_And_Or (IoMuxMmioAddr, GPIO_65, 0x00, 3); // function 3 } } diff --git a/src/mainboard/asus/am1i-a/BiosCallOuts.c b/src/mainboard/asus/am1i-a/BiosCallOuts.c index 6b25d38..f70b88d 100644 --- a/src/mainboard/asus/am1i-a/BiosCallOuts.c +++ b/src/mainboard/asus/am1i-a/BiosCallOuts.c @@ -125,7 +125,7 @@ /* Read SATA controller mode from CMOS */ enum cb_err ret; ret = get_option(&FchParams_env->Sata.SataClass, "sata_mode"); - if ( ret != CB_SUCCESS) { + if (ret != CB_SUCCESS) { FchParams_env->Sata.SataClass = 0; printk(BIOS_DEBUG, "ERROR: cannot read CMOS setting, falling back to default. Error code: %x\n", (int)ret); } diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c index 00a12cc..992cfcc 100644 --- a/src/mainboard/asus/m4a785-m/mainboard.c +++ b/src/mainboard/asus/m4a785-m/mainboard.c @@ -172,7 +172,7 @@ * pm_iowrite(0x55, byte); * * byte = pm_ioread(0x67); - * byte &= ~( 1 << 6); + * byte &= ~(1 << 6); * pm_iowrite(0x67, byte); */ } diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c index 7caa4dc..3dcc6c5 100644 --- a/src/mainboard/biostar/am1ml/romstage.c +++ b/src/mainboard/biostar/am1ml/romstage.c @@ -59,36 +59,36 @@ static void ite_evc_conf(pnp_devfn_t dev) { ite_enter_conf(dev); - it_sio_write(dev, 0xf1 , 0x40 ); - it_sio_write(dev, 0xf4 , 0x80 ); - it_sio_write(dev, 0xf5 , 0x00 ); - it_sio_write(dev, 0xf6 , 0xf0 ); - it_sio_write(dev, 0xf9 , 0x48 ); - it_sio_write(dev, 0xfa , 0x00 ); - it_sio_write(dev, 0xfb , 0x00 ); + it_sio_write(dev, 0xf1 , 0x40); + it_sio_write(dev, 0xf4 , 0x80); + it_sio_write(dev, 0xf5 , 0x00); + it_sio_write(dev, 0xf6 , 0xf0); + it_sio_write(dev, 0xf9 , 0x48); + it_sio_write(dev, 0xfa , 0x00); + it_sio_write(dev, 0xfb , 0x00); ite_exit_conf(dev); } static void ite_gpio_conf(pnp_devfn_t dev) { ite_enter_conf (dev); - it_sio_write (dev, 0x25 , 0x80 ); - it_sio_write (dev, 0x26 , 0x07 ); - it_sio_write (dev, 0x28 , 0x81 ); - it_sio_write (dev, 0x2c , 0x06 ); - it_sio_write (dev, 0x72 , 0x00 ); - it_sio_write (dev, 0x73 , 0x00 ); - it_sio_write (dev, 0xb3 , 0x01 ); - it_sio_write (dev, 0xb8 , 0x00 ); - it_sio_write (dev, 0xc0 , 0x00 ); - it_sio_write (dev, 0xc3 , 0x00 ); - it_sio_write (dev, 0xc8 , 0x00 ); - it_sio_write (dev, 0xc9 , 0x07 ); - it_sio_write (dev, 0xcb , 0x01 ); - it_sio_write (dev, 0xf0 , 0x10 ); - it_sio_write (dev, 0xf4 , 0x27 ); - it_sio_write (dev, 0xf8 , 0x20 ); - it_sio_write (dev, 0xf9 , 0x01 ); + it_sio_write (dev, 0x25 , 0x80); + it_sio_write (dev, 0x26 , 0x07); + it_sio_write (dev, 0x28 , 0x81); + it_sio_write (dev, 0x2c , 0x06); + it_sio_write (dev, 0x72 , 0x00); + it_sio_write (dev, 0x73 , 0x00); + it_sio_write (dev, 0xb3 , 0x01); + it_sio_write (dev, 0xb8 , 0x00); + it_sio_write (dev, 0xc0 , 0x00); + it_sio_write (dev, 0xc3 , 0x00); + it_sio_write (dev, 0xc8 , 0x00); + it_sio_write (dev, 0xc9 , 0x07); + it_sio_write (dev, 0xcb , 0x01); + it_sio_write (dev, 0xf0 , 0x10); + it_sio_write (dev, 0xf4 , 0x27); + it_sio_write (dev, 0xf8 , 0x20); + it_sio_write (dev, 0xf9 , 0x01); ite_exit_conf (dev); } diff --git a/src/mainboard/esd/atom15/romstage.c b/src/mainboard/esd/atom15/romstage.c index 3aa02d8..c89a1e2 100644 --- a/src/mainboard/esd/atom15/romstage.c +++ b/src/mainboard/esd/atom15/romstage.c @@ -57,7 +57,7 @@ read_ssus_gpio(27), read_ssus_gpio(28), read_ssus_gpio(29), - read_ssus_gpio(30) ); + read_ssus_gpio(30)); } diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c index de90fda..a0e9631 100644 --- a/src/mainboard/gigabyte/ma785gmt/mainboard.c +++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c @@ -226,7 +226,7 @@ * pm_iowrite(0x55, byte); * * byte = pm_ioread(0x67); - * byte &= ~( 1 << 6); + * byte &= ~(1 << 6); * pm_iowrite(0x67, byte); */ } diff --git a/src/mainboard/gizmosphere/gizmo/OemCustomize.c b/src/mainboard/gizmosphere/gizmo/OemCustomize.c index c07465c..e1850d2 100644 --- a/src/mainboard/gizmosphere/gizmo/OemCustomize.c +++ b/src/mainboard/gizmosphere/gizmo/OemCustomize.c @@ -123,7 +123,7 @@ #define WLSEED 0x08 #define RXSEED 0x40 WRITE_LEVELING_SEED(ANY_SOCKET, ANY_CHANNEL, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED), - HW_RXEN_SEED( ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), + HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), PSO_END }; diff --git a/src/mainboard/google/gru/boardid.c b/src/mainboard/google/gru/boardid.c index aaa8ae7..5b2985a 100644 --- a/src/mainboard/google/gru/boardid.c +++ b/src/mainboard/google/gru/boardid.c @@ -65,7 +65,7 @@ } } - die("Read impossible value ( > 1023) from 10-bit ADC!"); + die("Read impossible value (> 1023) from 10-bit ADC!"); } uint32_t board_id(void) diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c index 8b8000c..8bd758b 100644 --- a/src/mainboard/google/link/i915.c +++ b/src/mainboard/google/link/i915.c @@ -295,7 +295,7 @@ index = run(index); auxout[0] = 1 << 31 /* dp */|0x0 << 28/*W*/|DP_LINK_BW_SET << 8|0x8; auxout[1] = 0x0a840000; - /*( DP_LINK_BW_2_7 &0xa)|0x0000840a*/ + /*(DP_LINK_BW_2_7 &0xa)|0x0000840a*/ auxout[2] = 0x00000000; auxout[3] = 0x01000000; intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 13, auxin, 0); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index ed79dad..7ab5eb1 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -365,9 +365,9 @@ #define SCI_MAP_PWRBTN 0x73 SCI_MAP_CONTROL m6_1035dx_sci_map[] = { - {GEVENT_PIN( EC_SCI_GEVENT ), EC_SCI_GPE}, - {GEVENT_PIN( EC_LID_GEVENT ), EC_LID_GPE}, - {GEVENT_PIN( PCIE_GEVENT ), PCIE_GPE}, + {GEVENT_PIN(EC_SCI_GEVENT), EC_SCI_GPE}, + {GEVENT_PIN(EC_LID_GEVENT), EC_LID_GPE}, + {GEVENT_PIN(PCIE_GEVENT), PCIE_GPE}, {SCI_MAP_OHCI_12_0, PME_GPE}, {SCI_MAP_OHCI_13_0, PME_GPE}, {SCI_MAP_XHCI_10_0, PME_GPE}, diff --git a/src/mainboard/intel/bayleybay_fsp/romstage.c b/src/mainboard/intel/bayleybay_fsp/romstage.c index d988023..199a15e 100644 --- a/src/mainboard/intel/bayleybay_fsp/romstage.c +++ b/src/mainboard/intel/bayleybay_fsp/romstage.c @@ -65,67 +65,67 @@ /* *ALC262 Verb Table - 10EC0262 */ - /* Pin Complex (NID 0x11 ) */ + /* Pin Complex (NID 0x11) */ 0x01171CF0, 0x01171D11, 0x01171E11, 0x01171F41, - /* Pin Complex (NID 0x12 ) */ + /* Pin Complex (NID 0x12) */ 0x01271CF0, 0x01271D11, 0x01271E11, 0x01271F41, - /* Pin Complex (NID 0x14 ) */ + /* Pin Complex (NID 0x14) */ 0x01471C10, 0x01471D40, 0x01471E01, 0x01471F01, - /* Pin Complex (NID 0x15 ) */ + /* Pin Complex (NID 0x15) */ 0x01571CF0, 0x01571D11, 0x01571E11, 0x01571F41, - /* Pin Complex (NID 0x16 ) */ + /* Pin Complex (NID 0x16) */ 0x01671CF0, 0x01671D11, 0x01671E11, 0x01671F41, - /* Pin Complex (NID 0x18 ) */ + /* Pin Complex (NID 0x18) */ 0x01871C20, 0x01871D98, 0x01871EA1, 0x01871F01, - /* Pin Complex (NID 0x19 ) */ + /* Pin Complex (NID 0x19) */ 0x01971C21, 0x01971D98, 0x01971EA1, 0x01971F02, - /* Pin Complex (NID 0x1A ) */ + /* Pin Complex (NID 0x1A) */ 0x01A71C2F, 0x01A71D30, 0x01A71E81, 0x01A71F01, - /* Pin Complex (NID 0x1B ) */ + /* Pin Complex (NID 0x1B) */ 0x01B71C1F, 0x01B71D40, 0x01B71E21, 0x01B71F02, - /* Pin Complex (NID 0x1C ) */ + /* Pin Complex (NID 0x1C) */ 0x01C71CF0, 0x01C71D11, 0x01C71E11, 0x01C71F41, - /* Pin Complex (NID 0x1D ) */ + /* Pin Complex (NID 0x1D) */ 0x01D71C01, 0x01D71DC6, 0x01D71E14, 0x01D71F40, - /* Pin Complex (NID 0x1E ) */ + /* Pin Complex (NID 0x1E) */ 0x01E71CF0, 0x01E71D11, 0x01E71E11, 0x01E71F41, - /* Pin Complex (NID 0x1F ) */ + /* Pin Complex (NID 0x1F) */ 0x01F71CF0, 0x01F71D11, 0x01F71E11, diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index 9ef46d5..3eaa8b0 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -365,9 +365,9 @@ #define SCI_MAP_PWRBTN 0x73 SCI_MAP_CONTROL lenovo_g505s_sci_map[] = { - {GEVENT_PIN( EC_SCI_GEVENT ), EC_SCI_GPE}, - {GEVENT_PIN( EC_LID_GEVENT ), EC_LID_GPE}, - {GEVENT_PIN( PCIE_GEVENT ), PCIE_GPE}, + {GEVENT_PIN(EC_SCI_GEVENT), EC_SCI_GPE}, + {GEVENT_PIN(EC_LID_GEVENT), EC_LID_GPE}, + {GEVENT_PIN(PCIE_GEVENT), PCIE_GPE}, {SCI_MAP_OHCI_12_0, PME_GPE}, {SCI_MAP_OHCI_13_0, PME_GPE}, {SCI_MAP_XHCI_10_0, PME_GPE}, diff --git a/src/mainboard/lenovo/t60/smihandler.c b/src/mainboard/lenovo/t60/smihandler.c index 7707d62..bccb7f1 100644 --- a/src/mainboard/lenovo/t60/smihandler.c +++ b/src/mainboard/lenovo/t60/smihandler.c @@ -49,7 +49,7 @@ { u8 *bar; if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) { - printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int )bar, *(bar+LVTMA_BL_MOD_LEVEL)); + printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); *(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f; if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0) *(bar+LVTMA_BL_MOD_LEVEL) += 0x10; diff --git a/src/mainboard/lenovo/z61t/smihandler.c b/src/mainboard/lenovo/z61t/smihandler.c index d98a809..b93f48e 100644 --- a/src/mainboard/lenovo/z61t/smihandler.c +++ b/src/mainboard/lenovo/z61t/smihandler.c @@ -50,7 +50,7 @@ { u8 *bar; if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) { - printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int )bar, + printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL)); *(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f; if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0) diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index 80810cc..4254859 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -65,19 +65,19 @@ /* Init Hudson GPIOs. */ printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE); - FCH_IOMUX( 50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices - FCH_GPIO ( 50) = 0xC0; // = output set to 1 as it's never needed + FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices + FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed FCH_IOMUX(197) = 2; // GPIO197: BIOS_DEFAULTS# = input (int. PU) - FCH_IOMUX( 56) = 1; // GPIO58-56: REV_ID2-0 - FCH_GPIO ( 56) = 0x28; // = inputs, disable int. pull-ups - FCH_IOMUX( 57) = 1; - FCH_GPIO ( 57) = 0x28; - FCH_IOMUX( 58) = 1; - FCH_GPIO ( 58) = 0x28; - FCH_IOMUX( 96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU) - FCH_IOMUX( 52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector - FCH_IOMUX( 61) = 2; // default to inputs with int. PU - FCH_IOMUX( 62) = 2; + FCH_IOMUX(56) = 1; // GPIO58-56: REV_ID2-0 + FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups + FCH_IOMUX(57) = 1; + FCH_GPIO (57) = 0x28; + FCH_IOMUX(58) = 1; + FCH_GPIO (58) = 0x28; + FCH_IOMUX(96) = 1; // "Gpio96": GEVENT0# signal on X2 connector (int. PU) + FCH_IOMUX(52) = 1; // GPIO52,61,62,187-192 free to use on X2 connector + FCH_IOMUX(61) = 2; // default to inputs with int. PU + FCH_IOMUX(62) = 2; FCH_IOMUX(187) = 2; FCH_IOMUX(188) = 2; FCH_IOMUX(189) = 1; diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index c6ab265..5168228 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -33,16 +33,16 @@ /* Init Hudson GPIOs. */ printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE); - FCH_IOMUX( 50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices - FCH_GPIO ( 50) = 0xC0; // = output set to 1 as it's never needed + FCH_IOMUX(50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices + FCH_GPIO (50) = 0xC0; // = output set to 1 as it's never needed FCH_IOMUX(197) = 2; // GPIO197: BIOS_DEFAULTS# FCH_GPIO (197) = 0x28; // = input, disable int. pull-up - FCH_IOMUX( 56) = 1; // GPIO58-56: REV_ID2-0 - FCH_GPIO ( 56) = 0x28; // = inputs, disable int. pull-ups - FCH_IOMUX( 57) = 1; - FCH_GPIO ( 57) = 0x28; - FCH_IOMUX( 58) = 1; - FCH_GPIO ( 58) = 0x28; + FCH_IOMUX(56) = 1; // GPIO58-56: REV_ID2-0 + FCH_GPIO (56) = 0x28; // = inputs, disable int. pull-ups + FCH_IOMUX(57) = 1; + FCH_GPIO (57) = 0x28; + FCH_IOMUX(58) = 1; + FCH_GPIO (58) = 0x28; FCH_IOMUX(187) = 2; // GPIO187,188,166,GPO160: GPO0-3 on COM Express connector FCH_GPIO (187) = 0x08; // = outputs, disable PUs, default to 0 FCH_IOMUX(188) = 2; diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c index c5ceb75..5b7b9c0 100644 --- a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c +++ b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c @@ -106,7 +106,7 @@ m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 ); + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); } } diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index 8fe2dc0..e482840 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -44,7 +44,7 @@ * 4banks (2) * SSTL_2 (2) * 4th GEN die (C) - * Normal Power Consumption (<blank> ) + * Normal Power Consumption (<blank>) * TSOP (T) * Single Die (<blank>) * Lead Free (P) diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index da3913d..9bb9c00 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -42,7 +42,7 @@ * 4banks (2) * SSTL_2 (2) * 4th GEN die (C) - * Normal Power Consumption (<blank> ) + * Normal Power Consumption (<blank>) * TSOP (T) * Single Die (<blank>) * Lead Free (P) diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c index 330531f..9febec7 100644 --- a/src/mainboard/pcengines/apu1/OemCustomize.c +++ b/src/mainboard/pcengines/apu1/OemCustomize.c @@ -108,7 +108,7 @@ #define WLSEED 0x08 #define RXSEED 0x40 WRITE_LEVELING_SEED(ANY_SOCKET, ANY_CHANNEL, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED), - HW_RXEN_SEED( ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), + HW_RXEN_SEED(ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED), PSO_END }; diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.c b/src/mainboard/pcengines/apu1/gpio_ftns.c index 018fc0a..8942d9b 100644 --- a/src/mainboard/pcengines/apu1/gpio_ftns.c +++ b/src/mainboard/pcengines/apu1/gpio_ftns.c @@ -25,9 +25,9 @@ uintptr_t base_addr = 0; /* Find the ACPImmioAddr base address */ - for ( pm_index = 0x27; pm_index > 0x23; pm_index-- ) { - outb( pm_index, PM_INDEX ); - pm_data = inb( PM_DATA ); + for (pm_index = 0x27; pm_index > 0x23; pm_index--) { + outb(pm_index, PM_INDEX); + pm_data = inb(PM_DATA); base_addr <<= 8; base_addr |= (u32)pm_data; } diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index 8e2636b..1c7b4fd 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -99,7 +99,7 @@ FchParams->Usb.Ehci1Enable = TRUE; } - // Enable EHCI 1 ( port 4 to 7) + // Enable EHCI 1 (port 4 to 7) // port 4 and 5 to EHCI header port 6 and 7 to PCIe slot. FchParams->Usb.Ehci2Enable = TRUE; diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 9434b93..c6b9b8e 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -167,12 +167,12 @@ // // Enable the RTC output // - pm_write16 ( PM_RTC_CONTROL, pm_read16( PM_RTC_CONTROL ) | (1 << 11)); + pm_write16 (PM_RTC_CONTROL, pm_read16(PM_RTC_CONTROL) | (1 << 11)); // // Enable power on from WAKE# // - pm_write16 ( PM_S_STATE_CONTROL, pm_read16( PM_S_STATE_CONTROL ) | (1 << 14)); + pm_write16 (PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14)); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); diff --git a/src/mainboard/siemens/mc_tcu3/romstage.c b/src/mainboard/siemens/mc_tcu3/romstage.c index 628e88b..ef07f7e 100644 --- a/src/mainboard/siemens/mc_tcu3/romstage.c +++ b/src/mainboard/siemens/mc_tcu3/romstage.c @@ -66,67 +66,67 @@ /* *ALC262 Verb Table - 10EC0262 */ - /* Pin Complex (NID 0x11 ) */ + /* Pin Complex (NID 0x11) */ 0x01171CF0, 0x01171D11, 0x01171E11, 0x01171F41, - /* Pin Complex (NID 0x12 ) */ + /* Pin Complex (NID 0x12) */ 0x01271CF0, 0x01271D11, 0x01271E11, 0x01271F41, - /* Pin Complex (NID 0x14 ) */ + /* Pin Complex (NID 0x14) */ 0x01471C10, 0x01471D40, 0x01471E01, 0x01471F01, - /* Pin Complex (NID 0x15 ) */ + /* Pin Complex (NID 0x15) */ 0x01571CF0, 0x01571D11, 0x01571E11, 0x01571F41, - /* Pin Complex (NID 0x16 ) */ + /* Pin Complex (NID 0x16) */ 0x01671CF0, 0x01671D11, 0x01671E11, 0x01671F41, - /* Pin Complex (NID 0x18 ) */ + /* Pin Complex (NID 0x18) */ 0x01871C20, 0x01871D98, 0x01871EA1, 0x01871F01, - /* Pin Complex (NID 0x19 ) */ + /* Pin Complex (NID 0x19) */ 0x01971C21, 0x01971D98, 0x01971EA1, 0x01971F02, - /* Pin Complex (NID 0x1A ) */ + /* Pin Complex (NID 0x1A) */ 0x01A71C2F, 0x01A71D30, 0x01A71E81, 0x01A71F01, - /* Pin Complex (NID 0x1B ) */ + /* Pin Complex (NID 0x1B) */ 0x01B71C1F, 0x01B71D40, 0x01B71E21, 0x01B71F02, - /* Pin Complex (NID 0x1C ) */ + /* Pin Complex (NID 0x1C) */ 0x01C71CF0, 0x01C71D11, 0x01C71E11, 0x01C71F41, - /* Pin Complex (NID 0x1D ) */ + /* Pin Complex (NID 0x1D) */ 0x01D71C01, 0x01D71DC6, 0x01D71E14, 0x01D71F40, - /* Pin Complex (NID 0x1E ) */ + /* Pin Complex (NID 0x1E) */ 0x01E71CF0, 0x01E71D11, 0x01E71E11, 0x01E71F41, - /* Pin Complex (NID 0x1F ) */ + /* Pin Complex (NID 0x1F) */ 0x01F71CF0, 0x01F71D11, 0x01F71E11, diff --git a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c index b2bc0dd..1015a7a 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c @@ -104,7 +104,7 @@ m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 ); + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); } } diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c index 75b1347..5bdbe29 100644 --- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c @@ -110,7 +110,7 @@ m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 ); + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); } } diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c index 09704f8..7da31d7 100644 --- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c +++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c @@ -103,7 +103,7 @@ m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 ); + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2); } } diff --git a/src/northbridge/amd/agesa/family12/dimmSpd.c b/src/northbridge/amd/agesa/family12/dimmSpd.c index 2f0af59..a0a1aea 100644 --- a/src/northbridge/amd/agesa/family12/dimmSpd.c +++ b/src/northbridge/amd/agesa/family12/dimmSpd.c @@ -55,7 +55,7 @@ IN UINT32 Func, IN UINTN Data, IN OUT AGESA_READ_SPD_PARAMS *SpdData - ) + ) { UINT8 SmBusAddress = 0; UINTN Index; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index f62aa15..b62661b 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -684,7 +684,7 @@ {tempW = bitTestSet(tempW, 7);} if (bitTest(tempW1,18)) {tempW = bitTestSet(tempW, 6);} - /* tempW = tempW|(((tempW1 >> 20) & 0x7 )<< 3); */ + /* tempW = tempW|(((tempW1 >> 20) & 0x7)<< 3); */ tempW = tempW|((tempW1&0x00700000) >> 17); /* workaround for DR-B0 */ if ((pDCTData->LogicalCPUID & AMD_DR_Bx) && (pDCTData->Status[DCT_STATUS_REGISTERED])) diff --git a/src/northbridge/amd/pi/00730F01/dimmSpd.c b/src/northbridge/amd/pi/00730F01/dimmSpd.c index fdeefab..4df2cbd 100644 --- a/src/northbridge/amd/pi/00730F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00730F01/dimmSpd.c @@ -34,9 +34,9 @@ if ((dev == 0) || (config == 0)) return AGESA_ERROR; - if (info->SocketId >= DIMENSION(config->spdAddrLookup )) + if (info->SocketId >= DIMENSION(config->spdAddrLookup )) return AGESA_ERROR; - if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0] )) + if (info->MemChannelId >= DIMENSION(config->spdAddrLookup[0] )) return AGESA_ERROR; if (info->DimmId >= DIMENSION(config->spdAddrLookup[0][0])) return AGESA_ERROR; diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c index c085c87..da12abd 100644 --- a/src/northbridge/intel/e7505/debug.c +++ b/src/northbridge/intel/e7505/debug.c @@ -148,7 +148,7 @@ printk(BIOS_DEBUG, "\n"); for (device = 1; device < 0x80; device++) { int j; - if ( spd_read_byte(device, 0) < 0 ) continue; + if (spd_read_byte(device, 0) < 0) continue; printk(BIOS_DEBUG, "smbus: %02x", device); for (j = 0; j < 256; j++) { int status; diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 72b2761..94855cf 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -131,7 +131,7 @@ mmio_resource(dev, index++, tomlow >> 10, (bmbound - bsmmrrl) >> 10); if (bmbound_hi > 0x100000000) { - ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10 ); + ram_resource(dev, index++, 0x100000000 >> 10, (bmbound_hi - 0x100000000) >> 10); printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", (bmbound_hi - 0x100000000) >> 20); } diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 5adf865..778b2f7 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -57,13 +57,13 @@ #define DIMM_IS_POPULATED(dimms, idx) (dimms[idx].card_type != 0) #define IF_DIMM_POPULATED(dimms, idx) if (dimms[idx].card_type != 0) -#define ONLY_DIMMA_IS_POPULATED(dimms, ch) ( \ +#define ONLY_DIMMA_IS_POPULATED(dimms, ch) (\ (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ !DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3))) -#define ONLY_DIMMB_IS_POPULATED(dimms, ch) ( \ +#define ONLY_DIMMB_IS_POPULATED(dimms, ch) (\ (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3) && \ !DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2))) -#define BOTH_DIMMS_ARE_POPULATED(dimms, ch) ( \ +#define BOTH_DIMMS_ARE_POPULATED(dimms, ch) (\ (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3)))) #define FOR_EACH_DIMM(idx) \ @@ -905,11 +905,11 @@ reg32 |= ((u32) pll->dben[f][clk]) << (dqs + 9); reg32 |= ((u32) pll->dbsel[f][clk]) << dqs; MCHBAR32(0x5b4+rank*4) = (MCHBAR32(0x5b4+rank*4) & - ~( (1 << (dqs+9))|(1 << dqs) )) | reg32; + ~((1 << (dqs+9))|(1 << dqs))) | reg32; reg32 = ((u32) pll->clkdelay[f][clk]) << ((dqs*2) + 16); MCHBAR32(0x5c8+rank*4) = (MCHBAR32(0x5c8+rank*4) & - ~( (1 << (dqs*2 + 17))|(1 << (dqs*2 + 16)) )) | reg32; + ~((1 << (dqs*2 + 17))|(1 << (dqs*2 + 16)))) | reg32; reg8 = pll->pi[f][clk]; MCHBAR8(0x520+j) = (MCHBAR8(0x520+j) & ~0x3f) | reg8; @@ -930,11 +930,11 @@ reg32 |= ((u32) pll->dben[f][clk]) << (dq + 9); reg32 |= ((u32) pll->dbsel[f][clk]) << dq; MCHBAR32(0x5a4+rank*4) = (MCHBAR32(0x5a4+rank*4) & - ~( (1 << (dq+9))|(1 << dq) )) | reg32; + ~((1 << (dq+9))|(1 << dq))) | reg32; reg32 = ((u32) pll->clkdelay[f][clk]) << (dq*2); MCHBAR32(0x5c8+rank*4) = (MCHBAR32(0x5c8+rank*4) & - ~( (1 << (dq*2 + 1))|(1 << (dq*2)) )) | reg32; + ~((1 << (dq*2 + 1))|(1 << (dq*2)))) | reg32; reg8 = pll->pi[f][clk]; MCHBAR8(0x500+j) = (MCHBAR8(0x500+j) & ~0x3f) | reg8; diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c index 254be7b..494d78a 100644 --- a/src/northbridge/via/vx900/chrome9hd.c +++ b/src/northbridge/via/vx900/chrome9hd.c @@ -105,15 +105,15 @@ * 0000: 66MHz * 0001: 100MHz * 0010: 133MHz - * 0011: 200MHz ( DDR200 ) - * 0100: 266MHz ( DDR266 ) - * 0101: 333MHz ( DDR333 ) - * 0110: 400MHz ( DDR400 ) - * 0111: 533MHz ( DDR I/II 533) - * 1000: 667MHz ( DDR I/II 667) - * 1001: 800MHz ( DDR3 800) - * 1010: 1066MHz ( DDR3 1066) - * 1011: 1333MHz ( DDR3 1333) + * 0011: 200MHz (DDR200) + * 0100: 266MHz (DDR266) + * 0101: 333MHz (DDR333) + * 0110: 400MHz (DDR400) + * 0111: 533MHz (DDR I/II 533) + * 1000: 667MHz (DDR I/II 667) + * 1001: 800MHz (DDR3 800) + * 1010: 1066MHz (DDR3 1066) + * 1011: 1333MHz (DDR3 1333) * Bit[3:0] * N: Frame Buffer Size 2^N MB */ diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c index ff5dc87..ea9400e 100644 --- a/src/soc/broadcom/cygnus/ddr_init.c +++ b/src/soc/broadcom/cygnus/ddr_init.c @@ -71,31 +71,31 @@ // Disable low power receivers: bit 0 of the byte lane STATIC_PAD_CTL register readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL); - reg32_write ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL, ( readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R))); + reg32_write ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL, (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R))); // Turn off ZQ_CAL drivers: bits 0,1, and 17 of the ZQ_CAL register (other bits 0 & 1 are set to 1) readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL); - reg32_write ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL, ( readvalue & ~(1 << DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ))); + reg32_write ((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL, (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ))); // Byte lane 0 power up readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); - reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE))); + reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE))); readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); - reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, ( readvalue & 0xffff800f)); + reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, (readvalue & 0xffff800f)); readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); - reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ))); + reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ))); // Byte lane 1 power up readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); - reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE))); + reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE))); readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); - reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, ( readvalue & 0xffff800f)); + reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, (readvalue & 0xffff800f)); readvalue = reg32_read ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); - reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, ( readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ))); + reg32_write ((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ))); // Turn on PHY_CONTROL AUTO_OEB C not required // Enable byte lane AUTO_DQ_RXENB_MODE: bits 18 and 19 of the byte lane IDLE_PAD_CONTROL C already set 180114c8: 000f000a @@ -108,7 +108,7 @@ printk(BIOS_INFO, "\n....poll lock..\n"); // Poll lock readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_STATUS); - while ( ( readvalue & 0x1) == 0x0 ) + while ((readvalue & 0x1) == 0x0) { printk(BIOS_INFO, "\n....DDR_PHY_CONTROL_REGS_PLL_STATUS = %8x..\n",readvalue); readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_STATUS); @@ -143,7 +143,7 @@ { uint32_t val; -#define SET_OVR_STEP(v) ( 0x30000 | ( (v) & 0x3F ) ) /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */ +#define SET_OVR_STEP(v) (0x30000 | ((v) & 0x3F)) /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */ val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN); val = SET_OVR_STEP(val & 0xff); @@ -441,27 +441,27 @@ /*DDR_SHMOO_RELATED_CHANGE*/ #ifdef CONFIG_RUN_DDR_SHMOO -int ReWriteModeRegisters( void ) +int ReWriteModeRegisters(void) { int nRet = 0; int j = 100; - reg32_clear_bits( (volatile uint32_t *)DDR_DENALI_CTL_89 , 1 << 18 ); + reg32_clear_bits((volatile uint32_t *)DDR_DENALI_CTL_89 , 1 << 18); /* Set mode register for MR0, MR1, MR2 and MR3 write for all chip selects */ - reg32_write( (volatile uint32_t *)DDR_DENALI_CTL_43 , (1 << 17) | (1 << 24) | (1 << 25) ); + reg32_write((volatile uint32_t *)DDR_DENALI_CTL_43 , (1 << 17) | (1 << 24) | (1 << 25)); /* Trigger Mode Register Write(MRW) sequence */ - reg32_set_bits( (volatile uint32_t *)DDR_DENALI_CTL_43 , 1 << 25 ); + reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_43 , 1 << 25); do { - if ( reg32_read( (volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18) ) { + if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) { break; } --j; - } while ( j ); + } while (j); - if ( j == 0 && (reg32_read( (volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18) ) == 0 ) { + if (j == 0 && (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) == 0) { printk(BIOS_ERR, "Error: DRAM mode registers write failed\n"); nRet = 1; }; @@ -965,7 +965,7 @@ for (i=0; i<pairs; i++) { reg = (uint32_t *)(*flptr++); val = (uint32_t *)(*flptr++); - if ( (((uint32_t)reg >= DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + 0x114))) + if ((((uint32_t)reg >= DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + 0x114))) #if IS_ENABLED(CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) || defined(CONFIG_NS_PLUS) || (((uint32_t)reg >= DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN + 0x114))) #endif @@ -983,7 +983,7 @@ printk(BIOS_INFO, "done\n"); /* Perform memory test to see if the parameters work */ - if (CONFIG_SHMOO_REUSE_MEMTEST_LENGTH > 0 ) { + if (CONFIG_SHMOO_REUSE_MEMTEST_LENGTH > 0) { printk(BIOS_INFO, "Running simple memory test ..... "); i = simple_memory_test( (void *)CONFIG_SHMOO_REUSE_MEMTEST_START, @@ -1118,7 +1118,7 @@ reg32_write((uint32_t *)DDR_BistConfig,reg32_read((uint32_t *)DDR_BistConfig) & ~0x1); - for ( i = 0; i < 1000; i++); + for (i = 0; i < 1000; i++); #if !defined(CONFIG_IPROC_P7) reg32_write((volatile uint32_t *)DDR_DENALI_CTL_213, 0x00FFFFFF); @@ -1377,7 +1377,7 @@ /* Wait for DDR PHY up */ for (i=0; i < 0x19000; i++) { val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION); - if ( val != 0) { + if (val != 0) { printk(BIOS_INFO, "PHY revision version: 0x%08x\n", val); break; /* DDR PHY is up */ } @@ -1484,7 +1484,7 @@ /* Enable auto self-refresh */ reg32_set_bits((unsigned int *)DDR_DENALI_CTL_57, 0x2 << DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_R | - 0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R ); + 0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R); reg32_set_bits((unsigned int *)DDR_DENALI_CTL_58, DDR_AUTO_SELF_REFRESH_IDLE_COUNT << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R); @@ -1495,9 +1495,9 @@ /* Disable auto-self refresh */ reg32_clear_bits((unsigned int *)DDR_DENALI_CTL_57, 0x2 << DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_R | - 0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R ); + 0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R); reg32_clear_bits((unsigned int *)DDR_DENALI_CTL_58, - 0xff << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R ); + 0xff << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R); #endif /* Start the DDR */ diff --git a/src/soc/broadcom/cygnus/phy_reg_access.c b/src/soc/broadcom/cygnus/phy_reg_access.c index eb48133..7965d5b 100644 --- a/src/soc/broadcom/cygnus/phy_reg_access.c +++ b/src/soc/broadcom/cygnus/phy_reg_access.c @@ -17,14 +17,14 @@ volatile unsigned long data; - data = (* (volatile uint32 *) ( ((uint32)GLOBAL_REG_RBUS_START) | (address))); + data = (* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))); //printf("REGRD %08X=%08X\n", address, data); return data; } uint32 REGWR (uint32 address, uint32 data) { - ((* (volatile uint32 *) ( ((uint32)GLOBAL_REG_RBUS_START) | (address))) = data); + ((* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))) = data); //printf("REGWR %08X=%08X\n", address, data); // return SOC_E_NONE; return 0; diff --git a/src/soc/intel/baytrail/perf_power.c b/src/soc/intel/baytrail/perf_power.c index 20a0664..6cddf76 100644 --- a/src/soc/intel/baytrail/perf_power.c +++ b/src/soc/intel/baytrail/perf_power.c @@ -221,7 +221,7 @@ E(CCU, 0x38, MASK_VAL(31, 0, 0x0)), //vlv.ccu.ccu_trunk_clkgate_2 E(CCU, 0x1c, MASK_VAL(29, 28, 0x0)), //vlv.ccu.clkgate_en_1.cr_lpe_pri_clkgate_en E(CCU, 0x1c, MASK_VAL(25, 24, 0x0)), //vlv.ccu.clkgate_en_1.cr_lpe_sb_clkgate_en -E(CCU, 0x1c, MASK_VAL( 1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en +E(CCU, 0x1c, MASK_VAL(1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en E(CCU, 0x54, MASK_VAL(17, 16, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_func_ip_clkgate_en E(CCU, 0x54, MASK_VAL(13, 12, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_osc_ip_clk_en E(CCU, 0x54, MASK_VAL(15, 14, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_xtal_ip_clkgate_en diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index 4d13539..ccd6c9f 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -24,7 +24,7 @@ static void pci_domain_set_resources(struct device *dev) { - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); assign_resources(dev->link_list); } @@ -49,7 +49,7 @@ static void enable_dev(struct device *dev) { - printk(BIOS_SPEW, "----------\n%s/%s ( %s ), type: %d\n", + printk(BIOS_SPEW, "----------\n%s/%s (%s), type: %d\n", __FILE__, __func__, dev_name(dev), dev->path.type); printk(BIOS_SPEW, "vendor: 0x%04x. device: 0x%04x\n", @@ -384,7 +384,7 @@ static void pci_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) { - printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n", + printk(BIOS_SPEW, "%s/%s (%s, 0x%04x, 0x%04x)\n", __FILE__, __func__, dev_name(dev), vendor, device); if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 27903e8..195dba4 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -47,7 +47,7 @@ static void soc_core_init(struct device *cpu) { - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(cpu)); printk(BIOS_DEBUG, "Init Braswell core.\n"); @@ -219,7 +219,7 @@ { struct bus *cpu_bus = dev->link_list; - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); if (mp_init_with_smm(cpu_bus, &mp_ops)) diff --git a/src/soc/intel/braswell/emmc.c b/src/soc/intel/braswell/emmc.c index 44116a8..238f8db 100644 --- a/src/soc/intel/braswell/emmc.c +++ b/src/soc/intel/braswell/emmc.c @@ -36,7 +36,7 @@ { struct soc_intel_braswell_config *config = dev->chip_info; - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); printk(BIOS_DEBUG, "eMMC init\n"); reg_script_run_on_dev(dev, emmc_ops); diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c index b329531..895d2ee 100644 --- a/src/soc/intel/braswell/gfx.c +++ b/src/soc/intel/braswell/gfx.c @@ -49,7 +49,7 @@ static void gfx_pre_vbios_init(struct device *dev) { - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); gfx_run_script(dev, gpu_pre_vbios_script); @@ -57,7 +57,7 @@ static void gfx_post_vbios_init(struct device *dev) { - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); printk(BIOS_INFO, "GFX: Post VBIOS Init\n"); gfx_run_script(dev, gfx_post_vbios_script); @@ -65,7 +65,7 @@ static void gfx_init(struct device *dev) { - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); /* Pre VBIOS Init */ diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 7c9f306..6338878 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -153,7 +153,7 @@ { struct soc_intel_braswell_config *config = dev->chip_info; - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); lpe_stash_firmware_info(dev); diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c index aac953b..60ff49f 100644 --- a/src/soc/intel/braswell/lpss.c +++ b/src/soc/intel/braswell/lpss.c @@ -143,7 +143,7 @@ struct soc_intel_braswell_config *config = dev->chip_info; int iosf_reg, nvs_index; - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); printk(BIOS_SPEW, "%s - %s\n", get_pci_class_name(dev), diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c index 1a127f4..efd891a 100644 --- a/src/soc/intel/braswell/pcie.c +++ b/src/soc/intel/braswell/pcie.c @@ -41,7 +41,7 @@ static void pcie_init(struct device *dev) { - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); } @@ -56,7 +56,7 @@ { int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT; - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); switch (root_port_offset(dev)) { @@ -99,7 +99,7 @@ static uint32_t rootports_in_use = MAX_ROOT_PORTS_BSW; - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); /* Set slot implemented. */ pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI); @@ -137,7 +137,7 @@ static void pcie_enable(struct device *dev) { - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); if (is_first_port(dev)) { struct soc_intel_braswell_config *config = dev->chip_info; @@ -162,7 +162,7 @@ static void pcie_root_set_subsystem(struct device *dev, unsigned int vid, unsigned int did) { - printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n", + printk(BIOS_SPEW, "%s/%s (%s, 0x%04x, 0x%04x)\n", __FILE__, __func__, dev_name(dev), vid, did); uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff); diff --git a/src/soc/intel/braswell/sata.c b/src/soc/intel/braswell/sata.c index 8052b29..2507641 100644 --- a/src/soc/intel/braswell/sata.c +++ b/src/soc/intel/braswell/sata.c @@ -30,7 +30,7 @@ static void sata_init(struct device *dev) { - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); } diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c index 122c67e..17fc685 100644 --- a/src/soc/intel/braswell/scc.c +++ b/src/soc/intel/braswell/scc.c @@ -29,7 +29,7 @@ struct resource *bar; global_nvs_t *gnvs; - printk(BIOS_SPEW, "%s/%s ( %s, 0x%08x, 0x%08x )\n", + printk(BIOS_SPEW, "%s/%s (%s, 0x%08x, 0x%08x)\n", __FILE__, __func__, dev_name(dev), iosf_reg, nvs_index); /* Find ACPI NVS to update BARs */ diff --git a/src/soc/intel/braswell/sd.c b/src/soc/intel/braswell/sd.c index 97c39b3..1775ce7 100644 --- a/src/soc/intel/braswell/sd.c +++ b/src/soc/intel/braswell/sd.c @@ -35,7 +35,7 @@ { struct soc_intel_braswell_config *config = dev->chip_info; - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); if (config == NULL) diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index 14b412a..ca87d63 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -55,14 +55,14 @@ add_mmio_resource(struct device *dev, int i, unsigned long addr, unsigned long size) { - printk(BIOS_SPEW, "%s/%s ( %s, 0x%016lx, 0x%016lx )\n", + printk(BIOS_SPEW, "%s/%s (%s, 0x%016lx, 0x%016lx)\n", __FILE__, __func__, dev_name(dev), addr, size); mmio_resource(dev, i, addr >> 10, size >> 10); } static void sc_add_mmio_resources(struct device *dev) { - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE); add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE); @@ -102,7 +102,7 @@ { struct resource *res; - printk(BIOS_SPEW, "%s/%s ( %s, 0x%08x, 0x%08x, 0x%08x )\n", + printk(BIOS_SPEW, "%s/%s (%s, 0x%08x, 0x%08x, 0x%08x)\n", __FILE__, __func__, dev_name(dev), base, size, index); if (io_range_in_default(base, size)) @@ -118,7 +118,7 @@ { struct resource *res; - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); /* Add the default claimed IO range for the LPC device. */ @@ -136,7 +136,7 @@ static void sc_read_resources(struct device *dev) { - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); /* Get the normal PCI resources of this device. */ @@ -165,7 +165,7 @@ const struct soc_irq_route *ir = &global_soc_irq_route; struct soc_intel_braswell_config *config = dev->chip_info; - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); /* Set up the PIRQ PIC routing based on static config. */ @@ -206,7 +206,7 @@ uint32_t mask = 0; uint32_t mask2 = 0; - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); #define SET_DIS_MASK(name_) \ @@ -292,7 +292,7 @@ { uint32_t reg8; - printk(BIOS_SPEW, "%s/%s ( %s, 0x%08x )\n", + printk(BIOS_SPEW, "%s/%s (%s, 0x%08x)\n", __FILE__, __func__, dev_name(dev), offset); printk(BIOS_DEBUG, "Power management CAP offset 0x%x.\n", offset); reg8 = pci_read_config8(dev, offset + 4); @@ -309,7 +309,7 @@ { void *gctl = (void *)(TEMP_BASE_ADDRESS + 0x8); - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); /* Need to set magic register 0x43 to 0xd7 in config space. */ @@ -331,7 +331,7 @@ { unsigned int offset; - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); /* @@ -410,7 +410,7 @@ { uint32_t reg32; - printk(BIOS_SPEW, "%s/%s ( %s )\n", + printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); if (!dev->enabled) { int slot = PCI_SLOT(dev->path.pci.devfn); @@ -461,7 +461,7 @@ int __weak mainboard_get_spi_config(struct spi_config *cfg) { - printk(BIOS_SPEW, "%s/%s ( 0x%p )\n", + printk(BIOS_SPEW, "%s/%s (0x%p)\n", __FILE__, __func__, (void *)cfg); return -1; } @@ -475,7 +475,7 @@ uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS; struct spi_config cfg; - printk(BIOS_SPEW, "%s/%s ( 0x%p )\n", + printk(BIOS_SPEW, "%s/%s (0x%p)\n", __FILE__, __func__, unused); /* Set the lock enable on the BIOS control register. */ diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c index 6f0049f..8ce0a1d 100644 --- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c +++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c @@ -37,8 +37,8 @@ * Check if INIT# is asserted by port 0xCF9 and whether RCBA has been set. * If either is true, then this is a warm reset so execute a Hard Reset */ - if ( (inb(0xcf9) == 0x04) || - (pci_io_read_config32(LPC_BDF, RCBA) & RCBA_ENABLE) ) { + if ((inb(0xcf9) == 0x04) || + (pci_io_read_config32(LPC_BDF, RCBA) & RCBA_ENABLE)) { outb(0x00, 0xcf9); outb(0x06, 0xcf9); } diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index a7268aa..55bdbf1 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -314,7 +314,7 @@ if (prev_sleep_state == ACPI_S3) { /* S3 resume */ - if ( pFspInitParams->NvsBufferPtr == NULL) { + if (pFspInitParams->NvsBufferPtr == NULL) { /* If waking from S3 and no cache then. */ printk(BIOS_WARNING, "No MRC cache found in S3 resume path.\n"); post_code(POST_RESUME_FAILURE); @@ -322,7 +322,7 @@ outl(inl(ACPI_BASE_ADDRESS + PM1_CNT) & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); /* Reboot */ - printk(BIOS_WARNING,"Rebooting..\n" ); + printk(BIOS_WARNING,"Rebooting..\n"); warm_reset(); /* Should not reach here.. */ die("Reboot System\n"); diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index 9f22b25..f909121 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -158,7 +158,7 @@ (bmbound - fsp_mem_base) >> 10); if (highmem_size) { - ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10 ); + ram_resource(dev, index++, 0x100000000 >> 10, highmem_size >> 10); } printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", highmem_size >> 20); diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index 7a25bfe..00fbde4 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -589,9 +589,9 @@ } } else if (hold < setup) { - /* like this: (hold time != 0 )*/ + /* like this: (hold time != 0)*/ /* xxxoooooooooooooooooo|ooooooooxxxxxxxxxxxxxxxxx */ - /* like this: (hold time == 0 ) */ + /* like this: (hold time == 0) */ /* xxxoooooooooooooooxxx|xxxxxxxxxxxxxxxxxxxxxxxxx */ p->best_dqsdly = 0; @@ -1121,7 +1121,7 @@ dramc_dbg_msg("DQ Delay :\n"); for (i = 0; i < DATA_WIDTH_32BIT; i++) { dramc_dbg_msg("DQ%d = %d ", i, dqdqs_perbit_dly[i].best_dqdly); - if ( ((i + 1) % 4) == 0) + if (((i + 1) % 4) == 0) dramc_dbg_msg("\n"); } diff --git a/src/soc/nvidia/tegra124/sdram_lp0.c b/src/soc/nvidia/tegra124/sdram_lp0.c index 536ad31..5cc5889 100644 --- a/src/soc/nvidia/tegra124/sdram_lp0.c +++ b/src/soc/nvidia/tegra124/sdram_lp0.c @@ -44,9 +44,9 @@ #define pack(src, src_bits, dst, dst_bits) { \ _Static_assert((1 ? src_bits) >= (0 ? src_bits) && (1 ? dst_bits) >= \ - (0 ? dst_bits), "byte range flipped (must be MSB:LSB)" ); \ + (0 ? dst_bits), "byte range flipped (must be MSB:LSB)"); \ _Static_assert((1 ? src_bits) - (0 ? src_bits) == (1 ? dst_bits) - \ - (0 ? dst_bits), "src and dst byte range lengths differ" ); \ + (0 ? dst_bits), "src and dst byte range lengths differ"); \ u32 mask = 0xffffffff >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \ dst &= ~(mask << (0 ? dst_bits)); \ dst |= ((src >> (0 ? src_bits)) & mask) << (0 ? dst_bits); \ diff --git a/src/soc/nvidia/tegra210/sdram_lp0.c b/src/soc/nvidia/tegra210/sdram_lp0.c index c3a4dd4..9eaf5f0 100644 --- a/src/soc/nvidia/tegra210/sdram_lp0.c +++ b/src/soc/nvidia/tegra210/sdram_lp0.c @@ -32,9 +32,9 @@ #define pack(src, src_bits, dst, dst_bits) { \ _Static_assert((1 ? src_bits) >= (0 ? src_bits) && (1 ? dst_bits) >= \ - (0 ? dst_bits), "byte range flipped (must be MSB:LSB)" ); \ + (0 ? dst_bits), "byte range flipped (must be MSB:LSB)"); \ _Static_assert((1 ? src_bits) - (0 ? src_bits) == (1 ? dst_bits) - \ - (0 ? dst_bits), "src and dst byte range lengths differ" ); \ + (0 ? dst_bits), "src and dst byte range lengths differ"); \ u32 mask = 0xffffffff >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \ dst &= ~(mask << (0 ? dst_bits)); \ dst |= ((src >> (0 ? src_bits)) & mask) << (0 ? dst_bits); \ diff --git a/src/soc/samsung/exynos5250/clock.c b/src/soc/samsung/exynos5250/clock.c index 63e30f6..a6cc3c7 100644 --- a/src/soc/samsung/exynos5250/clock.c +++ b/src/soc/samsung/exynos5250/clock.c @@ -617,7 +617,7 @@ epll_con |= epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT; /* - * Required period ( in cycles) to generate a stable clock output. + * Required period (in cycles) to generate a stable clock output. * The maximum clock time can be up to 3000 * PDIV cycles of PLLs * frequency input (as per spec) */ diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c index 3c4bb04..04125d9 100644 --- a/src/soc/samsung/exynos5420/clock.c +++ b/src/soc/samsung/exynos5420/clock.c @@ -582,7 +582,7 @@ epll_con |= epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT; /* - * Required period ( in cycles) to generate a stable clock output. + * Required period (in cycles) to generate a stable clock output. * The maximum clock time can be up to 3000 * PDIV cycles of PLLs * frequency input (as per spec) */ diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c index 1b6f5ae..30fcd37 100644 --- a/src/southbridge/amd/agesa/hudson/sm.c +++ b/src/southbridge/amd/agesa/hudson/sm.c @@ -45,8 +45,8 @@ #define BIT6 (1 << 6) #define BIT7 (1 << 7) -#define BIT8 (1 << 8 ) -#define BIT9 (1 << 9 ) +#define BIT8 (1 << 8) +#define BIT9 (1 << 9) #define BIT10 (1 << 10) #define BIT11 (1 << 11) #define BIT12 (1 << 12) diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c index f3ba8b6..8a197b8 100644 --- a/src/southbridge/amd/amd8111/early_ctrl.c +++ b/src/southbridge/amd/amd8111/early_ctrl.c @@ -68,7 +68,7 @@ pci_write_config8(dev, 0x74, 4); - /* set VFSMAF ( VID/FID System Management Action Field) to 2 */ + /* set VFSMAF (VID/FID System Management Action Field) to 2 */ pci_write_config32(dev, 0x70, 2<<12); } diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c index 52306ab..4f6b9d9 100644 --- a/src/southbridge/amd/amd8132/bridge.c +++ b/src/southbridge/amd/amd8132/bridge.c @@ -213,7 +213,7 @@ if (chip_rev == 0x01) { /* Errata #37 */ byte = pci_read_config8(dev, 0x0c); - if (byte == 0x08 ) + if (byte == 0x08) pci_write_config8(dev, 0x0c, 0x10); #if 0 @@ -385,7 +385,7 @@ } - if ( (chip_rev == 0x11) ||(chip_rev == 0x12) ) { + if ((chip_rev == 0x11) ||(chip_rev == 0x12)) { //for b1 b2 /* Errata #73 */ dword = pci_read_config32(dev, 0x80); diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c index 977ffb6..db87b6a 100644 --- a/src/southbridge/amd/cimx/sb800/fan.c +++ b/src/southbridge/amd/cimx/sb800/fan.c @@ -70,7 +70,7 @@ * * Device 20, Function 3, Reg 0xA4 * [0]: if 1, the address specified in IMC_PortAddress is used. - * [15:1] IMC_PortAddress bits 15:1 (0x17 - address 0x2E ) + * [15:1] IMC_PortAddress bits 15:1 (0x17 - address 0x2E) */ pci_write_config16(dev, 0xA4, sb_chip->imc_port_address | 0x01); @@ -102,7 +102,7 @@ sb_config.Pecstruct.MSGFun81zone0MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone0MSGREG1 = IMC_ZONE0; message_ptr = &sb_config.Pecstruct.MSGFun81zone0MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ ) + for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone0_config_vals[i]; /* EC LDN9 function 83 zone 0 - Temperature Thresholds */ @@ -110,14 +110,14 @@ sb_config.Pecstruct.MSGFun83zone0MSGREG1 = IMC_ZONE0; sb_config.Pecstruct.MSGFun83zone0MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone0MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ ) + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone0_thresholds[i]; /*EC LDN9 function 85 zone 0 - Fan Speeds */ sb_config.Pecstruct.MSGFun85zone0MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone0MSGREG1 = IMC_ZONE0; message_ptr = &sb_config.Pecstruct.MSGFun85zone0MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ ) + for (i = 0; i < IMC_FAN_SPEED_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone0_fanspeeds[i]; } @@ -133,7 +133,7 @@ sb_config.Pecstruct.MSGFun81zone1MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone1MSGREG1 = IMC_ZONE1; message_ptr = &sb_config.Pecstruct.MSGFun81zone1MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ ) + for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone1_config_vals[i]; /* EC LDN9 function 83 zone 1 - Temperature Thresholds */ @@ -141,14 +141,14 @@ sb_config.Pecstruct.MSGFun83zone1MSGREG1 = IMC_ZONE1; sb_config.Pecstruct.MSGFun83zone1MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone1MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ ) + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone1_thresholds[i]; /* EC LDN9 function 85 zone 1 - Fan Speeds */ sb_config.Pecstruct.MSGFun85zone1MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone1MSGREG1 = IMC_ZONE1; message_ptr = &sb_config.Pecstruct.MSGFun85zone1MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ ) + for (i = 0; i < IMC_FAN_SPEED_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone1_fanspeeds[i]; } @@ -165,7 +165,7 @@ sb_config.Pecstruct.MSGFun81zone2MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone2MSGREG1 = IMC_ZONE2; message_ptr = &sb_config.Pecstruct.MSGFun81zone2MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ ) + for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone2_config_vals[i]; /* EC LDN9 function 83 zone 2 */ @@ -173,14 +173,14 @@ sb_config.Pecstruct.MSGFun83zone2MSGREG1 = IMC_ZONE2; sb_config.Pecstruct.MSGFun83zone2MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone2MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ ) + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone2_thresholds[i]; /* EC LDN9 function 85 zone 2 */ sb_config.Pecstruct.MSGFun85zone2MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone2MSGREG1 = IMC_ZONE2; message_ptr = &sb_config.Pecstruct.MSGFun85zone2MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ ) + for (i = 0; i < IMC_FAN_SPEED_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone2_fanspeeds[i]; } @@ -197,7 +197,7 @@ sb_config.Pecstruct.MSGFun81zone3MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun81zone3MSGREG1 = IMC_ZONE3; message_ptr = &sb_config.Pecstruct.MSGFun81zone3MSGREG2; - for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ ) + for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone3_config_vals[i]; /* EC LDN9 function 83 zone 3 */ @@ -205,14 +205,14 @@ sb_config.Pecstruct.MSGFun83zone3MSGREG1 = IMC_ZONE3; sb_config.Pecstruct.MSGFun83zone3MSGREGB = 0x00; message_ptr = &sb_config.Pecstruct.MSGFun83zone3MSGREG2; - for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ ) + for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone3_thresholds[i]; /* EC LDN9 function 85 zone 3 */ sb_config.Pecstruct.MSGFun85zone3MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun85zone3MSGREG1 = IMC_ZONE3; message_ptr = &sb_config.Pecstruct.MSGFun85zone3MSGREG2; - for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ ) + for (i = 0; i < IMC_FAN_SPEED_COUNT; i++) *(message_ptr + i) = sb_chip->imc_zone3_fanspeeds[i]; } @@ -231,11 +231,11 @@ /* EC LDN9 function 89 TEMPIN channel 0 */ sb_config.Pecstruct.MSGFun89zone0MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun89zone0MSGREG1 = 0x00; - sb_config.Pecstruct.MSGFun89zone0MSGREG2 = ( sb_chip->imc_tempin0_at & 0xff); + sb_config.Pecstruct.MSGFun89zone0MSGREG2 = (sb_chip->imc_tempin0_at & 0xff); sb_config.Pecstruct.MSGFun89zone0MSGREG3 = ((sb_chip->imc_tempin0_at >> 8) & 0xff); sb_config.Pecstruct.MSGFun89zone0MSGREG4 = ((sb_chip->imc_tempin0_at >> 16) & 0xff); sb_config.Pecstruct.MSGFun89zone0MSGREG5 = ((sb_chip->imc_tempin0_at >> 24) & 0xff); - sb_config.Pecstruct.MSGFun89zone0MSGREG6 = ( sb_chip->imc_tempin0_ct & 0xff); + sb_config.Pecstruct.MSGFun89zone0MSGREG6 = (sb_chip->imc_tempin0_ct & 0xff); sb_config.Pecstruct.MSGFun89zone0MSGREG7 = ((sb_chip->imc_tempin0_ct >> 8) & 0xff); sb_config.Pecstruct.MSGFun89zone0MSGREG8 = ((sb_chip->imc_tempin0_ct >> 16) & 0xff); sb_config.Pecstruct.MSGFun89zone0MSGREG9 = ((sb_chip->imc_tempin0_ct >> 24) & 0xff); @@ -249,11 +249,11 @@ /* EC LDN9 function 89 TEMPIN channel 1 */ sb_config.Pecstruct.MSGFun89zone1MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun89zone1MSGREG1 = 0x01; - sb_config.Pecstruct.MSGFun89zone1MSGREG2 = ( sb_chip->imc_tempin1_at & 0xff); + sb_config.Pecstruct.MSGFun89zone1MSGREG2 = (sb_chip->imc_tempin1_at & 0xff); sb_config.Pecstruct.MSGFun89zone1MSGREG3 = ((sb_chip->imc_tempin1_at >> 8) & 0xff); sb_config.Pecstruct.MSGFun89zone1MSGREG4 = ((sb_chip->imc_tempin1_at >> 16) & 0xff); sb_config.Pecstruct.MSGFun89zone1MSGREG5 = ((sb_chip->imc_tempin1_at >> 24) & 0xff); - sb_config.Pecstruct.MSGFun89zone1MSGREG6 = ( sb_chip->imc_tempin1_ct & 0xff); + sb_config.Pecstruct.MSGFun89zone1MSGREG6 = (sb_chip->imc_tempin1_ct & 0xff); sb_config.Pecstruct.MSGFun89zone1MSGREG7 = ((sb_chip->imc_tempin1_ct >> 8) & 0xff); sb_config.Pecstruct.MSGFun89zone1MSGREG8 = ((sb_chip->imc_tempin1_ct >> 16) & 0xff); sb_config.Pecstruct.MSGFun89zone1MSGREG9 = ((sb_chip->imc_tempin1_ct >> 24) & 0xff); @@ -267,11 +267,11 @@ /* EC LDN9 function 89 TEMPIN channel 2 */ sb_config.Pecstruct.MSGFun89zone2MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun89zone2MSGREG1 = 0x02; - sb_config.Pecstruct.MSGFun89zone2MSGREG2 = ( sb_chip->imc_tempin2_at & 0xff); + sb_config.Pecstruct.MSGFun89zone2MSGREG2 = (sb_chip->imc_tempin2_at & 0xff); sb_config.Pecstruct.MSGFun89zone2MSGREG3 = ((sb_chip->imc_tempin2_at >> 8) & 0xff); sb_config.Pecstruct.MSGFun89zone2MSGREG4 = ((sb_chip->imc_tempin2_at >> 16) & 0xff); sb_config.Pecstruct.MSGFun89zone2MSGREG5 = ((sb_chip->imc_tempin2_at >> 24) & 0xff); - sb_config.Pecstruct.MSGFun89zone2MSGREG6 = ( sb_chip->imc_tempin2_ct & 0xff); + sb_config.Pecstruct.MSGFun89zone2MSGREG6 = (sb_chip->imc_tempin2_ct & 0xff); sb_config.Pecstruct.MSGFun89zone2MSGREG7 = ((sb_chip->imc_tempin2_ct >> 8) & 0xff); sb_config.Pecstruct.MSGFun89zone2MSGREG8 = ((sb_chip->imc_tempin2_ct >> 16) & 0xff); sb_config.Pecstruct.MSGFun89zone2MSGREG9 = ((sb_chip->imc_tempin2_ct >> 24) & 0xff); @@ -285,11 +285,11 @@ /* EC LDN9 function 89 TEMPIN channel 3 */ sb_config.Pecstruct.MSGFun89zone3MSGREG0 = 0x00; sb_config.Pecstruct.MSGFun89zone3MSGREG1 = 0x03; - sb_config.Pecstruct.MSGFun89zone3MSGREG2 = ( sb_chip->imc_tempin3_at & 0xff); + sb_config.Pecstruct.MSGFun89zone3MSGREG2 = (sb_chip->imc_tempin3_at & 0xff); sb_config.Pecstruct.MSGFun89zone3MSGREG3 = ((sb_chip->imc_tempin3_at >> 8) & 0xff); sb_config.Pecstruct.MSGFun89zone3MSGREG4 = ((sb_chip->imc_tempin3_at >> 16) & 0xff); sb_config.Pecstruct.MSGFun89zone3MSGREG5 = ((sb_chip->imc_tempin3_at >> 24) & 0xff); - sb_config.Pecstruct.MSGFun89zone3MSGREG6 = ( sb_chip->imc_tempin3_ct & 0xff); + sb_config.Pecstruct.MSGFun89zone3MSGREG6 = (sb_chip->imc_tempin3_ct & 0xff); sb_config.Pecstruct.MSGFun89zone3MSGREG7 = ((sb_chip->imc_tempin3_ct >> 8) & 0xff); sb_config.Pecstruct.MSGFun89zone3MSGREG8 = ((sb_chip->imc_tempin3_ct >> 16) & 0xff); sb_config.Pecstruct.MSGFun89zone3MSGREG9 = ((sb_chip->imc_tempin3_ct >> 24) & 0xff); diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c index 865b577..017c764 100644 --- a/src/southbridge/amd/rs780/early_setup.c +++ b/src/southbridge/amd/rs780/early_setup.c @@ -35,7 +35,7 @@ static void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index, u32 data) { - pci_write_config32(dev, index_reg, index /* | 0x80 */ ); + pci_write_config32(dev, index_reg, index /* | 0x80 */); pci_write_config32(dev, index_reg + 0x4, data); } diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index 43bfb02..a765655 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -247,7 +247,7 @@ } } if (pMMIO[k].Limit != 0) { - if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0 ) { + if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) { Base = 0; } else diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index 1d1ac13..57dd7bc 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -461,7 +461,7 @@ else printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n", (i / 2) ? "Secondary" : "Primary", - (i % 2 ) ? "Slave" : "Master", + (i % 2) ? "Slave" : "Master", (j == 10) ? "not " : "", (j == 10) ? j : j + 1); } else { @@ -470,7 +470,7 @@ else printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n", (i / 2) ? "Secondary" : "Primary", - (i % 2 ) ? "Slave" : "Master", i); + (i % 2) ? "Slave" : "Master", i); } } diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c index 15b2527..8e6009a 100644 --- a/src/southbridge/amd/sb800/sata.c +++ b/src/southbridge/amd/sb800/sata.c @@ -177,7 +177,7 @@ byte = read8(sata_bar5 + 0x128 + 0x80 * i); printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte); byte &= 0xF; - if ( byte == 0x1 ) { + if (byte == 0x1) { /* If the drive status is 0x1 then we see it but we aren't talking to it. */ /* Try to do something about it. */ printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n"); @@ -212,13 +212,13 @@ } printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n", (i / 2) ? "Secondary" : "Primary", - (i % 2 ) ? "Slave" : "Master", + (i % 2) ? "Slave" : "Master", (j == 10) ? "not " : "", (j == 10) ? j : j + 1); } else { printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n", (i / 2) ? "Secondary" : "Primary", - (i % 2 ) ? "Slave" : "Master", i); + (i % 2) ? "Slave" : "Master", i); } } diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c index d4ed3cc..fdb6283 100644 --- a/src/southbridge/amd/sb800/sm.c +++ b/src/southbridge/amd/sb800/sm.c @@ -45,8 +45,8 @@ #define BIT6 (1 << 6) #define BIT7 (1 << 7) -#define BIT8 (1 << 8 ) -#define BIT9 (1 << 9 ) +#define BIT8 (1 << 8) +#define BIT9 (1 << 9) #define BIT10 (1 << 10) #define BIT11 (1 << 11) #define BIT12 (1 << 12) diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index 8986e67..159f3e4 100644 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -665,7 +665,7 @@ /* CIMx CommonPortInit settings that are not set above. */ pci_ext_write_config32(nb_dev, dev, 0x88, 0xF0, 1 << 0); /* LINK_CRTL2 */ - if ( port == 8 ) + if (port == 8) set_pcie_enable_bits(dev, 0xA0, 0, 1 << 23); #if 0 //SR56x0 pcie Gen2 code is not tested yet, we should enable it again when test finished. @@ -687,7 +687,7 @@ pci_ext_write_config32(nb_dev, dev, 0x74, 1 << 3, 1 << 3); /* 5.12.9.3 step 2 - PCIEP_PORT_CNTL - enable hotplug messages */ - if ( port != 8) + if (port != 8) set_pcie_enable_bits(dev, 0x10, 1 << 2, 1 << 2); /* Not sure about this PME setup */ @@ -806,7 +806,7 @@ set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 1 << 6, 1 << 6); /* Step 20: Disables immediate RCB timeout on link down */ - if (!((pci_read_config32(dev, 0x6C ) >> 6) & 0x01)) { + if (!((pci_read_config32(dev, 0x6C) >> 6) & 0x01)) { set_pcie_enable_bits(dev, 0x70, 1 << 19, 0 << 19); } diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c index 3477c52..5b95c57 100644 --- a/src/southbridge/intel/i82371eb/smbus.c +++ b/src/southbridge/intel/i82371eb/smbus.c @@ -68,7 +68,7 @@ * power-on default is 0x7fffbfffh */ if (gpo) { /* only 8bit access allowed */ - outb( gpo & 0xff, DEFAULT_PMBASE + GPO0); + outb(gpo & 0xff, DEFAULT_PMBASE + GPO0); outb((gpo >> 8) & 0xff, DEFAULT_PMBASE + GPO1); outb((gpo >> 16) & 0xff, DEFAULT_PMBASE + GPO2); outb((gpo >> 24) & 0xff, DEFAULT_PMBASE + GPO3); diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c index bdbcba7..361bed3 100644 --- a/src/southbridge/ricoh/rl5c476/rl5c476.c +++ b/src/southbridge/ricoh/rl5c476/rl5c476.c @@ -166,7 +166,7 @@ /* For CF socket we need an extra memory window for * the control structure of the CF itself */ - if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ + if (enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ /* fake index as it isn't in PCI config space */ resource = new_resource(dev, 1); resource->flags |= IORESOURCE_MEM; @@ -181,9 +181,9 @@ { struct resource *resource; printk(BIOS_DEBUG, "%s In set resources\n",dev_path(dev)); - if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ + if (enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){ resource = find_resource(dev,1); - if ( !(resource->flags & IORESOURCE_STORED) ){ + if (!(resource->flags & IORESOURCE_STORED)){ resource->flags |= IORESOURCE_STORED; printk(BIOS_DEBUG, "%s 1 ==> %llx\n", dev_path(dev), resource->base); cf_base = resource->base; diff --git a/src/superio/serverengines/pilot/early_init.c b/src/superio/serverengines/pilot/early_init.c index acd2ab4..82438e4 100644 --- a/src/superio/serverengines/pilot/early_init.c +++ b/src/superio/serverengines/pilot/early_init.c @@ -59,7 +59,7 @@ pnp_set_logical_device(PNP_DEV(port, 0x4)); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); - pnp_set_enable( PNP_DEV(port, 0x4), 0); + pnp_set_enable(PNP_DEV(port, 0x4), 0); pnp_exit_ext_func_mode(dev); pnp_enter_ext_func_mode(dev); diff --git a/src/superio/smsc/sch4037/sch4037_early_init.c b/src/superio/smsc/sch4037/sch4037_early_init.c index eea9dce..0ebd207 100644 --- a/src/superio/smsc/sch4037/sch4037_early_init.c +++ b/src/superio/smsc/sch4037/sch4037_early_init.c @@ -41,7 +41,7 @@ /* Auto power management */ pnp_write_config(dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */ - pnp_write_config(dev, 0x23, 0 ); + pnp_write_config(dev, 0x23, 0); /* Enable SMSC UART 0 */ dev = PNP_DEV(port, SMSCSUPERIO_SP1); -- To view, visit https://review.coreboot.org/29161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d Gerrit-Change-Number: 29161 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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coreboot-gerrit October 2018