Martin Roth has posted comments on this change. ( https://review.coreboot.org/29158 )
Change subject: Macro for adding raw integer into CBFS.
......................................................................
Patch Set 1:
How is this different from the cbfstool add-int command?
add-int [-r image,regions] -i INTEGER -n NAME [-b base] Add a raw 64-bit integer value
--
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Gerrit-Change-Id: Id82950031063e1b0ceee80fff0553ea93dfa331a
Gerrit-Change-Number: 29158
Gerrit-PatchSet: 1
Gerrit-Owner: Zheng Bao <fishbaozi(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Martin Roth <martinroth(a)google.com>
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Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29156
Change subject: amd/stoneyridge/include/soc: GPIO control a mux base addresses double defined
......................................................................
amd/stoneyridge/include/soc: GPIO control a mux base addresses double defined
GPIO control a mux base addresses are defined within MMIO definitions
and again bellow as GPIO specific base addresses. Eliminate those within
MMIO bases.
BUG=b:117754420
TEST=Build grunt.
Change-Id: I53f7cf17d6267e6f8daa650b5f864bab688dc3f0
Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com>
---
M src/soc/amd/stoneyridge/acpi/gpio_lib.asl
M src/soc/amd/stoneyridge/include/soc/iomap.h
2 files changed, 1 insertion(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/29156/1
diff --git a/src/soc/amd/stoneyridge/acpi/gpio_lib.asl b/src/soc/amd/stoneyridge/acpi/gpio_lib.asl
index fbd6525..a2ea1ac 100644
--- a/src/soc/amd/stoneyridge/acpi/gpio_lib.asl
+++ b/src/soc/amd/stoneyridge/acpi/gpio_lib.asl
@@ -19,7 +19,7 @@
Method (GPAD, 0x1)
{
/* Arg0 - GPIO pin number */
- Return (Add(Multiply(Arg0, 4), GPIO_CONTROL_BASE))
+ Return (Add(Multiply(Arg0, 4), AMD_GPIO_CONTROL))
}
/* Read pin control dword */
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h
index beb2bc8..128318c 100644
--- a/src/soc/amd/stoneyridge/include/soc/iomap.h
+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h
@@ -37,9 +37,7 @@
#define APU_SMI_BASE 0xfed80200
#define PM_MMIO_BASE 0xfed80300
#define BIOSRAM_MMIO_BASE 0xfed80500
-#define IOMUX_MMIO_BASE 0xfed80d00
#define MISC_MMIO_BASE 0xfed80e00
-#define GPIO_CONTROL_BASE 0xfed81500
#define XHCI_ACPI_PM_MMIO_BASE 0xfed81c00
#define AOAC_MMIO_BASE 0xfed81e00
--
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Gerrit-Change-Id: I53f7cf17d6267e6f8daa650b5f864bab688dc3f0
Gerrit-Change-Number: 29156
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>
Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29154
Change subject: soc/amd/stoneyridge/smi.c :Prefer using '"%s...", __func__'
......................................................................
soc/amd/stoneyridge/smi.c :Prefer using '"%s...", __func__'
In function smm_setup_structures(), the function name used in a print string.
Use __func__ instead.
BUG=b:117642170
TEST=Build grunt.
Change-Id: Icac5ea997289ef75fb246a09715cbca4442a57f4
Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com>
---
M src/soc/amd/stoneyridge/smi.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/29154/1
diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c
index 1d2dbc8..d21c70e 100644
--- a/src/soc/amd/stoneyridge/smi.c
+++ b/src/soc/amd/stoneyridge/smi.c
@@ -25,7 +25,7 @@
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
{
- printk(BIOS_DEBUG, "smm_setup_structures STUB!!!\n");
+ printk(BIOS_DEBUG, "%s STUB!!!\n", __func__);
}
/** Set the EOS bit and enable SMI generation from southbridge */
--
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Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>
Angel Pons has posted comments on this change. ( https://review.coreboot.org/29152 )
Change subject: soc/amd/stoneyridge: Remove "else" after a return
......................................................................
Patch Set 1: Code-Review+1
--
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Gerrit-Change-Id: Ie8298773ae455dbb1125420ec65df24f3c65eb44
Gerrit-Change-Number: 29152
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Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Comment-Date: Tue, 16 Oct 2018 20:58:40 +0000
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Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/29151
Change subject: drivers/intel/fsp*: Use newly added post codes for memory param prep
......................................................................
drivers/intel/fsp*: Use newly added post codes for memory param prep
This change replaces use of post codes 0x34 and 0x36 in fsp drivers to
instead use POST_MEM_PREINIT_PREP_{START,END} to make it easy to
search from where these post codes are generated during boot flow.
Additionally, it adds POST_MEM_PREINIT_PREP_END to fsp2_0 memory_init
to make it consistent with fsp1_1 memory init.
Change-Id: I307ada1679f212c424e9f7ad2c9d254e24f41fd3
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/drivers/intel/fsp1_1/raminit.c
M src/drivers/intel/fsp1_1/romstage.c
M src/drivers/intel/fsp2_0/memory_init.c
3 files changed, 6 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/29151/1
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index 407a0b6..bca9f71 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -64,7 +64,7 @@
* set to NULL. This indicates that the FSP code will use the UPD
* region in the FSP binary.
*/
- post_code(0x34);
+ post_code(POST_MEM_PREINIT_PREP_START);
fsp_header = params->chipset_context;
vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset +
fsp_header->ImageBase);
@@ -103,7 +103,7 @@
if (IS_ENABLED(CONFIG_MMA))
setup_mma(&memory_init_params);
- post_code(0x36);
+ post_code(POST_MEM_PREINIT_PREP_END);
/* Display the UPD data */
if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c
index b239d86..8e8c24c 100644
--- a/src/drivers/intel/fsp1_1/romstage.c
+++ b/src/drivers/intel/fsp1_1/romstage.c
@@ -344,7 +344,7 @@
/* Transition RAM from off or self-refresh to active */
__weak void raminit(struct romstage_params *params)
{
- post_code(0x34);
+ post_code(POST_MEM_PREINIT_PREP_START);
die("ERROR - No RAM initialization specified!\n");
}
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index dc37eaa..1026c79 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -273,7 +273,7 @@
FSPM_ARCH_UPD *arch_upd;
uint32_t fsp_version;
- post_code(0x34);
+ post_code(POST_MEM_PREINIT_PREP_START);
fsp_version = fsp_memory_settings_version(hdr);
@@ -301,6 +301,8 @@
if (IS_ENABLED(CONFIG_MMA))
setup_mma(&fspm_upd.FspmConfig);
+ post_code(POST_MEM_PREINIT_PREP_END);
+
/* Call FspMemoryInit */
fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset);
fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd);
--
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Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>
Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/29150
Change subject: console/post_codes: Add post codes for memory param prep callback
......................................................................
console/post_codes: Add post codes for memory param prep callback
This change adds two new post codes to indicate start and end of
memory param preparation in callbacks to SoC/mainboard code:
1. 0x34: Start of memory preparation
2. 0x36: End of memory preparation
These post codes are already used in coreboot. This change just
ensures that the codes are defined in post_codes.h for easy lookup.
These post codes are useful if SoC/mainboard decides to do a reset of
the platform before returning back to memory initialization.
Change-Id: I065518caedb7943d960a8a5c8708823b8eb3246d
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/include/console/post_codes.h
1 file changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/29150/1
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index 0277337..f482ae9 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -82,6 +82,22 @@
#define POST_ENTRY_C_START 0x13
/**
+ * \brief Pre-memory init preparation start
+ *
+ * Post code emitted in romstage before making callbacks to allow SoC/mainboard
+ * to prepare params for FSP memory init.
+ */
+#define POST_MEM_PREINIT_PREP_START 0x34
+
+/**
+ * \brief Pre-memory init preparation end
+ *
+ * Post code emitted in romstage after returning from SoC/mainboard callbacks
+ * to prepare params for FSP memory init.
+ */
+#define POST_MEM_PREINIT_PREP_END 0x36
+
+/**
* \brief Pre call to RAM stage main()
*
* POSTed right before RAM stage main() is called from c_start.S
--
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