coreboot-gerrit October 2018

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Change in coreboot[master]: ec/google/wilco: Add ACPI SuperIO devices
by Duncan Laurie (Code Review) 16 Oct '18

16 Oct '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/29125 Change subject: ec/google/wilco: Add ACPI SuperIO devices ...................................................................... ec/google/wilco: Add ACPI SuperIO devices Add ACPI devices for the basic SuperIO functionality provided by the EC for PS/2 keyboard, PS/2 mouse (trackpad emulation), and legacy UART. The specific defines to enable these devices should be declared by the mainboard before including this ASL, the same as the Chrome EC behavior. Change-Id: I910940ebf26b8758ab12d695e1eba9c668c640c6 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- A src/ec/google/wilco/acpi/superio.asl 1 file changed, 117 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/29125/1 diff --git a/src/ec/google/wilco/acpi/superio.asl b/src/ec/google/wilco/acpi/superio.asl new file mode 100644 index 0000000..a8cea78 --- /dev/null +++ b/src/ec/google/wilco/acpi/superio.asl @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Scope is \_SB.PCI0.LPCB */ + +Device (SIO) +{ + Name (_UID, 0) + Name (_ADR, 0) + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501")) + Name (_UID, 1) + Name (_ADR, 0) + + Method (_STA, 0, NotSerialized) + { +#ifdef SIO_EC_ENABLE_COM1 + Return (0x0f) +#else + Return (Zero) +#endif + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) + IRQNoFlags () {4} + } + EndDependentFn () + }) + } + + Device (PS2K) + { + Name (_HID, EisaId ("PNP0303")) + Name (_CID, EisaId ("PNP030B")) + Name (_UID, 0) + Name (_ADR, 0) + + Method (_STA, 0, NotSerialized) + { +#ifdef SIO_EC_ENABLE_PS2K + Return (0x0f) +#else + Return (Zero) +#endif + } + + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQ (Edge, ActiveHigh, Exclusive) {1} + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQ (Edge, ActiveHigh, Exclusive) {1} + } + EndDependentFn () + }) + } + + Device (PS2M) + { + Name (_HID, EisaId ("PNP0F13")) + Name (_UID, 0) + Name (_ADR, 0) + + Method (_STA, 0, NotSerialized) + { +#ifdef SIO_EC_ENABLE_PS2M + Return (0x0f) +#else + Return (Zero) +#endif + } + + Name (_CRS, ResourceTemplate() + { + IRQ (Edge, ActiveHigh, Exclusive) {12} + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) { + IRQ (Edge, ActiveHigh, Exclusive) {12} + } + EndDependentFn () + }) + } +} -- To view, visit https://review.coreboot.org/29125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I910940ebf26b8758ab12d695e1eba9c668c640c6 Gerrit-Change-Number: 29125 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: ec/google/wilco: Add ACPI EC event handlers
by Duncan Laurie (Code Review) 16 Oct '18

16 Oct '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/29124 Change subject: ec/google/wilco: Add ACPI EC event handlers ...................................................................... ec/google/wilco: Add ACPI EC event handlers Add methods to handle ACPI EC events at runtime. Currently only some common events are handled like lid switch and battery info, and the event status is printed for debug on other events. Change-Id: Ic0bd070940c8a2dfa6a251f3464301418bdb69c1 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/ec/google/wilco/acpi/ec.asl A src/ec/google/wilco/acpi/event.asl 2 files changed, 127 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/29124/1 diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index d669854..cddfe3f 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -134,6 +134,7 @@ #include "ec_ram.asl" #include "ac.asl" #include "battery.asl" + #include "event.asl" #include "lid.asl" #include "platform.asl" } diff --git a/src/ec/google/wilco/acpi/event.asl b/src/ec/google/wilco/acpi/event.asl new file mode 100644 index 0000000..b43086c --- /dev/null +++ b/src/ec/google/wilco/acpi/event.asl @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* ACPI_POWER_RECORD */ +Name (ECPR, 0) + +Method (ECQP, 0, Serialized) +{ + Local0 = R (APWR) + Local1 = Local0 ^ ECPR + ECPR = Local0 + + If (EBIT (APAC, Local1)) { + Printf ("AC Power Status Changed") + Notify (AC, 0x80) + } + + If (EBIT (APB1, Local1)) { + If (EBIT (APB1, Local0)) { + Printf ("BAT0 Inserted") + Notify (BAT0, 0x81) + } Else { + Printf ("BAT0 Removed") + Notify (BAT0, 0x80) + Notify (BAT0, 0x81) + } + } + + If (EBIT (APC1, Local1)) { + Printf ("BAT0 Status Change") + Notify (BAT0, 0x80) + } +} + +/* Handle events in PmEv1 */ +Method (ECQ1, 1, Serialized) +{ + /* Power button pressed */ + If (EBIT (E1PB, Arg0)) { + Printf ("Power Button Event") + /* Do not notify \_SB.PWRB here to prevent double event */ + } + + /* LID state changed */ + If (EBIT (E1LD, Arg0)) { + Printf ("Lid State Changed") + Notify (^LID, 0x80) + } + + /* Power Event */ + If (EBIT (E1PW, Arg0)) { + Printf ("Power Event") + ECQP () + } + + /* Sleep Button */ + If (EBIT (E1SB, Arg0)) { + Printf ("Sleep Button") + } +} + +/* Handle events in PmEv2 */ +Method (ECQ2, 1, Serialized) +{ + Printf ("EVT2: %o", Arg0) +} + +/* Handle events in PmEv3 */ +Method (ECQ3, 1, Serialized) +{ + Printf ("EVT3: %o", Arg0) +} + +/* Handle events in PmEv4 */ +Method (ECQ4, 1, Serialized) +{ + Printf ("EVT4: %o", Arg0) +} + +/* Handle QuickSet events */ +Method (ECQS, 1, Serialized) +{ + Printf ("QS EVENT %o", Arg0) +} + +/* Process all events */ +Method (_Q66, 0, Serialized) +{ + Local0 = R (EVT1) + If (Local0) { + ECQ1 (Local0) + } + + Local0 = R (EVT2) + If (Local0) { + ECQ2 (Local0) + } + + Local0 = R (EVT3) + If (Local0) { + ECQ3 (Local0) + } + + Local0 = R (EVT4) + If (Local0) { + ECQ4 (Local0) + } + + Local0 = R (QSEC) + For (Local1 = 0, Local1 < Local0, Local1++) { + ECQS (R (QSEB)) + } +} -- To view, visit https://review.coreboot.org/29124 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic0bd070940c8a2dfa6a251f3464301418bdb69c1 Gerrit-Change-Number: 29124 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: ec/google/wilco: Add ACPI battery and AC objects
by Duncan Laurie (Code Review) 16 Oct '18

16 Oct '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/29123 Change subject: ec/google/wilco: Add ACPI battery and AC objects ...................................................................... ec/google/wilco: Add ACPI battery and AC objects Add the expected objects (_BST, _BIF, _BIX) for reading battery information and status from the embedded controller, and the expected objects for reporting AC power status. The battery was tested by booting with a battery attached and checking that it is present in /sys/class/power_supply/BAT0 and that the values are consistent and within expected ranges. The AC device was tested by checking the AC status in sysfs when AC is inserted or removed while the system is running. Change-Id: Ie996891c383c9e990736690aef9795512ad6d35a Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- A src/ec/google/wilco/acpi/ac.asl A src/ec/google/wilco/acpi/battery.asl M src/ec/google/wilco/acpi/ec.asl 3 files changed, 391 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/29123/1 diff --git a/src/ec/google/wilco/acpi/ac.asl b/src/ec/google/wilco/acpi/ac.asl new file mode 100644 index 0000000..5d51ce4 --- /dev/null +++ b/src/ec/google/wilco/acpi/ac.asl @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (AC) +{ + Name (_HID, "ACPI0003") + Name (_UID, 1) + Name (_PCL, Package () { \_SB, BAT0, BAT1 }) + + Method (_STA) + { + Return (0xf) + } + + Method (_PSR) + { + Return (R (ACEX)) + } +} diff --git a/src/ec/google/wilco/acpi/battery.asl b/src/ec/google/wilco/acpi/battery.asl new file mode 100644 index 0000000..dd1f69a --- /dev/null +++ b/src/ec/google/wilco/acpi/battery.asl @@ -0,0 +1,357 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Mutex (BATM, 0) + +Method (ESTA, 1, Serialized) +{ + /* Check battery presence */ + If (Arg0 == 1) { + Local0 = R (BTEX) + } ElseIf (Arg0 == 2) { + Local0 = R (P3B2) + } Else { + Local0 = Zero + } + + /* Indicate battery is present */ + If (Local0) { + Return (0x1f) + } Else { + Return (0xf) + } +} + +Name (BSTM, 0x01) /* Battery Model String */ +Name (BSTC, 0x02) /* Battery Chemistry String */ +Name (BSTG, 0x03) /* Battery Manufacturer String */ + +/* + * Read a battery string from the EC + * Arg0 = Battery String ID + * BSTM = Model + * BSTC = Chemical + * BSTG = Manufacturer + */ +Method (BSTR, 1, Serialized) +{ + /* Max string length */ + Local0 = 32 + + /* Select battery string */ + W (SSEL, Arg0) + + /* Fill buffer until NUL or max string length is read */ + Name (IBUF, Buffer (Local0 + One) {}) + For (Local1 = Zero, Local1 < Local0, Local1++) { + Local2 = R (BSBS) + If (!Local2) { + Break + } + IBUF[Local1] = Local2 + } + + /* Truncate and NUL terminate */ + Local1++ + Name (OBUF, Buffer (Local1) {}) + OBUF = Concatenate (IBUF, Zero) + + Return (OBUF) +} + +/* + * Handle Battery Status + * Arg0 = Battery Number + * Arg1 = _BST package + */ +Method (EBST, 2, Serialized) +{ + If (Acquire (BATM, 1000)) { + Return (Arg1) + } + + /* Select battery */ + W (BSEL, Arg0) + + /* 0: Battery State */ + Arg1[0] = R (BCST) + + /* 1: Battery Present Rate */ + Local0 = R (BCCL) + If (!Local0) { + Local0++ + } ElseIf (R (ACEX)) { + If (Local0 & 0x8000) { + Local0 = Ones + } + } Else { + If (Local0 & 0x8000) { + Local0 = 0 - Local0 + Local0 &= 0xffff + } Else { + Local0 = Ones + } + } + Arg1[1] = Local0 + + /* 2: Battery Remaining Capacity */ + Arg1[2] = R (BCYL) + + /* 3: Battery Present Voltage */ + Arg1[3] = R (BCVL) + + Release (BATM) + Return (Arg1) +} + +/* + * Handle Battery Info + * Arg0 = Battery Number + * Arg1 = _BIF package + */ +Method (EBIF, 2, Serialized) +{ + If (Acquire (BATM, 1000)) { + Return (Arg1) + } + + /* Select battery */ + W (BSEL, Arg0) + + /* Design Capacity */ + Local0 = R (BSCL) + Arg1[1] = Local0 + + /* Last Full Charge Capacity */ + Arg1[2] = R (BSFL) + + /* Design Voltage */ + Arg1[4] = R (BSVL) + + /* Design Warning Capacity */ + Arg1[5] = (Local0 * 10) / 100 + + /* Design Low Capacity */ + Arg1[6] = (Local0 * 33) / 100 + + /* Granularity */ + Arg1[7] = Local0 / 100 + Arg1[8] = Local0 / 100 + + /* Battery Model Number */ + Arg1[9] = BSTR (BSTM) + + /* Battery Serial Number */ + Arg1[10] = ToDecimalString (R (BSSL)) + + /* Battery Type */ + Arg1[11] = BSTR (BSTC) + + /* Battery Manufacturer Name */ + Arg1[12] = BSTR (BSTG) + + Release (BATM) + Return (Arg1) +} + +/* + * Handle Battery Info Extended + * Arg0 = Battery Number + * Arg1 = _BIX package + */ +Method (EBIX, 2, Serialized) +{ + If (Acquire (BATM, 1000)) { + Return (Arg1) + } + + /* Select battery */ + W (BSEL, Arg0) + + /* Design Capacity */ + Local0 = R (BSCL) + Arg1[2] = Local0 + + /* Last Full Charge Capacity */ + Arg1[3] = R (BSFL) + + /* Design Voltage */ + Arg1[5] = R (BSVL) + + /* Design Warning Capacity */ + Arg1[6] = (Local0 * 10) / 100 + + /* Design Low Capacity */ + Arg1[7] = (Local0 * 33) / 100 + + /* Cycle Count */ + Arg1[8] = R (BCCY) + + /* Granularity */ + Arg1[14] = Local0 / 100 + Arg1[15] = Local0 / 100 + + /* Battery Model Number */ + Arg1[16] = BSTR (BSTM) + + /* Battery Serial Number */ + Arg1[17] = ToDecimalString (R (BSSL)) + + /* Battery Type */ + Arg1[18] = BSTR (BSTC) + + /* Battery Manufacturer Name */ + Arg1[19] = BSTR (BSTG) + + Release (BATM) + Return (Arg1) +} + +Device (BAT0) +{ + Name (_HID, EisaId ("PNP0C0A")) + Name (_UID, 1) + Name (_PCL, Package () { \_SB }) + + Name (PBIF, Package () { + 0x00000001, /* 0x00: Power Unit: mAh */ + 0xFFFFFFFF, /* 0x01: Design Capacity */ + 0xFFFFFFFF, /* 0x02: Last Full Charge Capacity */ + 0x00000001, /* 0x03: Battery Technology: Rechargeable */ + 0xFFFFFFFF, /* 0x04: Design Voltage */ + 0x00000003, /* 0x05: Design Capacity of Warning */ + 0xFFFFFFFF, /* 0x06: Design Capacity of Low */ + 0x00000001, /* 0x07: Capacity Granularity 1 */ + 0x00000001, /* 0x08: Capacity Granularity 2 */ + "", /* 0x09: Model Number */ + "", /* 0x0a: Serial Number */ + "LION", /* 0x0b: Battery Type */ + "" /* 0x0c: OEM Information */ + }) + + Name (PBIX, Package () { + 0x00000000, /* 0x00: Revision */ + 0x00000001, /* 0x01: Power Unit: mAh */ + 0xFFFFFFFF, /* 0x02: Design Capacity */ + 0xFFFFFFFF, /* 0x03: Last Full Charge Capacity */ + 0x00000001, /* 0x04: Battery Technology: Rechargeable */ + 0xFFFFFFFF, /* 0x05: Design Voltage */ + 0x00000003, /* 0x06: Design Capacity of Warning */ + 0xFFFFFFFF, /* 0x07: Design Capacity of Low */ + 0x00000000, /* 0x08: Cycle Count */ + 0x00018000, /* 0x09: Measurement Accuracy (98.3%?) */ + 0x000001F4, /* 0x0a: Max Sampling Time (500ms) */ + 0x0000000a, /* 0x0b: Min Sampling Time (10ms) */ + 0xFFFFFFFF, /* 0x0c: Max Averaging Interval */ + 0xFFFFFFFF, /* 0x0d: Min Averaging Interval */ + 0x00000001, /* 0x0e: Capacity Granularity 1 */ + 0x00000001, /* 0x0f: Capacity Granularity 2 */ + "", /* 0x10 Model Number */ + "", /* 0x11: Serial Number */ + "LION", /* 0x12: Battery Type */ + "" /* 0x13: OEM Information */ + }) + + Name (PBST, Package () { + 0x00000000, /* 0x00: Battery State */ + 0xFFFFFFFF, /* 0x01: Battery Present Rate */ + 0xFFFFFFFF, /* 0x02: Battery Remaining Capacity */ + 0xFFFFFFFF, /* 0x03: Battery Present Voltage */ + }) + + Method (_STA, 0, Serialized) + { + Return (ESTA (_UID)) + } + + Method (_BST, 0, Serialized) + { + Return (EBST (_UID, PBST)) + } + + Method (_BIF, 0, Serialized) + { + Return (EBIF (_UID, PBIF)) + } +} + +Device (BAT1) +{ + Name (_HID, EisaId ("PNP0C0A")) + Name (_UID, 2) + Name (_PCL, Package () { \_SB }) + + Name (PBIF, Package () { + 0x00000001, /* 0x00: Power Unit: mAh */ + 0xFFFFFFFF, /* 0x01: Design Capacity */ + 0xFFFFFFFF, /* 0x02: Last Full Charge Capacity */ + 0x00000001, /* 0x03: Battery Technology: Rechargeable */ + 0xFFFFFFFF, /* 0x04: Design Voltage */ + 0x00000003, /* 0x05: Design Capacity of Warning */ + 0xFFFFFFFF, /* 0x06: Design Capacity of Low */ + 0x00000001, /* 0x07: Capacity Granularity 1 */ + 0x00000001, /* 0x08: Capacity Granularity 2 */ + "", /* 0x09: Model Number */ + "", /* 0x0a: Serial Number */ + "LION", /* 0x0b: Battery Type */ + "" /* 0x0c: OEM Information */ + }) + + Name (PBIX, Package () { + 0x00000000, /* 0x00: Revision */ + 0x00000001, /* 0x01: Power Unit: mAh */ + 0xFFFFFFFF, /* 0x02: Design Capacity */ + 0xFFFFFFFF, /* 0x03: Last Full Charge Capacity */ + 0x00000001, /* 0x04: Battery Technology: Rechargeable */ + 0xFFFFFFFF, /* 0x05: Design Voltage */ + 0x00000003, /* 0x06: Design Capacity of Warning */ + 0xFFFFFFFF, /* 0x07: Design Capacity of Low */ + 0x00000000, /* 0x08: Cycle Count */ + 0x00018000, /* 0x09: Measurement Accuracy (98.3%?) */ + 0x000001F4, /* 0x0a: Max Sampling Time (500ms) */ + 0x0000000a, /* 0x0b: Min Sampling Time (10ms) */ + 0xFFFFFFFF, /* 0x0c: Max Averaging Interval */ + 0xFFFFFFFF, /* 0x0d: Min Averaging Interval */ + 0x00000001, /* 0x0e: Capacity Granularity 1 */ + 0x00000001, /* 0x0f: Capacity Granularity 2 */ + "", /* 0x10 Model Number */ + "", /* 0x11: Serial Number */ + "LION", /* 0x12: Battery Type */ + "" /* 0x13: OEM Information */ + }) + + Name (PBST, Package () { + 0x00000000, /* 0x00: Battery State */ + 0xFFFFFFFF, /* 0x01: Battery Present Rate */ + 0xFFFFFFFF, /* 0x02: Battery Remaining Capacity */ + 0xFFFFFFFF, /* 0x03: Battery Present Voltage */ + }) + + Method (_STA, 0, Serialized) + { + Return (ESTA (^_UID)) + } + + Method (_BST, 0, Serialized) + { + Return (EBST (^_UID, PBST)) + } + + Method (_BIF, 0, Serialized) + { + Return (EBIF (^_UID, PBIF)) + } +} diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl index 8197c54..d669854 100644 --- a/src/ec/google/wilco/acpi/ec.asl +++ b/src/ec/google/wilco/acpi/ec.asl @@ -132,6 +132,8 @@ #include "ec_dev.asl" #include "ec_ram.asl" + #include "ac.asl" + #include "battery.asl" #include "lid.asl" #include "platform.asl" } -- To view, visit https://review.coreboot.org/29123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie996891c383c9e990736690aef9795512ad6d35a Gerrit-Change-Number: 29123 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: ec/google/wilco: Add ACPI EC infrastructure
by Duncan Laurie (Code Review) 16 Oct '18

16 Oct '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/29122 Change subject: ec/google/wilco: Add ACPI EC infrastructure ...................................................................... ec/google/wilco: Add ACPI EC infrastructure Add the base ACPI support for the Wilco embedded controller, using ASL 2.0 syntax throughout. This includes the EC device and its resources, as well as the layout for the EC RAM and the functions needed to read and write to the EC RAM. The EC RAM address space is typically read/write, and so the ACPI EC device expects that a defined Field can be read and/or written. With this EC the read and write address spaces are different. For example, a read from address zero will return data that is unrelated to what a write to address zero expects. This makes using a typical OperationRegion to describe the EC RAM address space somewhat impracticle, since field definitions would overlap. Instead, methods are provided for reading and writing to an EC RAM offset, and the EC RAM layout is defined as a Package that describes offset+mask for read or write fields within the EC RAM. Change-Id: If8cfdf2633db1ccad4306fe877180ba197ee7414 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- A src/ec/google/wilco/acpi/ec.asl A src/ec/google/wilco/acpi/ec_dev.asl A src/ec/google/wilco/acpi/ec_ram.asl A src/ec/google/wilco/acpi/lid.asl A src/ec/google/wilco/acpi/platform.asl 5 files changed, 381 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/29122/1 diff --git a/src/ec/google/wilco/acpi/ec.asl b/src/ec/google/wilco/acpi/ec.asl new file mode 100644 index 0000000..8197c54 --- /dev/null +++ b/src/ec/google/wilco/acpi/ec.asl @@ -0,0 +1,137 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (EC0) +{ + Name (_HID, EisaId ("PNP0C09")) + Name (_UID, 1) + Name (_GPE, EC_SCI_GPI) + Name (_STA, 0xf) + + Name (_CRS, ResourceTemplate() { + IO (Decode16, + CONFIG_EC_BASE_ACPI_DATA, + CONFIG_EC_BASE_ACPI_DATA, + 4, 4) + IO (Decode16, + CONFIG_EC_BASE_ACPI_COMMAND, + CONFIG_EC_BASE_ACPI_COMMAND, + 4, 4) + }) + + /* Handle registration of EmbeddedControl region */ + Name (EREG, Zero) + OperationRegion (ERAM, EmbeddedControl, 0, 0xff) + Method (_REG, 2) + { + /* Indicate region is registered */ + EREG = Arg1 + + /* Store initial value for power status */ + ECPR = R (APWR) + + /* Indicate to EC that OS is ready for queries */ + W (ERDY, One) + + /* Tell EC to stop emulating PS/2 mouse */ + W (PS2M, Zero) + } + + /* + * Find bitmask for field + * Arg0 = EC field structure + * Arg1 = Value + */ + Method (EBIT, 2, NotSerialized) + { + Local0 = DeRefOf (Arg0[1]) /* Mask */ + Local1 = Arg1 & Local0 + FindSetRightBit (Local0, Local2) + If (Local2) { + Local1 >>= Local2 - 1 + } + Return (Local1) + } + + /* + * READ or WRITE from EC region + * Arg0 = EC field structure + * Arg1 = Value to write + */ + Method (ECRW, 2, Serialized) + { + If (!EREG) { + Return (Zero) + } + + Local0 = DeRefOf (Arg0[0]) /* Byte offset */ + Local1 = DeRefOf (Arg0[1]) /* Mask */ + Local2 = DeRefOf (Arg0[2]) /* Read/Write */ + + OperationRegion (ERAM, EmbeddedControl, Local0, 2) + Field (ERAM, ByteAcc, Lock, WriteAsZeros) + { + BYT1, 8, + BYT2, 8, + } + + If (Local2 == RD) { + /* Read first byte */ + Local3 = BYT1 + + /* Read second byte if needed */ + FindSetLeftBit (Local1, Local4) + If (Local4 > 8) { + Local4 = BYT2 + Local4 <<= 8 + Local3 |= Local4 + } + + Local5 = EBIT (Arg0, Local3) + Printf ("ECRD %o = %o", Local0, Local5) + Return (Local5) + } ElseIf (Local2 == WR) { + /* Write byte */ + Printf ("ECWR %o = %o", Local0, Arg1) + BYT1 = Arg1 + } + Return (Zero) + } + + /* + * Read a field from EC + * Arg0 = EC field structure + */ + Method (R, 1, Serialized) + { + Return (ECRW (Arg0, Zero)) + } + + /* + * Write value to a field from EC + * Arg0 = EC field structure + * Arg1 = Value to write + */ + Method (W, 2, Serialized) + { + Return (ECRW (Arg0, Arg1)) + } + + #include "ec_dev.asl" + #include "ec_ram.asl" + #include "lid.asl" + #include "platform.asl" +} diff --git a/src/ec/google/wilco/acpi/ec_dev.asl b/src/ec/google/wilco/acpi/ec_dev.asl new file mode 100644 index 0000000..0519ff0 --- /dev/null +++ b/src/ec/google/wilco/acpi/ec_dev.asl @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (WLCO) +{ + Name (_HID, "GOOG000C") + Name (_UID, 1) + Name (_DDN, "Wilco EC Command Device") + + Method (_STA) + { + Return (0xf) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, + CONFIG_EC_BASE_HOST_DATA, + CONFIG_EC_BASE_HOST_DATA, + 4, 4) + IO (Decode16, + CONFIG_EC_BASE_HOST_COMMAND, + CONFIG_EC_BASE_HOST_COMMAND, + 4, 4) + IO (Decode16, + CONFIG_EC_BASE_PACKET, + CONFIG_EC_BASE_PACKET, + 16, 16) + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + IO (Decode16, + CONFIG_EC_BASE_HOST_DATA, + CONFIG_EC_BASE_HOST_DATA, + 4, 4) + IO (Decode16, + CONFIG_EC_BASE_HOST_COMMAND, + CONFIG_EC_BASE_HOST_COMMAND, + 4, 4) + IO (Decode16, + CONFIG_EC_BASE_PACKET, + CONFIG_EC_BASE_PACKET, + 16, 16) + } + EndDependentFn () + }) +} diff --git a/src/ec/google/wilco/acpi/ec_ram.asl b/src/ec/google/wilco/acpi/ec_ram.asl new file mode 100644 index 0000000..ffa0c9f --- /dev/null +++ b/src/ec/google/wilco/acpi/ec_ram.asl @@ -0,0 +1,127 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Name (RD, 0) +Name (WR, 1) + +/* + * EC RAM READ + */ + +Name (P1ST, Package () { 0x00, 0xff, RD }) /* PmSt1 */ +Name (P1AC, Package () { 0x00, 0x01, RD }) /* PmSt1_AC_AVAIL */ +Name (P1BA, Package () { 0x00, 0x02, RD }) /* PmSt1_BAT_AVAIL */ +Name (P1L1, Package () { 0x00, 0x04, RD }) /* PmSt1_LOBAT1 */ +Name (P1L2, Package () { 0x00, 0x08, RD }) /* PmSt1_LOBAT2 */ +Name (P1LC, Package () { 0x00, 0x10, RD }) /* PmSt1_LID_CL */ +Name (P1OT, Package () { 0x00, 0x40, RD }) /* PmSt1_OVERTEMP */ + +Name (P2ST, Package () { 0x01, 0xff, RD }) /* PmSt2 */ +name (P2PB, Package () { 0x01, 0x04, RD }) /* PmSt2_PWRB_PRESSED */ + +Name (P3ST, Package () { 0x02, 0xff, RD }) /* PmSt3 */ +Name (P3B1, Package () { 0x02, 0x04, RD }) /* PmSt3_BAT1_PRES */ +Name (P3B2, Package () { 0x02, 0x08, RD }) /* PmSt3_BAT2_PRES */ +Name (P3FB, Package () { 0x02, 0x40, RD }) /* PmSt3_FORCE_BOM */ +Name (P3FT, Package () { 0x02, 0x80, RD }) /* PmSt3_FORCE_THROTTLE */ + +Name (P4ST, Package () { 0x03, 0xff, RD }) /* PmSt4 */ +Name (P4C1, Package () { 0x03, 0x01, RD }) /* PmSt4_BAT1_CHG */ +Name (P4C2, Package () { 0x03, 0x02, RD }) /* PmSt4_BAT2_CHG */ +Name (P4P1, Package () { 0x03, 0x04, RD }) /* PmSt4_BAT1_PWR */ +Name (P4P2, Package () { 0x03, 0x08, RD }) /* PmSt4_BAT2_PWR */ +Name (P4BI, Package () { 0x03, 0x10, RD }) /* PmSt4_BAT_IDLE */ +Name (P4PS, Package () { 0x03, 0x20, RD }) /* PmSt4_PANEL_STATE */ +Name (P4CD, Package () { 0x03, 0x40, RD }) /* PmSt4_BATD_CHG */ + +Name (P5ST, Package () { 0x04, 0xff, RD }) /* PmSt5 */ +Name (P5U1, Package () { 0x04, 0x01, RD }) /* PmSt5_BAT1_UPDATE */ + +Name (P6ST, Package () { 0x05, 0xff, RD }) /* PmSt6 */ +Name (P6AC, Package () { 0x05, 0x08, RD }) /* PmSt6_AC_UPDATE */ + +Name (ACEX, Package () { 0x06, 0x01, RD }) /* AC Present */ +Name (BTEX, Package () { 0x06, 0x02, RD }) /* Battery Present */ +Name (BTSC, Package () { 0x06, 0x04, RD }) /* Battery Status Changed */ + +Name (EVT1, Package () { 0x07, 0xff, RD }) /* Event 1 */ +Name (E1PB, Package () { 0x07, 0x01, RD }) /* Power Button */ +Name (E1LD, Package () { 0x07, 0x04, RD }) /* Lid */ +Name (E1PW, Package () { 0x07, 0x08, RD }) /* Power */ +Name (E1SB, Package () { 0x07, 0x40, RD }) /* Sleep Button */ +Name (E1SS, Package () { 0x07, 0x80, RD }) /* SMI-SCI */ + +Name (EVT2, Package () { 0x08, 0xff, RD }) /* Event 2 */ +Name (E2BS, Package () { 0x08, 0x02, RD }) /* BSS */ +Name (E2OR, Package () { 0x08, 0x04, RD }) /* Orientation */ +Name (E2QS, Package () { 0x08, 0x08, RD }) /* Quickset */ +Name (E2PN, Package () { 0x08, 0x20, RD }) /* Panel */ +Name (E2DP, Package () { 0x08, 0x40, RD }) /* Display Port */ +Name (E2VT, Package () { 0x08, 0x80, RD }) /* Video Throttle */ + +Name (WAKE, Package () { 0x09, 0xff, RD }) /* Wake Events */ +Name (WPWB, Package () { 0x09, 0x01, RD }) /* Wake: Power Button */ +Name (WLID, Package () { 0x09, 0x02, RD }) /* Wake: Lid */ +Name (WUSB, Package () { 0x09, 0x04, RD }) /* Wake: USB */ +Name (WPME, Package () { 0x09, 0x10, RD }) /* Wake: PME */ +Name (WRTC, Package () { 0x09, 0x20, RD }) /* Wake: RTC */ +Name (WBAT, Package () { 0x09, 0x80, RD }) /* Wake: Low Battery */ + +Name (EVT3, Package () { 0x0b, 0xff, RD }) /* Event 3 */ +Name (EVT4, Package () { 0x0c, 0xff, RD }) /* Event 4 */ + +Name (BCST, Package () { 0x10, 0xff, RD }) /* BCACHE: BST */ +Name (BCRS, Package () { 0x11, 0xff, RD }) /* BCACHE: RSOC */ +Name (BCCL, Package () { 0x12, 0xffff, RD }) /* BCACHE: Current */ +Name (BCVL, Package () { 0x14, 0xffff, RD }) /* BCACHE: Voltage */ +Name (BCYL, Package () { 0x16, 0xffff, RD }) /* BCACHE: Capacity */ +Name (BCTL, Package () { 0x18, 0xffff, RD }) /* BCACHE: Temp */ +Name (BCML, Package () { 0x1a, 0xffff, RD }) /* BCACHE: Ma */ +Name (BSRL, Package () { 0x1c, 0xffff, RD }) /* BSTATIC: Max Error Low */ +Name (BSFL, Package () { 0x1e, 0xffff, RD }) /* BSTATIC: Full Cap Low */ +Name (BSCL, Package () { 0x20, 0xffff, RD }) /* BSTATIC: Design Cap Low */ +Name (BSVL, Package () { 0x22, 0xffff, RD }) /* BSTATIC: Design Volt Low */ +Name (BSDL, Package () { 0x24, 0xffff, RD }) /* BSTATIC: Mfg Date Low */ +Name (BSSL, Package () { 0x26, 0xffff, RD }) /* BSTATIC: Serial Number Low */ +Name (BSMN, Package () { 0x28, 0xff, RD }) /* BSTATIC: Manufacturer Name */ +Name (BSDC, Package () { 0x29, 0xff, RD }) /* BSTATIC: Device Chemistry */ +Name (BSBS, Package () { 0x2a, 0xff, RD }) /* BSTATIC: Battery String */ + +Name (QSEC, Package () { 0x2b, 0xff, RD }) /* QuickSet Event Count */ +Name (QSEB, Package () { 0x2c, 0xff, RD }) /* QuickSet Event Byte */ + +Name (ORST, Package () { 0x39, 0xff, RD }) /* Orientation State */ +Name (OREV, Package () { 0x3a, 0xff, RD }) /* Orientation Events */ +Name (OECH, Package () { 0x3a, 0x01, RD }) /* Event: Orientation */ +Name (OERL, Package () { 0x3a, 0x02, RD }) /* Event: Rotation Lock */ + +Name (BCCY, Package () { 0x3e, 0xffff, RD }) /* BCACHE: Cycle Count */ + +Name (APWR, Package () { 0x47, 0xff, RD }) /* POWER: Full Status */ +Name (APAC, Package () { 0x47, 0x01, RD }) /* POWER: AC */ +Name (APB1, Package () { 0x47, 0x02, RD }) /* POWER: Main Battery */ +Name (APC1, Package () { 0x47, 0x04, RD }) /* POWER: Main Batt Status */ + +/* + * EC RAM WRITE + */ + +Name (FPTS, Package () { 0x02, 0xff, WR }) /* EC _PTS */ +Name (BSEL, Package () { 0x03, 0xff, WR }) /* Battery Select */ +Name (SSEL, Package () { 0x04, 0xff, WR }) /* Battery String Select */ +Name (ERDY, Package () { 0x05, 0xff, WR }) /* EC Ready */ +Name (FWAK, Package () { 0x06, 0xff, WR }) /* EC _WAK */ +Name (PS2M, Package () { 0x20, 0xff, WR }) /* EC PS/2 Mouse Emulation */ diff --git a/src/ec/google/wilco/acpi/lid.asl b/src/ec/google/wilco/acpi/lid.asl new file mode 100644 index 0000000..818e135 --- /dev/null +++ b/src/ec/google/wilco/acpi/lid.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (LID) +{ + Name (_HID, EisaId ("PNP0C0D")) + Name (_UID, 1) + Name (_STA, 0xf) + + Method (_LID, 0, NotSerialized) + { + Return (R (P1LC)) + } +} diff --git a/src/ec/google/wilco/acpi/platform.asl b/src/ec/google/wilco/acpi/platform.asl new file mode 100644 index 0000000..802c8f7 --- /dev/null +++ b/src/ec/google/wilco/acpi/platform.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Call from \_SB._PTS() */ +Method (PTS, 1, Serialized) +{ + Printf ("EC _PTS") + W (FPTS, Arg0) +} + +/* Call from \_SB._WAK() */ +Method (WAK, 1, Serialized) +{ + Printf ("EC _WAK") + W (FWAK, Arg0) +} -- To view, visit https://review.coreboot.org/29122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If8cfdf2633db1ccad4306fe877180ba197ee7414 Gerrit-Change-Number: 29122 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: ec/google/wilco: Add a bootblock function for early init
by Duncan Laurie (Code Review) 16 Oct '18

16 Oct '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/29121 Change subject: ec/google/wilco: Add a bootblock function for early init ...................................................................... ec/google/wilco: Add a bootblock function for early init Add a function for use in bootblock stage that performs early init of the EC, in particular setting it up for UART passthrough so a legacy serial port can be used by the host. This needs to be called by the mainboard that intends to use it in bootblock in order for the UART to be available in later stages. Some of the PNP style programming may look odd, but it is following the EC specification which is not entirely standard. This code has been tested on a board with this EC and it is functional. Change-Id: I9d6935a9fdf0d7290a94bf2ee565ef2a7c00ecc7 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/ec/google/wilco/Makefile.inc A src/ec/google/wilco/bootblock.c A src/ec/google/wilco/bootblock.h 3 files changed, 75 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/29121/1 diff --git a/src/ec/google/wilco/Makefile.inc b/src/ec/google/wilco/Makefile.inc index 33eefd5..2e1c0d4 100644 --- a/src/ec/google/wilco/Makefile.inc +++ b/src/ec/google/wilco/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_EC_GOOGLE_WILCO),y) +bootblock-y += bootblock.c ramstage-y += chip.c commands.c mailbox.c smm-y += commands.c mailbox.c smihandler.c diff --git a/src/ec/google/wilco/bootblock.c b/src/ec/google/wilco/bootblock.c new file mode 100644 index 0000000..dadc5c9 --- /dev/null +++ b/src/ec/google/wilco/bootblock.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/pnp_def.h> +#include <swab.h> + +#include "bootblock.h" + +#define PNP_CFG_IDX 0x2e +#define PNP_LDN_SERIAL 0x0d + +static void pnp_enter_conf_state(pnp_devfn_t dev) +{ + outb(0x55, PNP_CFG_IDX); + outb(0x55, PNP_CFG_IDX); +} + +static void pnp_exit_conf_state(pnp_devfn_t dev) +{ + outb(0xaa, PNP_CFG_IDX); +} + +static void wilco_ec_serial_init(void) +{ + pnp_devfn_t dev = PNP_DEV(PNP_CFG_IDX, PNP_LDN_SERIAL); + + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); + pnp_set_iobase(dev, PNP_IDX_IO1, cpu_to_be16(CONFIG_TTYS0_BASE)); + pnp_write_config(dev, PNP_IDX_IO0, 1); + pnp_exit_conf_state(dev); +} + +void wilco_ec_early_init(void) +{ + if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)) + wilco_ec_serial_init(); +} diff --git a/src/ec/google/wilco/bootblock.h b/src/ec/google/wilco/bootblock.h new file mode 100644 index 0000000..6fc3fc7 --- /dev/null +++ b/src/ec/google/wilco/bootblock.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef EC_GOOGLE_WILCO_BOOTBLOCK_H +#define EC_GOOGLE_WILCO_BOOTBLOCK_H + +/* Perform early initialization of the EC */ +void wilco_ec_early_init(void); + +#endif /* EC_GOOGLE_WILCO_BOOTBLOCK_H */ -- To view, visit https://review.coreboot.org/29121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9d6935a9fdf0d7290a94bf2ee565ef2a7c00ecc7 Gerrit-Change-Number: 29121 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: ec/google/wilco: Save and restore PS/2 data for S3
by Duncan Laurie (Code Review) 16 Oct '18

16 Oct '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/29120 Change subject: ec/google/wilco: Save and restore PS/2 data for S3 ...................................................................... ec/google/wilco: Save and restore PS/2 data for S3 Send a command to the EC on the way into S3 suspend state telling it to save the PS/2 data, and on resume send it a command for restoring the PS/2 data that was previously saved. Change-Id: Ic4b5d6d2656dbb1c476b9211b0d60c71b0cd7b32 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/ec/google/wilco/chip.c M src/ec/google/wilco/commands.h M src/ec/google/wilco/smihandler.c 3 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/29120/1 diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index fe4ef6a..d8ec281 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -44,6 +44,13 @@ BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, wilco_ec_post_video_init, NULL); +static void wilco_ec_suspend_resume(void *unused) +{ + wilco_ec_send_noargs(KB_RESTORE); +} +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, + wilco_ec_suspend_resume, NULL); + static void wilco_ec_init(struct device *dev) { if (!dev->enabled) diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h index a74e1b2..eeb6d30 100644 --- a/src/ec/google/wilco/commands.h +++ b/src/ec/google/wilco/commands.h @@ -25,6 +25,10 @@ KB_POWER_STATUS = 0x05, /* Inform the EC aboout the reason host is turning off */ KB_POWER_OFF = 0x08, + /* Save PS/2 data before S3 suspend */ + KB_SAVE = 0x2f, + /* Restore PS/2 data after S3 resume */ + KB_RESTORE = 0x30, /* Retrieve information about the EC */ KB_EC_INFO = 0x38, /* Set ACPI mode on or off */ diff --git a/src/ec/google/wilco/smihandler.c b/src/ec/google/wilco/smihandler.c index 9fb1518..adad533 100644 --- a/src/ec/google/wilco/smihandler.c +++ b/src/ec/google/wilco/smihandler.c @@ -25,6 +25,7 @@ { switch (slp_type) { case ACPI_S3: + wilco_ec_send_noargs(KB_SAVE); wilco_ec_slp_en(); break; case ACPI_S5: -- To view, visit https://review.coreboot.org/29120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic4b5d6d2656dbb1c476b9211b0d60c71b0cd7b32 Gerrit-Change-Number: 29120 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: ec/google/wilco: Add SMM handlers
by Duncan Laurie (Code Review) 16 Oct '18

16 Oct '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/29119 Change subject: ec/google/wilco: Add SMM handlers ...................................................................... ec/google/wilco: Add SMM handlers Add EC handlers for specific SMM actions: - on entry to sleep state tell the EC to save state and to prepare for the host to enter sleep - on ACPI enable/disable send command to the EC - add a function to print SMI reasons when eSPI SMI is received These need to be called by the mainboard handlers which will be done when a board is added that uses this EC. Change-Id: Ibabdc1462e0a8df405f9520244b83684e2ccf2f5 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/ec/google/wilco/Makefile.inc A src/ec/google/wilco/smihandler.c A src/ec/google/wilco/smm.h 3 files changed, 83 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/29119/1 diff --git a/src/ec/google/wilco/Makefile.inc b/src/ec/google/wilco/Makefile.inc index c011ebf..33eefd5 100644 --- a/src/ec/google/wilco/Makefile.inc +++ b/src/ec/google/wilco/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_EC_GOOGLE_WILCO),y) ramstage-y += chip.c commands.c mailbox.c +smm-y += commands.c mailbox.c smihandler.c endif diff --git a/src/ec/google/wilco/smihandler.c b/src/ec/google/wilco/smihandler.c new file mode 100644 index 0000000..9fb1518 --- /dev/null +++ b/src/ec/google/wilco/smihandler.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <cpu/x86/smm.h> + +#include "commands.h" +#include "ec.h" +#include "smm.h" + +void wilco_ec_smi_sleep(int slp_type) +{ + switch (slp_type) { + case ACPI_S3: + wilco_ec_slp_en(); + break; + case ACPI_S5: + wilco_ec_power_off(EC_SWOFF_ACPI); + break; + } +} + +void wilco_ec_smi_apmc(int apmc) +{ + switch (apmc) { + case APM_CNT_ACPI_ENABLE: + wilco_ec_send(KB_ACPI, ACPI_ON); + break; + case APM_CNT_ACPI_DISABLE: + wilco_ec_send(KB_ACPI, ACPI_OFF); + break; + } +} + +void wilco_ec_smi_espi(void) +{ + struct ec_pm_event_state pm; + + if (!wilco_ec_power_smi(&pm)) { + printk(BIOS_INFO, + "EC SMI: %02x_%02x-%02x_%02x_%02x_%02x_%02x_%02x-%02x", + pm.event[0], pm.event[1], + pm.state[0], pm.state[1], pm.state[2], + pm.state[3], pm.state[4], pm.state[5], pm.hotkey); + } +} diff --git a/src/ec/google/wilco/smm.h b/src/ec/google/wilco/smm.h new file mode 100644 index 0000000..1798b79 --- /dev/null +++ b/src/ec/google/wilco/smm.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef EC_GOOGLE_WILCO_SMM_H +#define EC_GOOGLE_WILCO_SMM_H + +void wilco_ec_smi_sleep(int slp_type); +void wilco_ec_smi_apmc(int apmc); +void wilco_ec_smi_espi(void); + +#endif /* EC_GOOGLE_WILCO_SMM_H */ -- To view, visit https://review.coreboot.org/29119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibabdc1462e0a8df405f9520244b83684e2ccf2f5 Gerrit-Change-Number: 29119 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: ec/google/wilco: Report BIOS progress to the EC
by Duncan Laurie (Code Review) 16 Oct '18

16 Oct '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/29118 Change subject: ec/google/wilco: Report BIOS progress to the EC ...................................................................... ec/google/wilco: Report BIOS progress to the EC The EC expects to receive updates about the BIOS boot progress. This is used for the EC logging to track system boot completeness. If the EC is not informed about BIOS progress it will turn the system off 30 seconds after the boot starts. Change-Id: I693c3930117db2b69a119aee0380d6f303c4881c Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/ec/google/wilco/chip.c M src/ec/google/wilco/commands.h 2 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/29118/1 diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index 4e6f4af..fe4ef6a 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <bootstate.h> #include <device/pnp.h> #include <pc80/keyboard.h> #include <stdint.h> @@ -22,6 +23,27 @@ #include "ec.h" #include "chip.h" +static void wilco_ec_post_complete(void *unused) +{ + wilco_ec_send(KB_BIOS_PROGRESS, BIOS_PROGRESS_POST_COMPLETE); +} +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, + wilco_ec_post_complete, NULL); + +static void wilco_ec_post_memory_init(void *unused) +{ + wilco_ec_send(KB_BIOS_PROGRESS, BIOS_PROGRESS_MEMORY_INIT); +} +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, + wilco_ec_post_memory_init, NULL); + +static void wilco_ec_post_video_init(void *unused) +{ + wilco_ec_send(KB_BIOS_PROGRESS, BIOS_PROGRESS_VIDEO_INIT); +} +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, + wilco_ec_post_video_init, NULL); + static void wilco_ec_init(struct device *dev) { if (!dev->enabled) diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h index c277d83..a74e1b2 100644 --- a/src/ec/google/wilco/commands.h +++ b/src/ec/google/wilco/commands.h @@ -33,6 +33,8 @@ KB_POWER_BUTTON_TO_HOST = 0x3e, /* Inform the EC that the host is about to enter S3 */ KB_SLP_EN = 0x64, + /* Inform the EC about BIOS boot progress */ + KB_BIOS_PROGRESS = 0xc2, }; enum set_acpi_mode_cmd { @@ -40,6 +42,13 @@ ACPI_ON }; +enum bios_progress_code { + BIOS_PROGRESS_MEMORY_INIT = 0x01, + BIOS_PROGRESS_VIDEO_INIT = 0x02, + BIOS_PROGRESS_LOGO_DISPLAYED = 0x03, + BIOS_PROGRESS_POST_COMPLETE = 0x04, +}; + /* * EC Information */ -- To view, visit https://review.coreboot.org/29118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I693c3930117db2b69a119aee0380d6f303c4881c Gerrit-Change-Number: 29118 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: ec/google/wilco: Add devicetree chip infrastructure
by Duncan Laurie (Code Review) 16 Oct '18

16 Oct '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/29117 Change subject: ec/google/wilco: Add devicetree chip infrastructure ...................................................................... ec/google/wilco: Add devicetree chip infrastructure Add a chip_operations structure for Wilco EC and hook it into the device tree so it can be initialized at boot. Reserve the device resources specified in Kconfig, which will also create the device IO windows if they have not been created in bootblock. If the IO windows already exist (becauase they were specified in the mainboard devicetree.cb) then this will find the existing entry instead. During device init stage prepare the keyboard for use, which is required for it to be functional in firmware and OS with this EC. Also send a command to the EC telling it to pass the power button through to the host for processing. Change-Id: I0adb01cf394f939f4a28aeb47fe4d0bcda5957d9 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/ec/google/wilco/Makefile.inc A src/ec/google/wilco/chip.c A src/ec/google/wilco/chip.h 3 files changed, 107 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29117/1 diff --git a/src/ec/google/wilco/Makefile.inc b/src/ec/google/wilco/Makefile.inc index 68172e3..c011ebf 100644 --- a/src/ec/google/wilco/Makefile.inc +++ b/src/ec/google/wilco/Makefile.inc @@ -1,5 +1,5 @@ ifeq ($(CONFIG_EC_GOOGLE_WILCO),y) -ramstage-y += commands.c mailbox.c +ramstage-y += chip.c commands.c mailbox.c endif diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c new file mode 100644 index 0000000..4e6f4af --- /dev/null +++ b/src/ec/google/wilco/chip.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <stdint.h> +#include <stdlib.h> + +#include "commands.h" +#include "ec.h" +#include "chip.h" + +static void wilco_ec_init(struct device *dev) +{ + if (!dev->enabled) + return; + + /* Print EC firmware information */ + wilco_ec_print_info(); + + /* Initialize keyboard, ignore emulated PS/2 mouse */ + pc_keyboard_init(NO_AUX_DEVICE); + + /* Direct power button to the host for processing */ + wilco_ec_send(KB_POWER_BUTTON_TO_HOST, 1); +} + +static void wilco_ec_resource(struct device *dev, int index, + size_t base, size_t size) +{ + struct resource *res = new_resource(dev, index); + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res->base = base; + res->size = size; +} + +static void wilco_ec_read_resources(struct device *dev) +{ + /* ACPI command and data regions */ + wilco_ec_resource(dev, 0, CONFIG_EC_BASE_ACPI_DATA, 8); + + /* Host command and data regions */ + wilco_ec_resource(dev, 1, CONFIG_EC_BASE_HOST_DATA, 8); + + /* Packet region */ + wilco_ec_resource(dev, 2, CONFIG_EC_BASE_PACKET, 16); +} + +static struct device_operations ops = { + .init = wilco_ec_init, + .read_resources = wilco_ec_read_resources, + .enable_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, +}; + +static struct pnp_info info[] = { + { NULL, 0, 0, 0, } +}; + +static void wilco_ec_enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(info), info); +} + +struct chip_operations ec_google_wilco_ops = { + CHIP_NAME("Google Wilco EC") + .enable_dev = wilco_ec_enable_dev, +}; diff --git a/src/ec/google/wilco/chip.h b/src/ec/google/wilco/chip.h new file mode 100644 index 0000000..9b02ee3 --- /dev/null +++ b/src/ec/google/wilco/chip.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef EC_GOOGLE_WILCO_CHIP_H +#define EC_GOOGLE_WILCO_CHIP_H + +#include <device/device.h> + +extern struct chip_operations ec_google_wilco_ops; + +struct ec_google_wilco_config { +}; + +#endif /* EC_GOOGLE_WILCO_CHIP_H */ -- To view, visit https://review.coreboot.org/29117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0adb01cf394f939f4a28aeb47fe4d0bcda5957d9 Gerrit-Change-Number: 29117 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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Change in coreboot[master]: ec/google/wilco: Add mailbox commands
by Duncan Laurie (Code Review) 16 Oct '18

16 Oct '18

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/29115 Change subject: ec/google/wilco: Add mailbox commands ...................................................................... ec/google/wilco: Add mailbox commands Add basic supported mailbox commands for this embedded contrlller, and define some command functions to retrieve and print information about the EC. Change-Id: Ibcef7d58e1852fdb2e52b97acd4b51a26dd8cd77 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/ec/google/wilco/Makefile.inc A src/ec/google/wilco/commands.c A src/ec/google/wilco/commands.h 3 files changed, 107 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/29115/1 diff --git a/src/ec/google/wilco/Makefile.inc b/src/ec/google/wilco/Makefile.inc index 6130f6f..68172e3 100644 --- a/src/ec/google/wilco/Makefile.inc +++ b/src/ec/google/wilco/Makefile.inc @@ -1,5 +1,5 @@ ifeq ($(CONFIG_EC_GOOGLE_WILCO),y) -ramstage-y += mailbox.c +ramstage-y += commands.c mailbox.c endif diff --git a/src/ec/google/wilco/commands.c b/src/ec/google/wilco/commands.c new file mode 100644 index 0000000..4cec58b --- /dev/null +++ b/src/ec/google/wilco/commands.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <stdint.h> +#include <string.h> + +#include "ec.h" +#include "commands.h" + +int wilco_ec_get_info(enum get_ec_info_cmd type, char *info) +{ + struct ec_response_get_ec_info rsp; + + if (!info) + return -1; + if (wilco_ec_sendrecv(KB_EC_INFO, type, &rsp, sizeof(rsp)) < 0) + return -1; + + /* Copy returned string */ + strncpy(info, rsp.data, sizeof(rsp)); + return 0; +} + +void wilco_ec_print_info(void) +{ + char info[EC_INFO_MAX_SIZE]; + + if (!wilco_ec_get_info(GET_EC_LABEL, info)) + printk(BIOS_INFO, "EC Label : %s\n", info); + + if (!wilco_ec_get_info(GET_EC_SVN_REV, info)) + printk(BIOS_INFO, "EC Revision : %s\n", info); + + if (!wilco_ec_get_info(GET_EC_MODEL_NO, info)) + printk(BIOS_INFO, "EC Model Num : %s\n", info); + + if (!wilco_ec_get_info(GET_EC_BUILD_DATE, info)) + printk(BIOS_INFO, "EC Build Date : %s\n", info); +} diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h new file mode 100644 index 0000000..76949d0 --- /dev/null +++ b/src/ec/google/wilco/commands.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef EC_GOOGLE_WILCO_COMMANDS_H +#define EC_GOOGLE_WILCO_COMMANDS_H + +#include <stdint.h> + +enum { + /* Retrieve information about the EC */ + KB_EC_INFO = 0x38, + /* Set ACPI mode on or off */ + KB_ACPI = 0x3a, + /* Manage the EC power button passthru to the host */ + KB_POWER_BUTTON_TO_HOST = 0x3e, +}; + +enum set_acpi_mode_cmd { + ACPI_OFF = 0, + ACPI_ON +}; + +/* + * EC Information + */ + +enum get_ec_info_cmd { + GET_EC_LABEL = 0, + GET_EC_SVN_REV, + GET_EC_MODEL_NO, + GET_EC_BUILD_DATE +}; + +#define EC_INFO_MAX_SIZE 9 +struct ec_response_get_ec_info { + char data[EC_INFO_MAX_SIZE]; /* ascii null-terminated string */ +}; + +int wilco_ec_get_info(enum get_ec_info_cmd cmd, char *info); +void wilco_ec_print_info(void); + +#endif /* EC_GOOGLE_WILCO_COMMANDS_H */ -- To view, visit https://review.coreboot.org/29115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibcef7d58e1852fdb2e52b97acd4b51a26dd8cd77 Gerrit-Change-Number: 29115 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>

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coreboot-gerrit October 2018