coreboot-gerrit October 2018

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Change in coreboot[master]: amd {cpu, drivers}: Replace MSR addresses with macros
by Martin Roth (Code Review) 16 Oct '18

16 Oct '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/29097 ) Change subject: amd {cpu,drivers}: Replace MSR addresses with macros ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I30d906e586d8f61701f961c247215d138cafe74d Gerrit-Change-Number: 29097 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 15 Oct 2018 15:38:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: riscv: add support smp_pause / smp_resume
by build bot (Jenkins) (Code Review) 16 Oct '18

16 Oct '18

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Change in coreboot[master]: mb: Fix non-local header treated as local
by Martin Roth (Code Review) 16 Oct '18

16 Oct '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/29098 ) Change subject: mb: Fix non-local header treated as local ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/29098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib39305effdb00e032ca07e6d0e0d84cdf3dcf916 Gerrit-Change-Number: 29098 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 15 Oct 2018 15:33:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: riscv: add support smp_pause / smp_resume
by build bot (Jenkins) (Code Review) 16 Oct '18

16 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29023 ) Change subject: riscv: add support smp_pause / smp_resume ...................................................................... Patch Set 14: (4 comments) https://review.coreboot.org/#/c/29023/14/src/arch/riscv/smp.c File src/arch/riscv/smp.c: https://review.coreboot.org/#/c/29023/14/src/arch/riscv/smp.c@47 PS14, Line 47: /* Initialize the counter and mark the work hart into smp_pause */ line over 80 characters https://review.coreboot.org/#/c/29023/14/src/arch/riscv/smp.c@47 PS14, Line 47: /* Initialize the counter and mark the work hart into smp_pause */ code indent should use tabs where possible https://review.coreboot.org/#/c/29023/14/src/arch/riscv/smp.c@47 PS14, Line 47: /* Initialize the counter and mark the work hart into smp_pause */ please, no space before tabs https://review.coreboot.org/#/c/29023/14/src/arch/riscv/smp.c@47 PS14, Line 47: /* Initialize the counter and mark the work hart into smp_pause */ please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/29023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb Gerrit-Change-Number: 29023 Gerrit-PatchSet: 14 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 15 Oct 2018 15:28:39 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: add support smp_pause / smp_resume
by build bot (Jenkins) (Code Review) 15 Oct '18

15 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29023 ) Change subject: riscv: add support smp_pause / smp_resume ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/#/c/29023/9/src/arch/riscv/smp.c File src/arch/riscv/smp.c: https://review.coreboot.org/#/c/29023/9/src/arch/riscv/smp.c@41 PS9, Line 41: die("smp_resume must pass a non-null function pointer\n"); Prefer using '"%s...", __func__' to using 'smp_resume', this function's name, in a string -- To view, visit https://review.coreboot.org/29023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb Gerrit-Change-Number: 29023 Gerrit-PatchSet: 9 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 15 Oct 2018 14:27:08 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/asus/p5q_pro: Add mainboard
by Felix Held (Code Review) 15 Oct '18

15 Oct '18

Felix Held has submitted this change and it was merged. ( https://review.coreboot.org/29102 ) Change subject: mb/asus/p5q_pro: Add mainboard ...................................................................... mb/asus/p5q_pro: Add mainboard This mainboard is quite similar to the p5qc. The main differences being a second PEG slot, the IDE slot and being DDR2 only. The following was tested: - both PEG slots populated (coreboot sets legacy VGA decoding on the GPU in the black slot) - USB - Ethernet NIC - PS2 Keyboard - COM1 - S3 resume Change-Id: I49a4bca4256e2a905aff3252eca76387c81152c1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/29102 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/Kconfig.name A src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb R src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb 4 files changed, 143 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/asus/p5qc/Kconfig b/src/mainboard/asus/p5qc/Kconfig index cf71b64..2bcee16 100644 --- a/src/mainboard/asus/p5qc/Kconfig +++ b/src/mainboard/asus/p5qc/Kconfig @@ -14,7 +14,7 @@ # GNU General Public License for more details. # -if BOARD_ASUS_P5QC +if BOARD_ASUS_P5QC || BOARD_ASUS_P5Q_PRO config BOARD_SPECIFIC_OPTIONS def_bool y @@ -34,9 +34,20 @@ string default "asus/p5qc" +config VARIANT_DIR + string + default "p5qc" if BOARD_ASUS_P5QC + default "p5q_pro" if BOARD_ASUS_P5Q_PRO + config MAINBOARD_PART_NUMBER string - default "P5QC" + default "P5QC" if BOARD_ASUS_P5QC + default "P5Q-PRO" if BOARD_ASUS_P5Q_PRO + +config DEVICETREE + string + default "variants/p5qc/devicetree.cb" if BOARD_ASUS_P5QC + default "variants/p5q_pro/devicetree.cb" if BOARD_ASUS_P5Q_PRO config MAX_CPUS int diff --git a/src/mainboard/asus/p5qc/Kconfig.name b/src/mainboard/asus/p5qc/Kconfig.name index d764867..a4c6e48 100644 --- a/src/mainboard/asus/p5qc/Kconfig.name +++ b/src/mainboard/asus/p5qc/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_ASUS_P5QC bool "P5QC" + +config BOARD_ASUS_P5Q_PRO + bool "P5Q PRO" diff --git a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb new file mode 100644 index 0000000..f7088fc --- /dev/null +++ b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb @@ -0,0 +1,127 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# Copyright (C) 2018 Arthur Heymans <arthur(a)aheymans.xyz> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/x4x # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xACAC off end + end + end + device domain 0 on # PCI domain + device pci 0.0 on end # Host Bridge + device pci 1.0 on end # PEG + device pci 2.0 off end # Integrated graphics controller + device pci 2.1 off end # Integrated graphics controller 2 + device pci 3.0 off end # ME + device pci 3.1 off end # ME + device pci 3.2 off end # ME + device pci 3.3 off end # ME + device pci 6.0 on end # PEG 2 + chip southbridge/intel/i82801jx # Southbridge + register "gpe0_en" = "0x40" + + # Set AHCI mode. + register "sata_port_map" = "0x3f" + register "sata_clock_request" = "0" + register "sata_traffic_monitor" = "0" + + # Enable PCIe ports 0,2,3 as slots. + register "pcie_slot_implemented" = "0x31" + + device pci 19.0 off end # GBE + device pci 1a.0 on end # USB + device pci 1a.1 on end # USB + device pci 1a.2 on end # USB + device pci 1a.7 on end # USB + device pci 1b.0 on end # Audio + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 off end # PCIe 2 + device pci 1c.2 off end # PCIe 3 + device pci 1c.3 off end # PCIe 4 + device pci 1c.4 on end # PCIe 5 MARVEL IDE + device pci 1c.5 on end # PCIe 6 + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.7 on end # USB + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/winbond/w83667hg-a # Super I/O + device pnp 2e.0 on # FDC + # Global registers + irq 0x2a = 0x30 + irq 0x2c = 0x22 + irq 0x2d = 0x00 + io 0x60 = 0x3f0 + irq 0x70 = 0x06 + end + device pnp 2e.1 off end # LPT1 + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2 + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.106 off end # SPI1 + device pnp 2e.107 off end # GIPO6 + device pnp 2e.207 off end # GIPO7 + device pnp 2e.307 on # GIPO8 + irq 0xe4 = 0xfb + irq 0xe5 = 0x82 + end + device pnp 2e.407 off end # GIPO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO 1 + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 on end # GPIO3 + device pnp 2e.209 on # GPIO4 + irq 0xf0 = 0xff + irq 0xfe = 0x07 + end + device pnp 2e.309 on end # GPIO5 + device pnp 2e.a on # ACPI + irq 0xe4 = 0x10 # 3VSBSW# enable + irq 0xe5 = 0x02 + irq 0xf2 = 0xfc + end + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 0x0 + # IRQ purposefully not assigned to prevent lockups + end + device pnp 2e.c on end # PECI + device pnp 2e.d on end # VID_BUSSEL + device pnp 2e.f on end # GPIO_PP_OD + end + end + device pci 1f.1 off end # PATA/IDE + device pci 1f.2 on end # SATA + device pci 1f.3 on end # SMbus + device pci 1f.4 off end + device pci 1f.5 on end # IDE + device pci 1f.6 off end + end + end +end diff --git a/src/mainboard/asus/p5qc/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb similarity index 100% rename from src/mainboard/asus/p5qc/devicetree.cb rename to src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb -- To view, visit https://review.coreboot.org/29102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I49a4bca4256e2a905aff3252eca76387c81152c1 Gerrit-Change-Number: 29102 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: add support smp_pause / smp_resume
by Xiang Wang (Code Review) 15 Oct '18

15 Oct '18

Xiang Wang has posted comments on this change. ( https://review.coreboot.org/29023 ) Change subject: riscv: add support smp_pause / smp_resume ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/#/c/29023/7/src/arch/riscv/smp.c File src/arch/riscv/smp.c: https://review.coreboot.org/#/c/29023/7/src/arch/riscv/smp.c@24 PS7, Line 24: if (read_csr(mhartid) != working_hartid) { > Or as an alternative: […] Synchronous operations require atomic operations and static variables. Static variables are not easy to handle in bootblocks. Can you give me some suggestions? -- To view, visit https://review.coreboot.org/29023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb Gerrit-Change-Number: 29023 Gerrit-PatchSet: 8 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 15 Oct 2018 13:59:25 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/skylake: Prevent disabling of TCO
by Matt DeVillier (Code Review) 15 Oct '18

15 Oct '18

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/29108 ) Change subject: soc/intel/skylake: Prevent disabling of TCO ...................................................................... Patch Set 1: successfully tested on fizz with PmTimerDisable=0 -- To view, visit https://review.coreboot.org/29108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia146761036c9dbaef3c02c9a7122ae3dcdef7bdd Gerrit-Change-Number: 29108 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 15 Oct 2018 13:51:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/skylake: Prevent disabling of TCO
by Matt DeVillier (Code Review) 15 Oct '18

15 Oct '18

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/29108 ) Change subject: soc/intel/skylake: Prevent disabling of TCO ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia146761036c9dbaef3c02c9a7122ae3dcdef7bdd Gerrit-Change-Number: 29108 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 15 Oct 2018 13:51:10 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/x4x: Fix P45 CAPID max frequency
by Felix Held (Code Review) 15 Oct '18

15 Oct '18

Felix Held has submitted this change and it was merged. ( https://review.coreboot.org/29101 ) Change subject: nb/intel/x4x: Fix P45 CAPID max frequency ...................................................................... nb/intel/x4x: Fix P45 CAPID max frequency It looks like on the ASUS P5QC has 0 in this CAPID field while still supporting TCK_666MHZ. Change-Id: Id1a94d91434dbe782fcc56dad56fcaee4e78463b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/29101 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/northbridge/intel/x4x/raminit.c 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 4d34968..80bde6c 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -296,6 +296,7 @@ min_tCLK = MAX(min_tCLK, TCK_533MHZ); break; case 3: /* Only on P45 */ + case 0: min_tCLK = MAX(min_tCLK, TCK_666MHZ); break; } -- To view, visit https://review.coreboot.org/29101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Id1a94d91434dbe782fcc56dad56fcaee4e78463b Gerrit-Change-Number: 29101 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit October 2018