coreboot-gerrit October 2018

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Change in coreboot[master]: lib/ramtest: Adjust address for RAM test
by Werner Zeh (Code Review) 15 Oct '18

15 Oct '18

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/29106 Change subject: lib/ramtest: Adjust address for RAM test ...................................................................... lib/ramtest: Adjust address for RAM test In patch 83bd46e (selfboot: remove bounce buffers) the address for RAMBASE has been changed from 1 MiB to 14 MiB. As the address for the quick RAM test was unfortunately hard coded it was overseen in the mentioned patch. Use now the value of CONFIG_RAMBASE for the quick RAM test so that the address that will be used to load the ramstage is tested. Change-Id: Ibc57e684a677ac64225ea54cb43e6fbb68930354 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/lib/ramtest.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/29106/1 diff --git a/src/lib/ramtest.c b/src/lib/ramtest.c index 461a028..1344c95 100644 --- a/src/lib/ramtest.c +++ b/src/lib/ramtest.c @@ -214,5 +214,5 @@ void quick_ram_check(void) { - __quick_ram_check(0x100000); + __quick_ram_check(CONFIG_RAMBASE); } -- To view, visit https://review.coreboot.org/29106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibc57e684a677ac64225ea54cb43e6fbb68930354 Gerrit-Change-Number: 29106 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>

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Change in coreboot[master]: cpu/x86/smm: Fix non-local header treated as local
by Elyes HAOUAS (Code Review) 15 Oct '18

15 Oct '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29105 Change subject: cpu/x86/smm: Fix non-local header treated as local ...................................................................... cpu/x86/smm: Fix non-local header treated as local Change-Id: I15dfe0332fd87db61d692a94bf1fd5d00dfb83d4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/x86/smm/smmrelocate.S 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/29105/1 diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 56e73cd..16bccbc 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -22,13 +22,13 @@ // It's needed right now because we get our DEFAULT_PMBASE from // here. #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) -#include "../../../southbridge/intel/i82801gx/i82801gx.h" +#include <southbridge/intel/i82801gx/i82801gx.h> #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801DX) -#include "../../../southbridge/intel/i82801dx/i82801dx.h" +#include <southbridge/intel/i82801dx/i82801dx.h> #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801IX) -#include "../../../southbridge/intel/i82801ix/i82801ix.h" +#include <southbridge/intel/i82801ix/i82801ix.h> #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801JX) -#include "../../../southbridge/intel/i82801jx/i82801jx.h" +#include <southbridge/intel/i82801jx/i82801jx.h> #else #error "Southbridge needs SMM handler support." -- To view, visit https://review.coreboot.org/29105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I15dfe0332fd87db61d692a94bf1fd5d00dfb83d4 Gerrit-Change-Number: 29105 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mb/asus/p5q_pro: Add mainboard
by Felix Held (Code Review) 15 Oct '18

15 Oct '18

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Change in coreboot[master]: mb/asus/p5q_pro: Add mainboard
by Arthur Heymans (Code Review) 15 Oct '18

15 Oct '18

Hello Felix Held, Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29102 to look at the new patch set (#3). Change subject: mb/asus/p5q_pro: Add mainboard ...................................................................... mb/asus/p5q_pro: Add mainboard This mainboard is quite similar to the p5qc. The main differences being a second PEG slot, the IDE slot and being DDR2 only. The following was tested: - both PEG slots populated (coreboot sets legacy VGA decoding on the GPU in the black slot) - USB - Ethernet NIC - PS2 Keyboard - COM1 - S3 resume Change-Id: I49a4bca4256e2a905aff3252eca76387c81152c1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/Kconfig.name A src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb R src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb 4 files changed, 143 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/29102/3 -- To view, visit https://review.coreboot.org/29102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I49a4bca4256e2a905aff3252eca76387c81152c1 Gerrit-Change-Number: 29102 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/asus/p5q_pro: Add mainboard
by Felix Held (Code Review) 15 Oct '18

15 Oct '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/29102 ) Change subject: mb/asus/p5q_pro: Add mainboard ...................................................................... Patch Set 2: Code-Review+1 (2 comments) https://review.coreboot.org/#/c/29102/2/src/mainboard/asus/p5qc/variants/p5… File src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb: https://review.coreboot.org/#/c/29102/2/src/mainboard/asus/p5qc/variants/p5… PS2, Line 65: ISA LPC https://review.coreboot.org/#/c/29102/2/src/mainboard/asus/p5qc/variants/p5… PS2, Line 111: # IRQ purposefully not assigned to prevent lockups maybe set it explicitly to 0? that's the default value -- To view, visit https://review.coreboot.org/29102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I49a4bca4256e2a905aff3252eca76387c81152c1 Gerrit-Change-Number: 29102 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 14 Oct 2018 14:04:26 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: libpayload: Add HID mouse support
by build bot (Jenkins) (Code Review) 15 Oct '18

15 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18598 ) Change subject: libpayload: Add HID mouse support ...................................................................... Patch Set 7: (2 comments) https://review.coreboot.org/#/c/18598/7/payloads/libpayload/drivers/usb/usb… File payloads/libpayload/drivers/usb/usbhid.c: https://review.coreboot.org/#/c/18598/7/payloads/libpayload/drivers/usb/usb… PS7, Line 431: while((buf = dev->controller->poll_intr_queue (HID_INST(dev)->queue))) { space prohibited between function name and open parenthesis '(' https://review.coreboot.org/#/c/18598/7/payloads/libpayload/drivers/usb/usb… PS7, Line 431: while((buf = dev->controller->poll_intr_queue (HID_INST(dev)->queue))) { space required before the open parenthesis '(' -- To view, visit https://review.coreboot.org/18598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibce251d77f7ccc85e17d42fc471b14d294c0c3e9 Gerrit-Change-Number: 18598 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 14 Oct 2018 14:01:33 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/x4x: Fix P45 CAPID max frequency
by Felix Held (Code Review) 15 Oct '18

15 Oct '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/29101 ) Change subject: nb/intel/x4x: Fix P45 CAPID max frequency ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id1a94d91434dbe782fcc56dad56fcaee4e78463b Gerrit-Change-Number: 29101 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 14 Oct 2018 13:57:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: sb/intel/i82801jx: Use macros for LPC_EN
by Felix Held (Code Review) 15 Oct '18

15 Oct '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/29100 ) Change subject: sb/intel/i82801jx: Use macros for LPC_EN ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4a9a9366c85206fa460519a26f48b3aada5bc7c3 Gerrit-Change-Number: 29100 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 14 Oct 2018 13:42:24 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/nb: Fix non-local header treated as local
by Elyes HAOUAS (Code Review) 14 Oct '18

14 Oct '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29103 Change subject: src/nb: Fix non-local header treated as local ...................................................................... src/nb: Fix non-local header treated as local Change-Id: I0668b73cd3a5bf5220af55c29785220b77eb5259 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/lx/northbridge.c M src/northbridge/amd/pi/00630F01/dimmSpd.c M src/northbridge/amd/pi/00660F01/dimmSpd.c M src/northbridge/amd/pi/00730F01/dimmSpd.c 4 files changed, 10 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/29103/1 diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index b9ead38..ffaaa19 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -27,9 +27,8 @@ #include <cpu/x86/msr.h> #include <cpu/x86/cache.h> #include <cpu/amd/vr.h> -#include <cpu/cpu.h> #include "northbridge.h" -#include "../../../southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> /* here is programming for the various MSRs.*/ diff --git a/src/northbridge/amd/pi/00630F01/dimmSpd.c b/src/northbridge/amd/pi/00630F01/dimmSpd.c index 1789e7d..03ce254 100644 --- a/src/northbridge/amd/pi/00630F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00630F01/dimmSpd.c @@ -17,11 +17,11 @@ #include <device/device.h> /* warning: Porting.h includes an open #pragma pack(1) */ -#include "Porting.h" -#include "AGESA.h" +#include <vendorcode/amd/include/Porting.h> +#include <vendorcode/amd/pi/00630F01/AGESA.h> #include "chip.h" -#include "northbridge/amd/pi/dimmSpd.h" +#include <northbridge/amd/pi/dimmSpd.h> #define DIMENSION(array)(sizeof(array)/ sizeof(array [0])) diff --git a/src/northbridge/amd/pi/00660F01/dimmSpd.c b/src/northbridge/amd/pi/00660F01/dimmSpd.c index 4869895..c3e0705 100644 --- a/src/northbridge/amd/pi/00660F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00660F01/dimmSpd.c @@ -18,10 +18,10 @@ #include <stdlib.h> /* warning: Porting.h includes an open #pragma pack(1) */ -#include "Porting.h" -#include "AGESA.h" +#include <vendorcode/amd/include/Porting.h> +#include <vendorcode/amd/pi/00660F01/AGESA.h> #include "chip.h" -#include "northbridge/amd/pi/dimmSpd.h" +#include <northbridge/amd/pi/dimmSpd.h> AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info) { diff --git a/src/northbridge/amd/pi/00730F01/dimmSpd.c b/src/northbridge/amd/pi/00730F01/dimmSpd.c index fdeefab..5024f8c 100644 --- a/src/northbridge/amd/pi/00730F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00730F01/dimmSpd.c @@ -17,11 +17,11 @@ #include <device/device.h> /* warning: Porting.h includes an open #pragma pack(1) */ -#include "Porting.h" -#include "AGESA.h" +#include <vendorcode/amd/include/Porting.h> +#include <vendorcode/amd/pi/00730F01/AGESA.h> #include "chip.h" -#include "northbridge/amd/pi/dimmSpd.h" +#include <northbridge/amd/pi/dimmSpd.h> #define DIMENSION(array)(sizeof(array)/ sizeof(array [0])) -- To view, visit https://review.coreboot.org/29103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0668b73cd3a5bf5220af55c29785220b77eb5259 Gerrit-Change-Number: 29103 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mb/asus/p5q_pro: Add mainboard
by Arthur Heymans (Code Review) 14 Oct '18

14 Oct '18

Arthur Heymans has uploaded a new patch set (#2). ( https://review.coreboot.org/29102 ) Change subject: mb/asus/p5q_pro: Add mainboard ...................................................................... mb/asus/p5q_pro: Add mainboard This mainboard is quite similar to the p5qc. The main differences being a second PEG slot, the IDE slot and being DDR2 only. The following was tested: - both PEG slots populated (coreboot sets legacy VGA decoding on the GPU in the black slot) - USB - Ethernet NIC - PS2 Keyboard - COM1 Change-Id: I49a4bca4256e2a905aff3252eca76387c81152c1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/Kconfig.name A src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb R src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb 4 files changed, 142 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/29102/2 -- To view, visit https://review.coreboot.org/29102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I49a4bca4256e2a905aff3252eca76387c81152c1 Gerrit-Change-Number: 29102 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit October 2018