Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/29113
Change subject: ec/google/wilco: Add Wilco EC mailbox interface
......................................................................
ec/google/wilco: Add Wilco EC mailbox interface
The Google "Wilco" Embedded Controller is a new embedded controller that
will be used in some future devices. The mailbox interface is simliar
to the existing Chromium EC protocol version 3, but not close enough
that it was convenient to re-use the full Chrome EC driver.
This commit adds the basic mailbox interface for ramstage which will be
used by future commits to send varous mailbox commands during the boot
process. The IO base addresses for the mailbox interface are defined in
Kconfig so they can be changed by the mainboard if needed.
Change-Id: I8520dadfa982c9d14357cf2aa644e255cef425c2
Signed-off-by: Duncan Laurie <dlaurie(a)google.com>
---
A src/ec/google/wilco/Kconfig
A src/ec/google/wilco/Makefile.inc
A src/ec/google/wilco/ec.h
A src/ec/google/wilco/mailbox.c
4 files changed, 352 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/29113/1
diff --git a/src/ec/google/wilco/Kconfig b/src/ec/google/wilco/Kconfig
new file mode 100644
index 0000000..e905d5e
--- /dev/null
+++ b/src/ec/google/wilco/Kconfig
@@ -0,0 +1,47 @@
+config EC_GOOGLE_WILCO
+ bool
+ default n
+ select EC_GOOGLE_COMMON_MEC
+ help
+ Google Wilco Embedded Controller interface.
+
+config EC_BASE_ACPI_DATA
+ hex
+ default 0x930
+ help
+ This option provides the 16-bit IO base address for the ACPI
+ data interface. This is the standard ACPI EC interface that
+ is used by the ACPI EC drivers in the OS.
+
+config EC_BASE_ACPI_COMMAND
+ hex
+ default 0x934
+ help
+ This option provides the 16-bit IO base address for the ACPI
+ EC command interface. This is the standard ACPI EC interface
+ that is used by the ACPI EC drivers in the OS.
+
+config EC_BASE_HOST_DATA
+ hex
+ default 0x940
+ help
+ This option provides the 16-bit IO base address for the host
+ data interface. This is the interface that is used to drive
+ the mailbox protocol.
+
+config EC_BASE_HOST_COMMAND
+ hex
+ default 0x944
+ help
+ This option provides the 16-bit IO base address for the host
+ command interface. This is the interface that is used to drive
+ the mailbox protocol.
+
+config EC_BASE_PACKET
+ hex
+ default 0x950
+ help
+ This option provides the 16-bit IO base address for the EC
+ mailbox interface data region. This data buffer is used along
+ with the host command and data registers to drive the EC
+ mailbox interface. This is also the MEC EMI base address.
diff --git a/src/ec/google/wilco/Makefile.inc b/src/ec/google/wilco/Makefile.inc
new file mode 100644
index 0000000..6130f6f
--- /dev/null
+++ b/src/ec/google/wilco/Makefile.inc
@@ -0,0 +1,5 @@
+ifeq ($(CONFIG_EC_GOOGLE_WILCO),y)
+
+ramstage-y += mailbox.c
+
+endif
diff --git a/src/ec/google/wilco/ec.h b/src/ec/google/wilco/ec.h
new file mode 100644
index 0000000..7b58473
--- /dev/null
+++ b/src/ec/google/wilco/ec.h
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef EC_GOOGLE_WILCO_EC_H
+#define EC_GOOGLE_WILCO_EC_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+/* Maximum request or response data size */
+#define WILCO_EC_DATA_MAX 32
+
+/* Different supported message types */
+enum wilco_ec_msg_type {
+ WILCO_EC_MSG_RAW, /* Raw message, do not skip any data */
+ WILCO_EC_MSG_DEFAULT, /* Skip 1 byte of response data */
+ WILCO_EC_MSG_NO_RESPONSE, /* EC does not respond to command */
+};
+
+/**
+ * wilco_ec_mailbox
+ *
+ * Send a command request to the EC mailbox and receive the response.
+ *
+ * @type: Mailbox message type, see enum above
+ * @command: Command to execute
+ * @request_data: Request data buffer
+ * @request_size: Number of bytes in request data buffer
+ * @response_data: Response data buffer
+ * @response_size: Number of bytes in response data buffer
+ *
+ * @return number of bytes received, negative error code on failure
+ */
+int wilco_ec_mailbox(enum wilco_ec_msg_type type, uint8_t command,
+ const void *request_data, size_t request_size,
+ void *response_data, size_t response_size);
+
+#endif /* EC_GOOGLE_WILCO_EC_H */
diff --git a/src/ec/google/wilco/mailbox.c b/src/ec/google/wilco/mailbox.c
new file mode 100644
index 0000000..c3f393a
--- /dev/null
+++ b/src/ec/google/wilco/mailbox.c
@@ -0,0 +1,250 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <delay.h>
+#include <ec/google/common/mec.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include <timer.h>
+#include <types.h>
+
+#include "ec.h"
+
+/* Mailbox ID */
+#define EC_MAILBOX_ID 0x00f0
+
+/* Version of mailbox interface */
+#define EC_MAILBOX_VERSION 0
+
+/* Command to start mailbox transaction */
+#define EC_MAILBOX_START_COMMAND 0xda
+
+/* Version of EC protocol */
+#define EC_MAILBOX_PROTO_VERSION 3
+
+/* Max number of bytes in protocol data payload */
+#define EC_MAILBOX_DATA_SIZE WILCO_EC_DATA_MAX
+
+/* Number of header bytes to be counted as data bytes */
+#define EC_MAILBOX_DATA_EXTRA 2
+
+/* Maximum timeout */
+#define EC_MAILBOX_TIMEOUT_US USECS_PER_SEC
+
+/* EC response flags */
+#define EC_CMDR_DATA BIT(0) /* Data ready for host to read */
+#define EC_CMDR_PENDING BIT(1) /* Write pending to EC */
+#define EC_CMDR_BUSY BIT(2) /* EC is busy processing a command */
+#define EC_CMDR_CMD BIT(3) /* Last host write was a command */
+
+/* Request to EC */
+struct wilco_ec_request {
+ uint8_t struct_version; /* version (=3) */
+ uint8_t checksum; /* sum of all bytes must be 0 */
+ uint16_t mailbox_id; /* mailbox identifier */
+ uint8_t mailbox_version; /* mailbox version (=0) */
+ uint8_t reserved1; /* unused (=0) */
+ uint16_t data_size; /* length (data + 2 bytes of header) */
+ uint8_t command; /* mailbox command */
+ uint8_t reserved2; /* unused (=0) */
+} __packed;
+
+/* Response from EC */
+struct wilco_ec_response {
+ uint8_t struct_version; /* version (=3) */
+ uint8_t checksum; /* sum of all bytes must be 0 */
+ uint16_t result; /* result code */
+ uint16_t data_size; /* length of data after header */
+ uint8_t reserved[3]; /* unused (=0) */
+ uint8_t data[EC_MAILBOX_DATA_SIZE];
+} __packed;
+
+struct wilco_ec_message {
+ uint8_t command; /* mailbox command code */
+ uint8_t result; /* request result */
+ size_t request_size; /* bytes to send to the EC */
+ size_t response_size; /* bytes expected from the EC */
+ enum wilco_ec_msg_type type; /* message type */
+ uint8_t data[EC_MAILBOX_DATA_SIZE];
+};
+
+static bool wilco_ec_response_timed_out(void)
+{
+ uint8_t mask = EC_CMDR_PENDING | EC_CMDR_BUSY;
+ uint32_t time_count = 0;
+
+ do {
+ if (!(inb(CONFIG_EC_BASE_HOST_COMMAND) & mask))
+ return false;
+ mdelay(1);
+ } while (time_count++ < EC_MAILBOX_TIMEOUT_US);
+
+ printk(BIOS_ERR, "%s: Command timeout\n", __func__);
+ return true;
+}
+
+static uint8_t wilco_ec_checksum(void *data, size_t size)
+{
+ uint8_t *data_bytes = (uint8_t *)data;
+ uint8_t checksum = 0;
+ size_t i;
+
+ for (i = 0; i < size; i++)
+ checksum += data_bytes[i];
+
+ return checksum;
+}
+
+static void wilco_ec_prepare(struct wilco_ec_message *msg,
+ struct wilco_ec_request *rq)
+{
+ memset(rq, 0, sizeof(*rq));
+
+ /* Fill in request packet */
+ rq->struct_version = EC_MAILBOX_PROTO_VERSION;
+ rq->mailbox_id = EC_MAILBOX_ID;
+ rq->mailbox_version = EC_MAILBOX_VERSION;
+ rq->data_size = msg->request_size + EC_MAILBOX_DATA_EXTRA;
+ rq->command = msg->command;
+
+ /* Checksum header and data */
+ rq->checksum = wilco_ec_checksum(rq, sizeof(*rq));
+ rq->checksum += wilco_ec_checksum(msg->data, msg->request_size);
+ rq->checksum = -rq->checksum;
+}
+
+static int wilco_ec_transfer(struct wilco_ec_message *msg)
+{
+ struct wilco_ec_request rq;
+ struct wilco_ec_response rs;
+ uint8_t checksum;
+ size_t skip_size;
+
+ /* Prepare request packet */
+ wilco_ec_prepare(msg, &rq);
+
+ /* Write request header */
+ mec_io_bytes(MEC_IO_WRITE, CONFIG_EC_BASE_PACKET, 0, &rq, sizeof(rq));
+
+ /* Write request data */
+ mec_io_bytes(MEC_IO_WRITE, CONFIG_EC_BASE_PACKET, sizeof(rq),
+ msg->data, msg->request_size);
+
+ /* Start the command */
+ outb(EC_MAILBOX_START_COMMAND, CONFIG_EC_BASE_HOST_COMMAND);
+
+ /* Wait for it to complete */
+ if (wilco_ec_response_timed_out()) {
+ printk(BIOS_ERR, "%s: response timed out\n", __func__);
+ return -1;
+ }
+
+ /* Some commands will put the EC into a state where it cannot respond */
+ if (msg->type == WILCO_EC_MSG_NO_RESPONSE) {
+ printk(BIOS_DEBUG, "%s: EC does not respond to this command\n",
+ __func__);
+ return 0;
+ }
+
+ /* Check result */
+ msg->result = inb(CONFIG_EC_BASE_HOST_DATA);
+ if (msg->result != 0) {
+ printk(BIOS_ERR, "%s: bad response: 0x%02x\n",
+ __func__, msg->result);
+ return -1;
+ }
+
+ /* Read back response */
+ checksum = mec_io_bytes(MEC_IO_READ, CONFIG_EC_BASE_PACKET, 0,
+ &rs, sizeof(rs));
+ if (checksum) {
+ printk(BIOS_ERR, "%s: bad checksum %02x\n", __func__, checksum);
+ return -1;
+ }
+ msg->result = rs.result;
+
+ /* EC always returns EC_MAILBOX_DATA_SIZE bytes */
+ if (rs.data_size > EC_MAILBOX_DATA_SIZE) {
+ printk(BIOS_ERR, "%s: packet too long (%d bytes, expected %d)",
+ __func__, rs.data_size, EC_MAILBOX_DATA_SIZE);
+ return -1;
+ }
+
+ if (msg->response_size > rs.data_size) {
+ printk(BIOS_ERR, "%s: data too short (%d bytes, expected %zu)",
+ __func__, rs.data_size, msg->response_size);
+ return -1;
+ }
+
+ /* Skip response data bytes as requested */
+ skip_size = (msg->type == WILCO_EC_MSG_DEFAULT) ? 1 : 0;
+ memcpy(msg->data, rs.data + skip_size, msg->response_size);
+
+ /* Return actual amount of data received */
+ return msg->response_size;
+}
+
+int wilco_ec_mailbox(enum wilco_ec_msg_type type, uint8_t command,
+ const void *request_data, size_t request_size,
+ void *response_data, size_t response_size)
+{
+ struct wilco_ec_message msg;
+ int ret;
+
+ if (request_size > EC_MAILBOX_DATA_SIZE) {
+ printk(BIOS_ERR, "%s: provided request data too large: %zu\n",
+ __func__, request_size);
+ return -1;
+ }
+ if (response_size > EC_MAILBOX_DATA_SIZE) {
+ printk(BIOS_ERR, "%s: expected response data too large: %zu\n",
+ __func__, response_size);
+ return -1;
+ }
+ if (request_size && !request_data) {
+ printk(BIOS_ERR, "%s: request data missing\n", __func__);
+ return -1;
+ }
+ if (response_size && !response_data) {
+ printk(BIOS_ERR, "%s: request data missing\n", __func__);
+ return -1;
+ }
+
+ /* Prepare message structure */
+ msg.command = command;
+ msg.request_size = request_size;
+ msg.response_size = response_size;
+ msg.type = type;
+
+ /* Copy request data if present */
+ if (request_size)
+ memcpy(msg.data, request_data, request_size);
+
+ /* Do the EC transfer */
+ ret = wilco_ec_transfer(&msg);
+
+ /* Copy response data if present */
+ if (ret > 0 && response_size)
+ memcpy(response_data, msg.data, response_size);
+
+ /* Return error if message result is non-zero */
+ if (ret >= 0 && msg.result)
+ ret = -1;
+
+ return ret;
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I8520dadfa982c9d14357cf2aa644e255cef425c2
Gerrit-Change-Number: 29113
Gerrit-PatchSet: 1
Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>
Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/29111
Change subject: ec/google/common: Add a common MEC interface
......................................................................
ec/google/common: Add a common MEC interface
In order to re-use the MEC interface code in the Chrome EC driver
move it to a common directory within the ec/google directory.
The Chrome EC driver itself is changed to use this interface in the
next commit, and future commits will introduce a new EC that also
uses this interface.
Change-Id: I13516b5e4c4c49f53bb998366284a26703142e2a
Signed-off-by: Duncan Laurie <dlaurie(a)google.com>
---
A src/ec/google/common/Kconfig
A src/ec/google/common/Makefile.inc
A src/ec/google/common/mec.c
A src/ec/google/common/mec.h
4 files changed, 174 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/29111/1
diff --git a/src/ec/google/common/Kconfig b/src/ec/google/common/Kconfig
new file mode 100644
index 0000000..2e138a5
--- /dev/null
+++ b/src/ec/google/common/Kconfig
@@ -0,0 +1,4 @@
+config EC_GOOGLE_COMMON_MEC
+ bool
+ help
+ Google common EC functions for Microchip EMI region.
diff --git a/src/ec/google/common/Makefile.inc b/src/ec/google/common/Makefile.inc
new file mode 100644
index 0000000..e8f511f
--- /dev/null
+++ b/src/ec/google/common/Makefile.inc
@@ -0,0 +1,5 @@
+bootblock-$(CONFIG_EC_GOOGLE_COMMON_MEC) += mec.c
+verstage-$(CONFIG_EC_GOOGLE_COMMON_MEC) += mec.c
+romstage-$(CONFIG_EC_GOOGLE_COMMON_MEC) += mec.c
+ramstage-$(CONFIG_EC_GOOGLE_COMMON_MEC) += mec.c
+smm-$(CONFIG_EC_GOOGLE_COMMON_MEC) += mec.c
\ No newline at end of file
diff --git a/src/ec/google/common/mec.c b/src/ec/google/common/mec.c
new file mode 100644
index 0000000..06a6bca
--- /dev/null
+++ b/src/ec/google/common/mec.c
@@ -0,0 +1,122 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stddef.h>
+#include <stdint.h>
+#include <arch/io.h>
+
+#include "mec.h"
+
+enum mec_access_mode {
+ /* 8-bit access */
+ ACCESS_TYPE_BYTE = 0x0,
+ /* 16-bit access */
+ ACCESS_TYPE_WORD = 0x1,
+ /* 32-bit access */
+ ACCESS_TYPE_LONG = 0x2,
+ /*
+ * 32-bit access, read or write of MEC_EMI_EC_DATA_B3 causes the
+ * EC data register to be incremented.
+ */
+ ACCESS_TYPE_LONG_AUTO_INCREMENT = 0x3,
+};
+
+/* EMI registers are relative to base */
+#define MEC_EMI_HOST_TO_EC(base) ((base) + 0)
+#define MEC_EMI_EC_TO_HOST(base) ((base) + 1)
+#define MEC_EMI_EC_ADDRESS_B0(base) ((base) + 2)
+#define MEC_EMI_EC_ADDRESS_B1(base) ((base) + 3)
+#define MEC_EMI_EC_DATA_B0(base) ((base) + 4)
+#define MEC_EMI_EC_DATA_B1(base) ((base) + 5)
+#define MEC_EMI_EC_DATA_B2(base) ((base) + 6)
+#define MEC_EMI_EC_DATA_B3(base) ((base) + 7)
+
+/*
+ * cros_ec_lpc_mec_emi_write_address
+ *
+ * Initialize EMI read / write at a given address.
+ *
+ * @base: Starting read / write address
+ * @offset: Offset applied to base address
+ * @access_mode: Type of access, typically 32-bit auto-increment
+ */
+static void mec_emi_write_address(uint16_t base, uint16_t offset,
+ enum mec_access_mode access_mode)
+{
+ outb((offset & 0xfc) | access_mode, MEC_EMI_EC_ADDRESS_B0(base));
+ outb((offset >> 8) & 0x7f, MEC_EMI_EC_ADDRESS_B1(base));
+}
+
+uint8_t mec_io_bytes(enum mec_io_type type, uint16_t base,
+ uint16_t offset, void *buffer, size_t size)
+{
+ enum mec_access_mode access_mode, new_access_mode;
+ uint8_t *buf = buffer;
+ uint8_t checksum = 0;
+ int io_addr;
+ int i = 0;
+
+ if (size == 0 || base == 0)
+ return 0;
+
+ /*
+ * Long access cannot be used on misaligned data since reading B0 loads
+ * the data register and writing B3 flushes it.
+ */
+ if ((offset & 0x3) || (size < 4))
+ access_mode = ACCESS_TYPE_BYTE;
+ else
+ access_mode = ACCESS_TYPE_LONG_AUTO_INCREMENT;
+
+ /* Initialize I/O at desired address */
+ mec_emi_write_address(base, offset, access_mode);
+
+ /* Skip bytes in case of misaligned offset */
+ io_addr = MEC_EMI_EC_DATA_B0(base) + (offset & 0x3);
+ while (i < size) {
+ while (io_addr <= MEC_EMI_EC_DATA_B3(base)) {
+ if (type == MEC_IO_WRITE)
+ outb(buf[i], io_addr++);
+ else
+ buf[i] = inb(io_addr++);
+
+ checksum += buf[i++];
+ offset++;
+
+ /* Extra bounds check in case of misaligned size */
+ if (i == size)
+ return checksum;
+ }
+
+ /*
+ * Use long auto-increment access except for misaligned write,
+ * since writing B3 triggers the flush.
+ */
+ if ((size - i) < 4 && type == MEC_IO_WRITE)
+ new_access_mode = ACCESS_TYPE_BYTE;
+ else
+ new_access_mode = ACCESS_TYPE_LONG_AUTO_INCREMENT;
+ if (new_access_mode != access_mode ||
+ access_mode != ACCESS_TYPE_LONG_AUTO_INCREMENT) {
+ access_mode = new_access_mode;
+ mec_emi_write_address(base, offset, access_mode);
+ }
+
+ /* Access [B0, B3] on each loop pass */
+ io_addr = MEC_EMI_EC_DATA_B0(base);
+ }
+
+ return checksum;
+}
diff --git a/src/ec/google/common/mec.h b/src/ec/google/common/mec.h
new file mode 100644
index 0000000..3452bad
--- /dev/null
+++ b/src/ec/google/common/mec.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef EC_GOOGLE_COMMON_MEC_H
+#define EC_GOOGLE_COMMON_MEC_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+/* Indicate read or write from MEC IO region */
+enum mec_io_type {
+ MEC_IO_READ,
+ MEC_IO_WRITE
+};
+
+/*
+ * mec_io_bytes - Read / write bytes to MEC EMI port
+ *
+ * @type: Indicate read or write operation
+ * @base: Base address for MEC EMI region
+ * @offset: Base read / write address
+ * @buffer: Destination / source buffer
+ * @size: Number of bytes to read / write
+ *
+ * @returns 8-bit checksum of all bytes read or written
+ */
+
+uint8_t mec_io_bytes(enum mec_io_type type, uint16_t base,
+ uint16_t offset, void *buffer, size_t size);
+
+#endif /* EC_GOOGLE_COMMON_MEC_H */
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I13516b5e4c4c49f53bb998366284a26703142e2a
Gerrit-Change-Number: 29111
Gerrit-PatchSet: 1
Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/29109
Change subject: src/mainboard: Add dell/gx520
......................................................................
src/mainboard: Add dell/gx520
What works:
- Compiling
What does not work:
- Getting the computer to display any signs of life with coreboot.
Change-Id: I0016dd35be67803e91ffefb0c87f54e35c93efcd
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
A src/mainboard/dell/Kconfig
A src/mainboard/dell/Kconfig.name
A src/mainboard/dell/gx520/Kconfig
A src/mainboard/dell/gx520/Kconfig.name
A src/mainboard/dell/gx520/Makefile.inc
A src/mainboard/dell/gx520/acpi/ec.asl
A src/mainboard/dell/gx520/acpi/ich7_pci_irqs.asl
A src/mainboard/dell/gx520/acpi/mainboard.asl
A src/mainboard/dell/gx520/acpi/platform.asl
A src/mainboard/dell/gx520/acpi/superio.asl
A src/mainboard/dell/gx520/acpi/thermal.asl
A src/mainboard/dell/gx520/acpi_tables.c
A src/mainboard/dell/gx520/board_info.txt
A src/mainboard/dell/gx520/cmos.default
A src/mainboard/dell/gx520/cmos.layout
A src/mainboard/dell/gx520/cstates.c
A src/mainboard/dell/gx520/data.vbt
A src/mainboard/dell/gx520/devicetree.cb
A src/mainboard/dell/gx520/dsdt.asl
A src/mainboard/dell/gx520/gpio.c
A src/mainboard/dell/gx520/hda_verb.c
A src/mainboard/dell/gx520/romstage.c
22 files changed, 985 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/29109/1
diff --git a/src/mainboard/dell/Kconfig b/src/mainboard/dell/Kconfig
new file mode 100644
index 0000000..c12e54a
--- /dev/null
+++ b/src/mainboard/dell/Kconfig
@@ -0,0 +1,16 @@
+if VENDOR_DELL
+
+choice
+ prompt "Mainboard model"
+
+source "src/mainboard/dell/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/dell/*/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "Dell"
+
+endif # VENDOR_DELL
diff --git a/src/mainboard/dell/Kconfig.name b/src/mainboard/dell/Kconfig.name
new file mode 100644
index 0000000..8a508ea
--- /dev/null
+++ b/src/mainboard/dell/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_DELL
+ bool "Dell"
diff --git a/src/mainboard/dell/gx520/Kconfig b/src/mainboard/dell/gx520/Kconfig
new file mode 100644
index 0000000..2d66191c
--- /dev/null
+++ b/src/mainboard/dell/gx520/Kconfig
@@ -0,0 +1,53 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 coresystems GmbH
+## Copyright (C) 2016 Arthur Heymans <arthur(a)ahemans.xyz
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+if BOARD_DELL_GX520
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_LGA775
+ select NORTHBRIDGE_INTEL_I945
+ select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
+ select SOUTHBRIDGE_INTEL_I82801GX
+ select SUPERIO_SMSC_SMSCSUPERIO
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select HAVE_MP_TABLE
+ select HAVE_ACPI_TABLES
+ select HAVE_ACPI_RESUME
+ select BOARD_ROMSIZE_KB_512
+ select CHANNEL_XOR_RANDOMIZATION
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+ #select INTEL_GMA_HAVE_VBT
+
+config MAINBOARD_DIR
+ string
+ default dell/gx520
+
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "GX520"
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAX_CPUS
+ int
+ default 4 ## 2 may be the chipsets limit
+
+endif # BOARD_DELL_GX520
diff --git a/src/mainboard/dell/gx520/Kconfig.name b/src/mainboard/dell/gx520/Kconfig.name
new file mode 100644
index 0000000..335aebe
--- /dev/null
+++ b/src/mainboard/dell/gx520/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_DELL_GX520
+ bool "GX520"
diff --git a/src/mainboard/dell/gx520/Makefile.inc b/src/mainboard/dell/gx520/Makefile.inc
new file mode 100644
index 0000000..f3d7e76
--- /dev/null
+++ b/src/mainboard/dell/gx520/Makefile.inc
@@ -0,0 +1,2 @@
+ramstage-y += cstates.c
+romstage-y += gpio.c
diff --git a/src/mainboard/dell/gx520/acpi/ec.asl b/src/mainboard/dell/gx520/acpi/ec.asl
new file mode 100644
index 0000000..5362bb2
--- /dev/null
+++ b/src/mainboard/dell/gx520/acpi/ec.asl
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device(EC0)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 1)
+
+ // _REG method requires that an operation region be defined.
+ OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff)
+ Field (ERAM, ByteAcc, Lock, Preserve)
+ {
+ }
+
+ Method (_CRS, 0, Serialized)
+ {
+ Name (ECMD, ResourceTemplate()
+ {
+ IO (Decode16, 0x62, 0x62, 0, 1)
+ IO (Decode16, 0x66, 0x66, 0, 1)
+ })
+
+ Return (ECMD)
+ }
+
+ Method (_REG, 2)
+ {
+ // This method is needed by Windows XP/2000
+ // for EC initialization before a driver
+ // is loaded
+ }
+
+ Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI
+
+ // TODO EC Query methods
+
+ // TODO Scope _SB devices for AC power, LID, Power button
+
+}
diff --git a/src/mainboard/dell/gx520/acpi/ich7_pci_irqs.asl b/src/mainboard/dell/gx520/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000..cc229a5
--- /dev/null
+++ b/src/mainboard/dell/gx520/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This is board specific information: IRQ routing for the
+ * 0:1e.0 PCI bridge of the ICH7
+ */
+
+
+If (PICM) {
+ Return (Package() {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x14 },
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x13 },
+ Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x12 },
+ Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x10 },
+ Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x14 },
+
+ })
+} Else {
+ Return (Package() {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKD, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LPCB.LNKA, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKD, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LPCB.LNKC, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LPCB.LNKA, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LPCB.LNKE, 0x00 },
+ })
+}
diff --git a/src/mainboard/dell/gx520/acpi/mainboard.asl b/src/mainboard/dell/gx520/acpi/mainboard.asl
new file mode 100644
index 0000000..0454c3f
--- /dev/null
+++ b/src/mainboard/dell/gx520/acpi/mainboard.asl
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (SLPB)
+{
+ Name(_HID, EisaId("PNP0C0E"))
+
+ // Wake
+ Name(_PRW, Package(){0x1d, 0x04})
+}
+
+Device (PWRB)
+{
+ Name(_HID, EisaId("PNP0C0C"))
+
+ // Wake
+ Name(_PRW, Package(){0x1d, 0x04})
+}
diff --git a/src/mainboard/dell/gx520/acpi/platform.asl b/src/mainboard/dell/gx520/acpi/platform.asl
new file mode 100644
index 0000000..21eb3df
--- /dev/null
+++ b/src/mainboard/dell/gx520/acpi/platform.asl
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+ // Call a trap so SMI can prepare for Sleep as well.
+ // TRAP(0x55)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ // CPU specific part
+
+ // Notify PCI Express slots in case a card
+ // was inserted while a sleep state was active.
+
+ // Are we going to S3?
+ If (LEqual(Arg0, 3)) {
+ // ..
+ }
+
+ // Are we going to S4?
+ If (LEqual(Arg0, 4)) {
+ // ..
+ }
+
+ // TODO: Windows XP SP2 P-State restore
+
+ Return(Package(){0,0})
+}
diff --git a/src/mainboard/dell/gx520/acpi/superio.asl b/src/mainboard/dell/gx520/acpi/superio.asl
new file mode 100644
index 0000000..2997587
--- /dev/null
+++ b/src/mainboard/dell/gx520/acpi/superio.asl
@@ -0,0 +1 @@
+/* dummy */
diff --git a/src/mainboard/dell/gx520/acpi/thermal.asl b/src/mainboard/dell/gx520/acpi/thermal.asl
new file mode 100644
index 0000000..2997587
--- /dev/null
+++ b/src/mainboard/dell/gx520/acpi/thermal.asl
@@ -0,0 +1 @@
+/* dummy */
diff --git a/src/mainboard/dell/gx520/acpi_tables.c b/src/mainboard/dell/gx520/acpi_tables.c
new file mode 100644
index 0000000..ba3995e
--- /dev/null
+++ b/src/mainboard/dell/gx520/acpi_tables.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <southbridge/intel/i82801gx/nvs.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+}
diff --git a/src/mainboard/dell/gx520/board_info.txt b/src/mainboard/dell/gx520/board_info.txt
new file mode 100644
index 0000000..70cbe41
--- /dev/null
+++ b/src/mainboard/dell/gx520/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=2669#ov
+Release year: 2007
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
diff --git a/src/mainboard/dell/gx520/cmos.default b/src/mainboard/dell/gx520/cmos.default
new file mode 100644
index 0000000..2cb37df
--- /dev/null
+++ b/src/mainboard/dell/gx520/cmos.default
@@ -0,0 +1,6 @@
+boot_option=Fallback
+debug_level=Debug
+hyper_threading=Enable
+nmi=Enable
+boot_devices=''
+gfx_uma_size=8M
diff --git a/src/mainboard/dell/gx520/cmos.layout b/src/mainboard/dell/gx520/cmos.layout
new file mode 100644
index 0000000..bdc264b
--- /dev/null
+++ b/src/mainboard/dell/gx520/cmos.layout
@@ -0,0 +1,114 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2008 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+#392 3 r 0 unused
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+
+# coreboot config options: northbridge
+411 3 e 11 gfx_uma_size
+
+# coreboot config options: bootloader
+416 512 s 0 boot_devices
+#928 80 r 0 unused
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# RAM initialization internal data
+1024 8 r 0 C0WL0REOST
+1032 8 r 0 C1WL0REOST
+1040 8 r 0 RCVENMT
+1048 4 r 0 C0DRT1
+1052 4 r 0 C1DRT1
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+11 0 1M
+11 1 4M
+11 2 8M
+11 3 16M
+11 4 32M
+11 5 48M
+11 6 64M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/dell/gx520/cstates.c b/src/mainboard/dell/gx520/cstates.c
new file mode 100644
index 0000000..f683756
--- /dev/null
+++ b/src/mainboard/dell/gx520/cstates.c
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <arch/x86/include/arch/acpigen.h>
+
+int get_cst_entries(acpi_cstate_t **entries)
+{
+ return 0;
+}
diff --git a/src/mainboard/dell/gx520/data.vbt b/src/mainboard/dell/gx520/data.vbt
new file mode 100644
index 0000000..d613a1c
--- /dev/null
+++ b/src/mainboard/dell/gx520/data.vbt
Binary files differ
diff --git a/src/mainboard/dell/gx520/devicetree.cb b/src/mainboard/dell/gx520/devicetree.cb
new file mode 100644
index 0000000..1688768
--- /dev/null
+++ b/src/mainboard/dell/gx520/devicetree.cb
@@ -0,0 +1,144 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+## Copyright (C) 2016 Arthur Heymans arthur(a)aheymans.xyz
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip northbridge/intel/i945
+
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_LGA775
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_1067x
+ device lapic 0xACAC off end
+ end
+ end
+
+ register "pci_mmio_size" = "768"
+
+ device domain 0 on
+ device pci 00.0 on # host bridge
+ subsystemid 0x1458 0x5000
+ end
+ device pci 01.0 on # i945 PCIe root port
+ subsystemid 0x1458 0x5000
+ end
+ device pci 02.0 on # vga controller
+ subsystemid 0x1458 0xd000
+ end
+ device pci 02.1 on # vga controller
+ subsystemid 0x1458 0xd000
+ end
+
+ chip southbridge/intel/i82801gx
+ #register "pirqa_routing" = "0x8c"
+ #register "pirqb_routing" = "0x8a"
+ #register "pirqc_routing" = "0x83"
+ #register "pirqd_routing" = "0x8b"
+ #register "pirqe_routing" = "0x80"
+ #register "pirqf_routing" = "0x80"
+ #register "pirqg_routing" = "0x80"
+ #register "pirqh_routing" = "0x85"
+
+ # GPI routing
+ # 0 No effect (default)
+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ # 2 SCI (if corresponding GPIO_EN bit is also set)
+ #register "gpi0_routing" = "1"
+ #register "gpi1_routing" = "1"
+ #register "gpi2_routing" = "1"
+ #register "gpi3_routing" = "1"
+ #register "gpi4_routing" = "1"
+ #register "gpi5_routing" = "1"
+ #register "gpi6_routing" = "1"
+ #register "gpi7_routing" = "1"
+ #register "gpi8_routing" = "1"
+ #register "gpi9_routing" = "1"
+ #register "gpi10_routing" = "1"
+ #register "gpi11_routing" = "1"
+ #register "gpi12_routing" = "1"
+ #register "gpi13_routing" = "2"
+ #register "gpi14_routing" = "1"
+ #register "gpi15_routing" = "1"
+
+ register "gpe0_en" = "100"
+
+ register "ide_legacy_combined" = "0x0"
+ register "ide_enable_primary" = "0x1"
+ register "ide_enable_secondary" = "0x0"
+ register "sata_ahci" = "0x0"
+ register "c3_latency" = "85"
+
+ register "p_cnt_throttling_supported" = "0"
+
+ device pci 1b.0 on # High Definition Audio
+ end
+ device pci 1c.0 on end # PCIe
+ device pci 1c.1 on end # PCIe
+ device pci 1c.2 off end # PCIe port 3
+ device pci 1c.3 off end # PCIe port 4
+ device pci 1c.4 off end # PCIe port 5
+ device pci 1c.5 off end # PCIe port 6
+ device pci 1d.0 on # USB UHCI
+ end
+ device pci 1d.1 on # USB UHCI
+ end
+ device pci 1d.2 on # USB UHCI
+ end
+ device pci 1d.3 on # USB UHCI
+ end
+ device pci 1d.7 on # USB2 EHCI
+ end
+ device pci 1e.0 on end # PCI bridge
+ device pci 1f.0 on # LPC bridge
+ chip superio/smsc/smscsuperio # SMSC SCH5504 Super I/O
+ device pnp 2e.0 on # Floppy
+ # global
+ irq 0x22 = 0x39
+ irq 0x2c = 0x10
+ #floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 0x06
+ drq 0x74 = 0x02
+ end
+ device pnp 2e.3 on # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 2
+ end
+ device pnp 2e.4 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.5 off end # COM2
+ device pnp 2e.7 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.a on # Runtime Regs
+ io 0x60 = 0x0c00
+ end
+ end
+ end
+ device pci 1f.1 on # IDE
+ end
+ device pci 1f.2 on # SATA
+ end
+ device pci 1f.3 on # SMBus
+ end
+ end
+ end
+end
diff --git a/src/mainboard/dell/gx520/dsdt.asl b/src/mainboard/dell/gx520/dsdt.asl
new file mode 100644
index 0000000..cbc1573
--- /dev/null
+++ b/src/mainboard/dell/gx520/dsdt.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20090419 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+
+ // General Purpose Events
+ //#include "acpi/gpe.asl"
+
+ // mainboard specific devices
+ #include "acpi/mainboard.asl"
+
+ // Thermal Zone
+ //#include "acpi/thermal.asl"
+
+ #include <cpu/intel/speedstep/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/i945/acpi/i945.asl>
+ #include <southbridge/intel/i82801gx/acpi/ich7.asl>
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/dell/gx520/gpio.c b/src/mainboard/dell/gx520/gpio.c
new file mode 100644
index 0000000..c60a86e
--- /dev/null
+++ b/src/mainboard/dell/gx520/gpio.c
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Arthur Heymans <arthur(a)aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_GPIO,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_GPIO,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_GPIO,
+ .gpio26 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_INPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_OUTPUT,
+ .gpio18 = GPIO_DIR_OUTPUT,
+ .gpio19 = GPIO_DIR_OUTPUT,
+ .gpio20 = GPIO_DIR_OUTPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio23 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio25 = GPIO_DIR_OUTPUT,
+ .gpio26 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio0 = GPIO_LEVEL_LOW,
+ .gpio1 = GPIO_LEVEL_HIGH,
+ .gpio2 = GPIO_LEVEL_LOW,
+ .gpio3 = GPIO_LEVEL_HIGH,
+ .gpio4 = GPIO_LEVEL_LOW,
+ .gpio6 = GPIO_LEVEL_HIGH,
+ .gpio7 = GPIO_LEVEL_LOW,
+ .gpio8 = GPIO_LEVEL_HIGH,
+ .gpio9 = GPIO_LEVEL_HIGH,
+ .gpio10 = GPIO_LEVEL_HIGH,
+ .gpio12 = GPIO_LEVEL_HIGH,
+ .gpio13 = GPIO_LEVEL_HIGH,
+ .gpio14 = GPIO_LEVEL_HIGH,
+ .gpio15 = GPIO_LEVEL_HIGH,
+ .gpio16 = GPIO_LEVEL_LOW,
+ .gpio18 = GPIO_LEVEL_HIGH,
+ .gpio19 = GPIO_LEVEL_HIGH,
+ .gpio20 = GPIO_LEVEL_HIGH,
+ .gpio21 = GPIO_LEVEL_HIGH,
+ .gpio22 = GPIO_LEVEL_LOW,
+ .gpio23 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio25 = GPIO_LEVEL_HIGH,
+ .gpio26 = GPIO_LEVEL_LOW,
+ .gpio27 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio9 = GPIO_INVERT,
+ .gpio10 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_OUTPUT,
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_HIGH,
+ .gpio33 = GPIO_LEVEL_LOW,
+ .gpio34 = GPIO_LEVEL_LOW,
+ .gpio35 = GPIO_LEVEL_LOW,
+ .gpio36 = GPIO_LEVEL_HIGH,
+ .gpio37 = GPIO_LEVEL_HIGH,
+ .gpio38 = GPIO_LEVEL_HIGH,
+ .gpio39 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+};
+
diff --git a/src/mainboard/dell/gx520/hda_verb.c b/src/mainboard/dell/gx520/hda_verb.c
new file mode 100644
index 0000000..1b57dfa
--- /dev/null
+++ b/src/mainboard/dell/gx520/hda_verb.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Arthur Heymans <arthur(a)aheymans.xyz>
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0662, /* Vendor ID */
+ 0x1458a002, /* Subsystem ID */
+ 0x00000009, /* Number of entries */
+
+ /* Pin Widget Verb Table */
+ AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+ AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x18, 0x01a19830),
+ AZALIA_PIN_CFG(0, 0x19, 0x02a19c31),
+ AZALIA_PIN_CFG(0, 0x1a, 0x0181303f),
+ AZALIA_PIN_CFG(0, 0x1b, 0x02214c1f),
+ AZALIA_PIN_CFG(0, 0x1c, 0x593301f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x4005c603),
+ AZALIA_PIN_CFG(0, 0x1e, 0x014b6120),
+};
+
+const u32 pc_beep_verbs[0] = {};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/gx520/romstage.c b/src/mainboard/dell/gx520/romstage.c
new file mode 100644
index 0000000..d9cecf2
--- /dev/null
+++ b/src/mainboard/dell/gx520/romstage.c
@@ -0,0 +1,177 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2016 Arthur Heymans arthur(a)aheymans.xyz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// __PRE_RAM__ means: use "unsigned" for device, not a struct.
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <lib.h>
+#include <arch/acpi.h>
+#include <timestamp.h>
+#include <console/console.h>
+#include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
+#include <northbridge/intel/i945/i945.h>
+#include <northbridge/intel/i945/raminit.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+#include <superio/smsc/smscsuperio/smscsuperio.h>
+
+#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
+
+static void ich7_enable_lpc(void)
+{
+ // Enable Serial IRQ
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0);
+ // Set COM1/COM2 decode range
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0000);
+ // Enable COM1
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN
+ | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMA_LPC_EN);
+ // Enable SuperIO Power Management Events
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0801);
+ /* LPC decode range 2: Environment Controller */
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00040291);
+}
+
+static void rcba_config(void)
+{
+ /* Enable IOAPIC */
+ RCBA8(OIC) = 0x03;
+
+ /* Disable unused devices */
+ RCBA32(FD) = 0x003c0061;
+
+ /* Enable PCIe Root Port Clock Gate */
+ RCBA32(CG) = 0x00000001;
+}
+
+static void early_ich7_init(void)
+{
+ uint8_t reg8;
+ uint32_t reg32;
+
+ // program secondary mlt XXX byte?
+ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
+
+ // reset rtc power status
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+ reg8 &= ~(1 << 2);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+
+ // usb transient disconnect
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
+ reg8 |= (3 << 0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
+
+ reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
+ reg32 |= (1 << 29) | (1 << 17);
+ pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
+
+ reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
+ reg32 |= (1 << 31) | (1 << 27);
+ pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+
+/*
+ RCBA32(0x0088) = 0x0011d000;
+ RCBA16(0x01fc) = 0x060f;
+ RCBA32(0x01f4) = 0x86000040;
+ RCBA32(0x0214) = 0x10030509;
+ RCBA32(0x0218) = 0x00020504;
+ RCBA8(0x0220) = 0xc5;
+ reg32 = RCBA32(GCS);
+ reg32 |= (1 << 6);
+ RCBA32(GCS) = reg32;
+ reg32 = RCBA32(0x3430);
+ reg32 &= ~(3 << 0);
+ reg32 |= (1 << 0);
+ RCBA32(0x3430) = reg32;
+ RCBA32(FD) |= (1 << 0);
+ RCBA16(0x0200) = 0x2008;
+ RCBA8(0x2027) = 0x0d;
+ RCBA16(0x3e08) |= (1 << 7);
+ RCBA16(0x3e48) |= (1 << 7);
+ RCBA32(0x3e0e) |= (1 << 7);
+ RCBA32(0x3e4e) |= (1 << 7);
+
+ // next step only on ich7m b0 and later:
+ reg32 = RCBA32(0x2034);
+ reg32 &= ~(0x0f << 16);
+ reg32 |= (5 << 16);
+ RCBA32(0x2034) = reg32;
+ */
+}
+
+void mainboard_romstage_entry(unsigned long bist)
+{
+ int s3resume = 0, boot_mode = 0;
+
+
+ timestamp_init(get_initial_timestamp());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
+ if (bist == 0)
+ enable_lapic();
+
+ ich7_enable_lpc();
+ /* Enable SuperIO PM */
+ smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+ /* Set up the console */
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ if (MCHBAR16(SSKPD) == 0xCAFE) {
+ printk(BIOS_DEBUG, "soft reset detected.\n");
+ boot_mode = 1;
+ }
+
+ /* Perform some early chipset initialization required
+ * before RAM initialization can work
+ */
+ i945_early_initialization();
+
+ s3resume = southbridge_detect_s3_resume();
+
+ /* Enable SPD ROMs and DDR-II DRAM */
+ enable_smbus();
+
+ dump_spd_registers();
+
+ timestamp_add_now(TS_BEFORE_INITRAM);
+ sdram_initialize(s3resume ? 2 : boot_mode, NULL);
+ timestamp_add_now(TS_AFTER_INITRAM);
+
+ /* Perform some initialization that must run before stage2 */
+ early_ich7_init();
+
+ /* This should probably go away. Until now it is required
+ * and mainboard specific
+ */
+ rcba_config();
+
+ /* Chipset Errata! */
+ fixup_i945_errata();
+
+ /* Initialize the internal PCIe links before we go into stage2 */
+ i945_late_initialization(s3resume);
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I0016dd35be67803e91ffefb0c87f54e35c93efcd
Gerrit-Change-Number: 29109
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>