coreboot-gerrit October 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: sb/intel/i82801jx: Use macros for LPC_EN
by Felix Held (Code Review) 15 Oct '18

15 Oct '18

Felix Held has submitted this change and it was merged. ( https://review.coreboot.org/29100 ) Change subject: sb/intel/i82801jx: Use macros for LPC_EN ...................................................................... sb/intel/i82801jx: Use macros for LPC_EN Change-Id: I4a9a9366c85206fa460519a26f48b3aada5bc7c3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/29100 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/intel/dg43gt/romstage.c M src/southbridge/intel/i82801jx/i82801jx.h 2 files changed, 14 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c index 64b462f..36aa149 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/romstage.c @@ -60,7 +60,10 @@ { /* Configure serial IRQs.*/ pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010); - pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3f0f); + pci_write_config16(LPC_DEV, D31F0_LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN + | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN + | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMB_LPC_EN | COMA_LPC_EN); pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0xfc0601); pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0xfc0291); pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0); diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 2e2d719..3c09746 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -99,6 +99,16 @@ #define D31F0_PIRQH_ROUT 0x6b #define D31F0_LPC_IODEC 0x80 #define D31F0_LPC_EN 0x82 +#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ +#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ +#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ +#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ +#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ +#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ +#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ +#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ +#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ +#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ #define D31F0_GEN1_DEC 0x84 #define D31F0_GEN2_DEC 0x88 #define D31F0_GEN3_DEC 0x8c -- To view, visit https://review.coreboot.org/29100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I4a9a9366c85206fa460519a26f48b3aada5bc7c3 Gerrit-Change-Number: 29100 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: add support to block smp in each stage
by Philipp Hug (Code Review) 15 Oct '18

15 Oct '18

Philipp Hug has posted comments on this change. ( https://review.coreboot.org/29024 ) Change subject: riscv: add support to block smp in each stage ...................................................................... Patch Set 11: (6 comments) Thanks! https://review.coreboot.org/#/c/29024/11/src/arch/riscv/boot.c File src/arch/riscv/boot.c: https://review.coreboot.org/#/c/29024/11/src/arch/riscv/boot.c@31 PS11, Line 31: static void arch_prog_run_help(struct prog *prog) suggestion: rename to do_arch_prog_run() https://review.coreboot.org/#/c/29024/11/src/arch/riscv/stages.c File src/arch/riscv/stages.c: https://review.coreboot.org/#/c/29024/11/src/arch/riscv/stages.c@35 PS11, Line 35: smp_pause(); this will only be reached by harts!=0 in romstage as the others are paused already in bootblock.s and romstage.s Can we make this more consistent? https://review.coreboot.org/#/c/29024/11/src/soc/sifive/fu540/Kconfig File src/soc/sifive/fu540/Kconfig: https://review.coreboot.org/#/c/29024/11/src/soc/sifive/fu540/Kconfig@42 PS11, Line 42: config RISCV_HART_NUM This should probably be done in 29023 https://review.coreboot.org/#/c/29024/11/src/soc/sifive/fu540/Makefile.inc File src/soc/sifive/fu540/Makefile.inc: https://review.coreboot.org/#/c/29024/11/src/soc/sifive/fu540/Makefile.inc@… PS11, Line 22: romstage-y += clint.c This should probably be done in 29023 https://review.coreboot.org/#/c/29024/11/src/soc/ucb/riscv/Makefile.inc File src/soc/ucb/riscv/Makefile.inc: https://review.coreboot.org/#/c/29024/11/src/soc/ucb/riscv/Makefile.inc@1 PS11, Line 1: ifeq ($(CONFIG_SOC_UCB_RISCV),y) This should probably be done in 29023 https://review.coreboot.org/#/c/29024/11/src/soc/ucb/riscv/ipi.c File src/soc/ucb/riscv/ipi.c: https://review.coreboot.org/#/c/29024/11/src/soc/ucb/riscv/ipi.c@1 PS11, Line 1: /* This file should probably be added in change 29023 instead -- To view, visit https://review.coreboot.org/29024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8d508c3d0f65a022010e74f8edad7ad2cfdc7dee Gerrit-Change-Number: 29024 Gerrit-PatchSet: 11 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 15 Oct 2018 11:26:11 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: add support smp_pause / smp_resume
by Philipp Hug (Code Review) 15 Oct '18

15 Oct '18

Philipp Hug has posted comments on this change. ( https://review.coreboot.org/29023 ) Change subject: riscv: add support smp_pause / smp_resume ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/#/c/29023/7/src/arch/riscv/smp.c File src/arch/riscv/smp.c: https://review.coreboot.org/#/c/29023/7/src/arch/riscv/smp.c@24 PS7, Line 24: if (read_csr(mhartid) != working_hartid) { > Can we move this check outside of this function to make the flow clearer? […] Or as an alternative: make it more clear that this function must be called by all harts. Also add synchronization code here to make sure all harts are here, before continuing on hart 0. -- To view, visit https://review.coreboot.org/29023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb Gerrit-Change-Number: 29023 Gerrit-PatchSet: 8 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 15 Oct 2018 11:14:07 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/skylake: Prevent disabling of TCO
by Naresh Solanki (Code Review) 15 Oct '18

15 Oct '18

Naresh Solanki has uploaded this change for review. ( https://review.coreboot.org/29108 Change subject: soc/intel/skylake: Prevent disabling of TCO ...................................................................... soc/intel/skylake: Prevent disabling of TCO If ACPI PM timer is disabled, TCO also gets disabled. FSP default config for EnableTcoTimer is disabled, this caused ACPI PM timer & TCO to be disabled by FSP even when config PmTimerDisable = 0. Thus update FSPS UPD EnableTcoTimer in accordance to devicetree config PmTimerDisable. BUG=None TEST= Build for Soraka with PmTimerDisable=0 & check if TCO caused reboot after running shell command: cat >> /dev/watchdog0 Change-Id: Ia146761036c9dbaef3c02c9a7122ae3dcdef7bdd Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- M src/soc/intel/skylake/chip_fsp20.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/29108/1 diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index a2a430e..7cc6de5 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -369,6 +369,7 @@ params->SataMode = config->SataMode; params->SataSpeedLimit = config->SataSpeedLimit; params->SataPwrOptEnable = config->SataPwrOptEnable; + params->EnableTcoTimer = !config->PmTimerDisabled; tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; -- To view, visit https://review.coreboot.org/29108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia146761036c9dbaef3c02c9a7122ae3dcdef7bdd Gerrit-Change-Number: 29108 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)intel.com>

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Change in coreboot[master]: riscv: add support smp_pause / smp_resume
by Xiang Wang (Code Review) 15 Oct '18

15 Oct '18

Xiang Wang has posted comments on this change. ( https://review.coreboot.org/29023 ) Change subject: riscv: add support smp_pause / smp_resume ...................................................................... Patch Set 8: (3 comments) https://review.coreboot.org/#/c/29023/7/src/arch/riscv/include/mcall.h File src/arch/riscv/include/mcall.h: https://review.coreboot.org/#/c/29023/7/src/arch/riscv/include/mcall.h@72 PS7, Line 72: /* > Can you clarify this comment? Done https://review.coreboot.org/#/c/29023/7/src/arch/riscv/smp.c File src/arch/riscv/smp.c: https://review.coreboot.org/#/c/29023/7/src/arch/riscv/smp.c@22 PS7, Line 22: void smp_pause(int working_hartid) > Could you add some comments here, especially that this function never returns. Done https://review.coreboot.org/#/c/29023/7/src/arch/riscv/smp.c@24 PS7, Line 24: if (read_csr(mhartid) != working_hartid) { > Can we move this check outside of this function to make the flow clearer? […] I want to pass the parameters to choose the cpu core to work. -- To view, visit https://review.coreboot.org/29023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb Gerrit-Change-Number: 29023 Gerrit-PatchSet: 8 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 15 Oct 2018 09:46:02 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: add support smp_pause / smp_resume
by Xiang Wang (Code Review) 15 Oct '18

15 Oct '18

Hello Shawn Chang, Jonathan Neuschäfer, build bot (Jenkins), Philipp Hug, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29023 to look at the new patch set (#8). Change subject: riscv: add support smp_pause / smp_resume ...................................................................... riscv: add support smp_pause / smp_resume See https://doc.coreboot.org/arch/riscv/ we know that we need to execute smp_pause at the start of each stage and smp_resume at the end of each stage. Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb Signed-off-by: Xiang Wang <wxjstz(a)126.com> --- M src/arch/riscv/Kconfig M src/arch/riscv/Makefile.inc A src/arch/riscv/include/arch/smp/smp.h M src/arch/riscv/include/mcall.h A src/arch/riscv/smp.c M src/soc/sifive/fu540/clint.c D src/soc/sifive/fu540/include/soc/clint.h 7 files changed, 103 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/29023/8 -- To view, visit https://review.coreboot.org/29023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb Gerrit-Change-Number: 29023 Gerrit-PatchSet: 8 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: riscv: add support smp_pause / smp_resume
by Philipp Hug (Code Review) 15 Oct '18

15 Oct '18

Philipp Hug has posted comments on this change. ( https://review.coreboot.org/29023 ) Change subject: riscv: add support smp_pause / smp_resume ...................................................................... Patch Set 7: (3 comments) Thanks! https://review.coreboot.org/#/c/29023/7/src/arch/riscv/include/mcall.h File src/arch/riscv/include/mcall.h: https://review.coreboot.org/#/c/29023/7/src/arch/riscv/include/mcall.h@72 PS7, Line 72: /* This function is used to operate msip by memory-mapped */ Can you clarify this comment? https://review.coreboot.org/#/c/29023/7/src/arch/riscv/smp.c File src/arch/riscv/smp.c: https://review.coreboot.org/#/c/29023/7/src/arch/riscv/smp.c@22 PS7, Line 22: void smp_pause(void) Could you add some comments here, especially that this function never returns. https://review.coreboot.org/#/c/29023/7/src/arch/riscv/smp.c@24 PS7, Line 24: if (read_csr(mhartid) == 0) Can we move this check outside of this function to make the flow clearer? Also the hart executing coreboot doesn't necessarily have to be 0 -- To view, visit https://review.coreboot.org/29023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb Gerrit-Change-Number: 29023 Gerrit-PatchSet: 7 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 15 Oct 2018 09:14:24 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: minnowmax: allow both 1333 and 1066 MHz memory SKUs
by build bot (Jenkins) (Code Review) 15 Oct '18

15 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27989 ) Change subject: minnowmax: allow both 1333 and 1066 MHz memory SKUs ...................................................................... Patch Set 4: (8 comments) https://review.coreboot.org/#/c/27989/4/src/mainboard/intel/minnowmax/romst… File src/mainboard/intel/minnowmax/romstage.c: https://review.coreboot.org/#/c/27989/4/src/mainboard/intel/minnowmax/romst… PS4, Line 61: .DRAMType = 1, /* DRAM Type: 0=DDR3, 1=DDR3L, 2=DDR3U, 4=LPDDR2, 5=LPDDR3, 6=DDR4*/ line over 80 characters https://review.coreboot.org/#/c/27989/4/src/mainboard/intel/minnowmax/romst… PS4, Line 65: .DIMMDensity = 1, /* DRAM device data density: 0=1Gb, 1=2Gb, 2=4Gb, 3=8Gb */ line over 80 characters https://review.coreboot.org/#/c/27989/4/src/mainboard/intel/minnowmax/romst… PS4, Line 66: .DIMMBusWidth = 3, /* DIMM Bus Width: 0=8bit, 1=16bit, 2=32bit, 3=64bit */ line over 80 characters https://review.coreboot.org/#/c/27989/4/src/mainboard/intel/minnowmax/romst… PS4, Line 69: .DIMMtRPtRCD = 11, /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */ line over 80 characters https://review.coreboot.org/#/c/27989/4/src/mainboard/intel/minnowmax/romst… PS4, Line 80: .DRAMType = 1, /* DRAM Type: 0=DDR3, 1=DDR3L, 2=DDR3U, 4=LPDDR2, 5=LPDDR3, 6=DDR4*/ line over 80 characters https://review.coreboot.org/#/c/27989/4/src/mainboard/intel/minnowmax/romst… PS4, Line 84: .DIMMDensity = 1, /* DRAM device data density: 0=1Gb, 1=2Gb, 2=4Gb, 3=8Gb */ line over 80 characters https://review.coreboot.org/#/c/27989/4/src/mainboard/intel/minnowmax/romst… PS4, Line 85: .DIMMBusWidth = 3, /* DIMM Bus Width: 0=8bit, 1=16bit, 2=32bit, 3=64bit */ line over 80 characters https://review.coreboot.org/#/c/27989/4/src/mainboard/intel/minnowmax/romst… PS4, Line 88: .DIMMtRPtRCD = 9, /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */ line over 80 characters -- To view, visit https://review.coreboot.org/27989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5e57dd419b443dfa742c8812cec87274af557728 Gerrit-Change-Number: 27989 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: York Yang <york.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 15 Oct 2018 08:21:42 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: sb/amd/pi/hudson: Add SPI controller support
by build bot (Jenkins) (Code Review) 15 Oct '18

15 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28719 ) Change subject: sb/amd/pi/hudson: Add SPI controller support ...................................................................... Patch Set 4: (24 comments) https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_d… File src/southbridge/amd/pi/hudson/pci_devs.h: https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_d… PS4, Line 34: #define XHCI_PCIDEV _PCI_DEV(XHCI_DEV,XHCI_FUNC) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_d… PS4, Line 40: #define XHCI2_PCIDEV _PCI_DEV(XHCI2_DEV,XHCI2_FUNC) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_d… PS4, Line 49: #define SATA_PCIDEV _PCI_DEV(SATA_DEV,SATA_FUNC) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_d… PS4, Line 65: #define OHCI1_PCIDEV _PCI_DEV(OHCI1_DEV,OHCI1_FUNC) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_d… PS4, Line 66: #define OHCI2_PCIDEV _PCI_DEV(OHCI2_DEV,OHCI2_FUNC) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_d… PS4, Line 67: #define OHCI3_PCIDEV _PCI_DEV(OHCI3_DEV,OHCI3_FUNC) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_d… PS4, Line 68: #define OHCI4_PCIDEV _PCI_DEV(OHCI4_DEV,OHCI4_FUNC) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_d… PS4, Line 81: #define EHCI1_PCIDEV _PCI_DEV(EHCI1_DEV,EHCI1_FUNC) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_d… PS4, Line 82: #define EHCI2_PCIDEV _PCI_DEV(EHCI2_DEV,EHCI2_FUNC) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_d… PS4, Line 83: #define EHCI3_PCIDEV _PCI_DEV(EHCI3_DEV,EHCI3_FUNC) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_d… PS4, Line 90: #define SMBUS_PCIDEV _PCI_DEV(SMBUS_DEV,SMBUS_FUNC) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_d… PS4, Line 98: #define IDE_PCIDEV _PCI_DEV(IDE_DEV,IDE_FUNC) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_d… PS4, Line 106: #define HDA_PCIDEV _PCI_DEV(HDA_DEV,HDA_FUNC) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_d… PS4, Line 114: #define LPC_PCIDEV _PCI_DEV(LPC_DEV,LPC_FUNC) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_d… PS4, Line 121: #define SB_PCI_PORT_PCIDEV _PCI_DEV(SB_PCI_PORT_DEV,SB_PCI_PORT_FUNC) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_d… PS4, Line 128: #define SD_PCIDEV _PCI_DEV(SD_DEV,SD_FUNC) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_d… PS4, Line 145: #define SB_PCIE_PORT1_PCIDEV _PCI_DEV(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_d… PS4, Line 146: #define SB_PCIE_PORT2_PCIDEV _PCI_DEV(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_d… PS4, Line 147: #define SB_PCIE_PORT3_PCIDEV _PCI_DEV(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_d… PS4, Line 148: #define SB_PCIE_PORT4_PCIDEV _PCI_DEV(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC) space required after that ',' (ctx:VxV) https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/spi.c File src/southbridge/amd/pi/hudson/spi.c: https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/spi.c… PS4, Line 117: while ((spi_read8(SPI_REG_CNTRL02) & CNTRL02_EXEC_OPCODE) && trailing statements should be on next line https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/spi.c… PS4, Line 165: for (count = 0; count < bytesout; count++, dout++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/spi.c… PS4, Line 174: for (count = 0; count < bytesout; count++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/spi.c… PS4, Line 178: for (count = 0; count < bytesin; count++, din++) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/28719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icc6feb433a19337e09fc394cbf30288f53b195dd Gerrit-Change-Number: 28719 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Comment-Date: Mon, 15 Oct 2018 08:05:10 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/lenovo/*/romstage: Remove explicit power-on defaults
by Peter Lemenkov (Code Review) 15 Oct '18

15 Oct '18

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/29107 Change subject: mb/lenovo/*/romstage: Remove explicit power-on defaults ...................................................................... mb/lenovo/*/romstage: Remove explicit power-on defaults Change-Id: Ib359e4039f87bb87faac040f24f70cc0988c0ea8 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/l520/romstage.c M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t430s/romstage.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/romstage.c M src/mainboard/lenovo/x220/romstage.c M src/mainboard/lenovo/x230/romstage.c 8 files changed, 1 insertion(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/29107/1 diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c index 0f6ffed..61319f5 100644 --- a/src/mainboard/lenovo/l520/romstage.c +++ b/src/mainboard/lenovo/l520/romstage.c @@ -34,8 +34,8 @@ void mainboard_rcba_config(void) { - RCBA32(0x3414) = 0x00000000; } + const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, -1 }, { 1, 0, -1 }, diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c index bef2562..aad8348 100644 --- a/src/mainboard/lenovo/t420/romstage.c +++ b/src/mainboard/lenovo/t420/romstage.c @@ -65,7 +65,6 @@ void mainboard_rcba_config(void) { - RCBA32(BUC) = 0; } // OC3 set in bios to port 2-7, OC7 set in bios to port 10-13 diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c index be8052c..8004e2f 100644 --- a/src/mainboard/lenovo/t420s/romstage.c +++ b/src/mainboard/lenovo/t420s/romstage.c @@ -67,7 +67,6 @@ void mainboard_rcba_config(void) { - RCBA32(BUC) = 0; } const struct southbridge_usb_port mainboard_usb_ports[] = { diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c index 633ba3f..b409b5e 100644 --- a/src/mainboard/lenovo/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/romstage.c @@ -40,7 +40,6 @@ void mainboard_rcba_config(void) { - RCBA32(BUC) = 0; } const struct southbridge_usb_port mainboard_usb_ports[] = { diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 4fcd651..cdd0d45 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -77,7 +77,6 @@ void mainboard_rcba_config(void) { - RCBA32(BUC) = 0; } const struct southbridge_usb_port mainboard_usb_ports[] = { diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 88e07c1..68dd694 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -69,7 +69,6 @@ void mainboard_rcba_config(void) { - RCBA32(BUC) = 0; } void mainboard_early_init(int s3resume) diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index 96e0284..6efcd01 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -50,7 +50,6 @@ void mainboard_rcba_config(void) { - RCBA32(BUC) = 0; } void mainboard_fill_pei_data(struct pei_data *pei_data) diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 1ddaedf..94bcab3 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -48,7 +48,6 @@ void mainboard_rcba_config(void) { - RCBA32(BUC) = 0; } const struct southbridge_usb_port mainboard_usb_ports[] = { -- To view, visit https://review.coreboot.org/29107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib359e4039f87bb87faac040f24f70cc0988c0ea8 Gerrit-Change-Number: 29107 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com>

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coreboot-gerrit October 2018