coreboot-gerrit October 2018

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Change in coreboot[master]: tpm/tspi: clean up tpm_setup function flow
by Philipp Deppenwiese (Code Review) 19 Oct '18

19 Oct '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/29026 ) Change subject: tpm/tspi: clean up tpm_setup function flow ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/29026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibea44880683a301e82ee2ba049003c36fcb44eba Gerrit-Change-Number: 29026 Gerrit-PatchSet: 5 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 18 Oct 2018 16:22:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: cpu/x86/smm: Fix non-local header treated as local
by Patrick Georgi (Code Review) 19 Oct '18

19 Oct '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29105 ) Change subject: cpu/x86/smm: Fix non-local header treated as local ...................................................................... cpu/x86/smm: Fix non-local header treated as local Change-Id: I15dfe0332fd87db61d692a94bf1fd5d00dfb83d4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/29105 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/cpu/x86/smm/smmrelocate.S 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 56e73cd..16bccbc 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -22,13 +22,13 @@ // It's needed right now because we get our DEFAULT_PMBASE from // here. #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) -#include "../../../southbridge/intel/i82801gx/i82801gx.h" +#include <southbridge/intel/i82801gx/i82801gx.h> #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801DX) -#include "../../../southbridge/intel/i82801dx/i82801dx.h" +#include <southbridge/intel/i82801dx/i82801dx.h> #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801IX) -#include "../../../southbridge/intel/i82801ix/i82801ix.h" +#include <southbridge/intel/i82801ix/i82801ix.h> #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801JX) -#include "../../../southbridge/intel/i82801jx/i82801jx.h" +#include <southbridge/intel/i82801jx/i82801jx.h> #else #error "Southbridge needs SMM handler support." -- To view, visit https://review.coreboot.org/29105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I15dfe0332fd87db61d692a94bf1fd5d00dfb83d4 Gerrit-Change-Number: 29105 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: cpu/x86/smm: Fix non-local header treated as local
by Patrick Georgi (Code Review) 19 Oct '18

19 Oct '18

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/29105 ) Change subject: cpu/x86/smm: Fix non-local header treated as local ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I15dfe0332fd87db61d692a94bf1fd5d00dfb83d4 Gerrit-Change-Number: 29105 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 18 Oct 2018 16:21:19 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: arch/x86/acpi: Add TPM2 table support
by Philipp Deppenwiese (Code Review) 19 Oct '18

19 Oct '18

Hello Werner Zeh, Patrick Rudolph, build bot (Jenkins), Joel Kitching, Vadim Bendebury, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29181 to look at the new patch set (#3). Change subject: arch/x86/acpi: Add TPM2 table support ...................................................................... arch/x86/acpi: Add TPM2 table support * Distinguish between TPM 1.2 and 2.0 ACPI table support * Add TPM2 table support for TIS interface only Change-Id: I030c7ea744bcfe61ebef8d66d1295273b5dccda5 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/arch/x86/acpi.c M src/arch/x86/include/arch/acpi.h 2 files changed, 55 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/29181/3 -- To view, visit https://review.coreboot.org/29181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I030c7ea744bcfe61ebef8d66d1295273b5dccda5 Gerrit-Change-Number: 29181 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: arch/x86/acpi: Add TPM2 table support
by Philipp Deppenwiese (Code Review) 19 Oct '18

19 Oct '18

Hello Werner Zeh, Patrick Rudolph, build bot (Jenkins), Joel Kitching, Vadim Bendebury, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29181 to look at the new patch set (#2). Change subject: arch/x86/acpi: Add TPM2 table support ...................................................................... arch/x86/acpi: Add TPM2 table support * Distinguish between TPM 1.2 and 2.0 ACPI table support * Add TPM2 table support for TIS interface only Change-Id: I030c7ea744bcfe61ebef8d66d1295273b5dccda5 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/arch/x86/acpi.c M src/arch/x86/include/arch/acpi.h 2 files changed, 55 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/29181/2 -- To view, visit https://review.coreboot.org/29181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I030c7ea744bcfe61ebef8d66d1295273b5dccda5 Gerrit-Change-Number: 29181 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: arch/x86/acpi: Add TPM2 table support
by Philipp Deppenwiese (Code Review) 19 Oct '18

19 Oct '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/29181 Change subject: arch/x86/acpi: Add TPM2 table support ...................................................................... arch/x86/acpi: Add TPM2 table support * Distinguish between TPM 1.2 and 2.0 ACPI table support * Add TPM2 table support for TIS interface only Change-Id: I030c7ea744bcfe61ebef8d66d1295273b5dccda5 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/arch/x86/acpi.c M src/arch/x86/include/arch/acpi.h 2 files changed, 55 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/29181/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 1b43004..286b56a 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -308,6 +308,30 @@ header->checksum = acpi_checksum((void *)tcpa, header->length); } +static void acpi_create_tpm2(acpi_tpm2_t *tpm2) +{ + acpi_header_t *header = &(tpm2->header); + + memset((void *)tpm2, 0, sizeof(acpi_tpm2_t)); + + /* Fill out header fields. */ + memcpy(header->signature, "TPM2", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_tpm2_t); + header->revision = get_acpi_table_revision(TPM2); + + tpm2->platform_class = 0; // Always pc platform.. + tpm2->control_area = 0; // no CRB interface support + tpm2->start_method = 6; // no CRB interface support + tpm2->psp = 0; + + /* Calculate checksum. */ + header->checksum = acpi_checksum((void *)tpm2, header->length); +} + static void acpi_ssdt_write_cbtable(void) { const struct cbmem_entry *cbtable; @@ -1163,13 +1187,26 @@ acpi_add_table(rsdp, mcfg); } - printk(BIOS_DEBUG, "ACPI: * TCPA\n"); - tcpa = (acpi_tcpa_t *) current; - acpi_create_tcpa(tcpa); - if (tcpa->header.length >= sizeof(acpi_tcpa_t)) { - current += tcpa->header.length; - current = acpi_align_current(current); - acpi_add_table(rsdp, tcpa); + if (IS_DEFINED(CONFIG_TPM1)) { + printk(BIOS_DEBUG, "ACPI: * TCPA\n"); + tcpa = (acpi_tcpa_t *) current; + acpi_create_tcpa(tcpa); + if (tcpa->header.length >= sizeof(acpi_tcpa_t)) { + current += tcpa->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, tcpa); + } + } + + if (IS_DEFINED(CONFIG_TPM2)) { + printk(BIOS_DEBUG, "ACPI: * TPM2\n"); + tpm2 = (acpi_tpm2_t *) current; + acpi_create_tpm2(tpm2); + if (tpm2->header.length >= sizeof(acpi_tpm2_t)) { + current += tpm2->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, tpm2); + } } printk(BIOS_DEBUG, "ACPI: * MADT\n"); @@ -1288,6 +1325,8 @@ return 1; case TCPA: return 2; + case TPM2: + return 4; case SSDT: /* ACPI 1.0/2.0: ?, ACPI 3.0/4.0: 2 */ return 2; case SRAT: /* ACPI 1.0: N/A, 2.0: 1, 3.0: 2, 4.0: 3 */ diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 54be1f4..5cf89da 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -191,6 +191,15 @@ u64 lasa; } __packed acpi_tcpa_t; +typedef struct acpi_tpm2 { + struct acpi_table_header header; + u16 platform_class; + u8 reserved[2]; + u64 control_area; + u32 start_method + u64 psp; +} __packed acpi_tpm2_t; + typedef struct acpi_mcfg_mmconfig { u32 base_address; u32 base_reserved; -- To view, visit https://review.coreboot.org/29181 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I030c7ea744bcfe61ebef8d66d1295273b5dccda5 Gerrit-Change-Number: 29181 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: mb/lenovo/*/romstage: No need to specify board's model in comments
by Peter Lemenkov (Code Review) 18 Oct '18

18 Oct '18

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/29180 Change subject: mb/lenovo/*/romstage: No need to specify board's model in comments ...................................................................... mb/lenovo/*/romstage: No need to specify board's model in comments This is a cosmetic one. It just removes some board names from comments since these functions sometimes are very similar, so no need to add extra difference between them. Change-Id: I26b9296b402d98bcf048580da51da7bbb0c237e4 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/romstage.c M src/mainboard/lenovo/x201/romstage.c M src/mainboard/lenovo/x220/romstage.c M src/mainboard/lenovo/x230/romstage.c 6 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/29180/1 diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 4fcd651..8769f01 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -63,7 +63,7 @@ void pch_enable_lpc(void) { - /* T520 EC Decode Range Port60/64, Port62/66 */ + /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 88e07c1..ac8c514 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -55,7 +55,7 @@ void pch_enable_lpc(void) { - /* X230 EC Decode Range Port60/64, Port62/66 */ + /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c index a34d1db..bd1c6a3 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c @@ -36,7 +36,7 @@ void pch_enable_lpc(void) { - /* X230 EC Decode Range Port60/64, Port62/66 */ + /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 8752949..b6efbd7 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -45,7 +45,7 @@ static void pch_enable_lpc(void) { - /* X201 EC Decode Range Port60/64, Port62/66 */ + /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index 96e0284..fb25f79 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -36,7 +36,7 @@ void pch_enable_lpc(void) { - /* X230 EC Decode Range Port60/64, Port62/66 */ + /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 1ddaedf..91b90d2 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -34,7 +34,7 @@ void pch_enable_lpc(void) { - /* X230 EC Decode Range Port60/64, Port62/66 */ + /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); -- To view, visit https://review.coreboot.org/29180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I26b9296b402d98bcf048580da51da7bbb0c237e4 Gerrit-Change-Number: 29180 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com>

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Change in coreboot[master]: mb: Fix non-local header treated as local
by Patrick Georgi (Code Review) 18 Oct '18

18 Oct '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/29098 ) Change subject: mb: Fix non-local header treated as local ...................................................................... mb: Fix non-local header treated as local Change-Id: Ib39305effdb00e032ca07e6d0e0d84cdf3dcf916 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/29098 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/amd/inagua/mainboard.c M src/mainboard/amd/inagua/mptable.c M src/mainboard/amd/lamar/romstage.c M src/mainboard/amd/persimmon/mainboard.c M src/mainboard/amd/persimmon/mptable.c M src/mainboard/amd/south_station/mainboard.c M src/mainboard/amd/south_station/mptable.c M src/mainboard/amd/torpedo/fadt.c M src/mainboard/amd/torpedo/gpio.c M src/mainboard/amd/torpedo/mptable.c M src/mainboard/amd/union_station/mainboard.c M src/mainboard/amd/union_station/mptable.c M src/mainboard/asrock/e350m1/mainboard.c M src/mainboard/asus/kcma-d8/dsdt.asl M src/mainboard/asus/kgpe-d16/dsdt.asl M src/mainboard/asus/p2b-ls/dsdt.asl M src/mainboard/asus/p2b/dsdt.asl M src/mainboard/elmex/pcm205400/mainboard.c M src/mainboard/elmex/pcm205400/mptable.c M src/mainboard/gizmosphere/gizmo/mainboard.c M src/mainboard/gizmosphere/gizmo/mptable.c M src/mainboard/google/beltino/acpi/superio.asl M src/mainboard/google/jecht/acpi/superio.asl M src/mainboard/intel/baskingridge/acpi/superio.asl M src/mainboard/intel/baskingridge/dsdt.asl M src/mainboard/intel/cougar_canyon2/acpi/superio.asl M src/mainboard/intel/dcp847ske/acpi/superio.asl M src/mainboard/intel/emeraldlake2/acpi/superio.asl M src/mainboard/intel/emeraldlake2/dsdt.asl M src/mainboard/lippert/frontrunner-af/mainboard.c M src/mainboard/lippert/frontrunner-af/mptable.c M src/mainboard/lippert/toucan-af/mainboard.c M src/mainboard/lippert/toucan-af/mptable.c M src/mainboard/pcengines/apu1/gpio_ftns.c M src/mainboard/pcengines/apu1/mainboard.c M src/mainboard/pcengines/apu1/mptable.c M src/mainboard/samsung/lumpy/acpi/superio.asl M src/mainboard/samsung/stumpy/acpi/superio.asl 38 files changed, 41 insertions(+), 61 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index 4be64f5..c4fc3b8 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -15,9 +15,8 @@ #include <console/console.h> #include <device/device.h> - #include <southbridge/amd/sb800/sb800.h> -#include "SBPLATFORM.h" /* Platform Specific Definitions */ +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /* Platform Specific Definitions */ static void init_gpios(void) { diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c index a1285a2..c02fb46 100644 --- a/src/mainboard/amd/inagua/mptable.c +++ b/src/mainboard/amd/inagua/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> @@ -21,7 +20,7 @@ #include <arch/ioapic.h> #include <string.h> #include <stdint.h> -#include <SBPLATFORM.h> +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> u8 intr_data[] = { [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index d8930c3..136e392 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -32,7 +32,7 @@ #include <cpu/x86/lapic.h> #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/pi/hudson/hudson.h> -#include "superio/fintek/f81216h/f81216h.h" +#include <superio/fintek/f81216h/f81216h.h> #define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1) diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 95aec3d..3fe513f 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -17,10 +17,9 @@ #include <console/console.h> #include <device/device.h> #include <arch/io.h> - #include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/cimx/cimx_util.h> -#include "SBPLATFORM.h" +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/cimx/sb800/pci_devs.h> #include <northbridge/amd/agesa/family14/pci_devs.h> diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index 9e92ae8..d153c79 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -14,14 +14,13 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> #include <arch/io.h> #include <string.h> #include <stdint.h> -#include <SBPLATFORM.h> +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/common/amd_pci_util.h> #include <drivers/generic/ioapic/chip.h> #include <arch/ioapic.h> diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index 1587d32..8932f7a 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -16,9 +16,8 @@ #include <console/console.h> #include <delay.h> #include <device/device.h> - #include <southbridge/amd/sb800/sb800.h> -#include "SBPLATFORM.h" /* Platform Specific Definitions */ +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /* Platform Specific Definitions */ /** * Southstation using SB GPIO 17/18 to control the Red/Green LED diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c index 152b959..93b68dd 100644 --- a/src/mainboard/amd/south_station/mptable.c +++ b/src/mainboard/amd/south_station/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> @@ -21,8 +20,7 @@ #include <arch/ioapic.h> #include <string.h> #include <stdint.h> -#include <SBPLATFORM.h> - +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> u8 intr_data[] = { [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ diff --git a/src/mainboard/amd/torpedo/fadt.c b/src/mainboard/amd/torpedo/fadt.c index 56a90a6..4de149d8 100644 --- a/src/mainboard/amd/torpedo/fadt.c +++ b/src/mainboard/amd/torpedo/fadt.c @@ -18,13 +18,12 @@ * ACPI - create the Fixed ACPI Description Tables (FADT) */ - #include <string.h> #include <console/console.h> #include <arch/acpi.h> #include <arch/io.h> #include <device/device.h> -#include "SbPlatform.h" +#include <southbridge/amd/cimx/sb900/SbPlatform.h> /*extern*/ u16 pm_base = 0x800; /* pm_base should be set in sb ACPI */ diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c index e26052a..7633cf3 100644 --- a/src/mainboard/amd/torpedo/gpio.c +++ b/src/mainboard/amd/torpedo/gpio.c @@ -13,9 +13,9 @@ * GNU General Public License for more details. */ -#include "SbPlatform.h" +#include <southbridge/amd/cimx/sb900/SbPlatform.h> #include "gpio.h" -#include "vendorcode/amd/cimx/sb900/AmdSbLib.h" +#include <vendorcode/amd/cimx/sb900/AmdSbLib.h> #ifndef SB_GPIO_REG01 diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c index f06fb75..47ae625 100644 --- a/src/mainboard/amd/torpedo/mptable.c +++ b/src/mainboard/amd/torpedo/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> @@ -22,7 +21,7 @@ #include <stdint.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include "SbPlatform.h" +#include <southbridge/amd/cimx/sb900/SbPlatform.h> #define IO_APIC_ID CONFIG_MAX_CPUS u32 apicid_sb900; diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index 7ed27d8..402bc36 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -15,9 +15,8 @@ #include <console/console.h> #include <device/device.h> - #include <southbridge/amd/sb800/sb800.h> -#include "SBPLATFORM.h" /* Platform Specific Definitions */ +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /* Platform Specific Definitions */ /********************************************** * Enable the dedicated functions of the board. diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c index 152b959..93b68dd 100644 --- a/src/mainboard/amd/union_station/mptable.c +++ b/src/mainboard/amd/union_station/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> @@ -21,8 +20,7 @@ #include <arch/ioapic.h> #include <string.h> #include <stdint.h> -#include <SBPLATFORM.h> - +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> u8 intr_data[] = { [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index f837842..35aa9ec 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -16,9 +16,8 @@ #include <console/console.h> #include <device/device.h> #include <arch/io.h> - #include <southbridge/amd/cimx/cimx_util.h> -#include "SBPLATFORM.h" +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /********************************************** * Enable the dedicated functions of the board. diff --git a/src/mainboard/asus/kcma-d8/dsdt.asl b/src/mainboard/asus/kcma-d8/dsdt.asl index b6dd211..d05c6d7 100644 --- a/src/mainboard/asus/kcma-d8/dsdt.asl +++ b/src/mainboard/asus/kcma-d8/dsdt.asl @@ -557,7 +557,7 @@ }) } - #include "../../../superio/winbond/w83667hg-a/ps2_controller.asl" + #include <superio/winbond/w83667hg-a/ps2_controller.asl> /* UART 1 */ Device (URT1) diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl index 7b78b5d..099aca5 100644 --- a/src/mainboard/asus/kgpe-d16/dsdt.asl +++ b/src/mainboard/asus/kgpe-d16/dsdt.asl @@ -557,7 +557,7 @@ }) } - #include "../../../superio/winbond/w83667hg-a/ps2_controller.asl" + #include <superio/winbond/w83667hg-a/ps2_controller.asl> /* UART 1 */ Device (URT1) diff --git a/src/mainboard/asus/p2b-ls/dsdt.asl b/src/mainboard/asus/p2b-ls/dsdt.asl index 73d9508..9bcf68c 100644 --- a/src/mainboard/asus/p2b-ls/dsdt.asl +++ b/src/mainboard/asus/p2b-ls/dsdt.asl @@ -248,7 +248,7 @@ } } - #include "superio/winbond/w83977tf/acpi/superio.asl" + #include <superio/winbond/w83977tf/acpi/superio.asl> } } diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 93f6afe..c49e584 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -234,7 +234,7 @@ } } - #include "superio/winbond/w83977tf/acpi/superio.asl" + #include <superio/winbond/w83977tf/acpi/superio.asl> } } diff --git a/src/mainboard/elmex/pcm205400/mainboard.c b/src/mainboard/elmex/pcm205400/mainboard.c index 8f8b735..3fe513f 100644 --- a/src/mainboard/elmex/pcm205400/mainboard.c +++ b/src/mainboard/elmex/pcm205400/mainboard.c @@ -19,7 +19,7 @@ #include <arch/io.h> #include <southbridge/amd/common/amd_pci_util.h> #include <southbridge/amd/cimx/cimx_util.h> -#include "SBPLATFORM.h" +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/cimx/sb800/pci_devs.h> #include <northbridge/amd/agesa/family14/pci_devs.h> diff --git a/src/mainboard/elmex/pcm205400/mptable.c b/src/mainboard/elmex/pcm205400/mptable.c index 9e92ae8..d153c79 100644 --- a/src/mainboard/elmex/pcm205400/mptable.c +++ b/src/mainboard/elmex/pcm205400/mptable.c @@ -14,14 +14,13 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> #include <arch/io.h> #include <string.h> #include <stdint.h> -#include <SBPLATFORM.h> +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/common/amd_pci_util.h> #include <drivers/generic/ioapic/chip.h> #include <arch/ioapic.h> diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index b02af0d..ecd770b 100644 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -20,9 +20,8 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> - #include <southbridge/amd/sb800/sb800.h> -#include "SBPLATFORM.h" +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> /********************************************** * Enable the dedicated functions of the board. diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c index b248a0b..868c8b4 100644 --- a/src/mainboard/gizmosphere/gizmo/mptable.c +++ b/src/mainboard/gizmosphere/gizmo/mptable.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> @@ -22,8 +21,7 @@ #include <arch/ioapic.h> #include <string.h> #include <stdint.h> -#include <SBPLATFORM.h> - +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> u8 intr_data[] = { [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ diff --git a/src/mainboard/google/beltino/acpi/superio.asl b/src/mainboard/google/beltino/acpi/superio.asl index f690787..7ccdf14 100644 --- a/src/mainboard/google/beltino/acpi/superio.asl +++ b/src/mainboard/google/beltino/acpi/superio.asl @@ -28,4 +28,4 @@ #define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 #define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 -#include "superio/ite/it8772f/acpi/superio.asl" +#include <superio/ite/it8772f/acpi/superio.asl> diff --git a/src/mainboard/google/jecht/acpi/superio.asl b/src/mainboard/google/jecht/acpi/superio.asl index 1d37792..b773d7a 100644 --- a/src/mainboard/google/jecht/acpi/superio.asl +++ b/src/mainboard/google/jecht/acpi/superio.asl @@ -28,4 +28,4 @@ #define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 #define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 -#include "superio/ite/it8772f/acpi/superio.asl" +#include <superio/ite/it8772f/acpi/superio.asl> diff --git a/src/mainboard/intel/baskingridge/acpi/superio.asl b/src/mainboard/intel/baskingridge/acpi/superio.asl index 7944d9f..61b0e60 100644 --- a/src/mainboard/intel/baskingridge/acpi/superio.asl +++ b/src/mainboard/intel/baskingridge/acpi/superio.asl @@ -28,4 +28,4 @@ #define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 #define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 -#include "superio/smsc/sio1007/acpi/superio.asl" +#include <superio/smsc/sio1007/acpi/superio.asl> diff --git a/src/mainboard/intel/baskingridge/dsdt.asl b/src/mainboard/intel/baskingridge/dsdt.asl index e4b489c..1871c3a 100644 --- a/src/mainboard/intel/baskingridge/dsdt.asl +++ b/src/mainboard/intel/baskingridge/dsdt.asl @@ -36,7 +36,7 @@ #include "acpi/thermal.asl" - #include "../../../cpu/intel/haswell/acpi/cpu.asl" + #include <cpu/intel/haswell/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/intel/cougar_canyon2/acpi/superio.asl b/src/mainboard/intel/cougar_canyon2/acpi/superio.asl index 92d951d..07e4187 100644 --- a/src/mainboard/intel/cougar_canyon2/acpi/superio.asl +++ b/src/mainboard/intel/cougar_canyon2/acpi/superio.asl @@ -28,4 +28,4 @@ #define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 #define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 -#include "superio/smsc/sio1007/acpi/superio.asl" +#include <superio/smsc/sio1007/acpi/superio.asl> diff --git a/src/mainboard/intel/dcp847ske/acpi/superio.asl b/src/mainboard/intel/dcp847ske/acpi/superio.asl index aefb51d..8adc853 100644 --- a/src/mainboard/intel/dcp847ske/acpi/superio.asl +++ b/src/mainboard/intel/dcp847ske/acpi/superio.asl @@ -25,4 +25,4 @@ #define NCT6776_SHOW_HWM 1 #define NCT6776_SHOW_GPIO 1 -#include "superio/nuvoton/nct6776/acpi/superio.asl" +#include <superio/nuvoton/nct6776/acpi/superio.asl> diff --git a/src/mainboard/intel/emeraldlake2/acpi/superio.asl b/src/mainboard/intel/emeraldlake2/acpi/superio.asl index 7944d9f..61b0e60 100644 --- a/src/mainboard/intel/emeraldlake2/acpi/superio.asl +++ b/src/mainboard/intel/emeraldlake2/acpi/superio.asl @@ -28,4 +28,4 @@ #define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 #define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 -#include "superio/smsc/sio1007/acpi/superio.asl" +#include <superio/smsc/sio1007/acpi/superio.asl> diff --git a/src/mainboard/intel/emeraldlake2/dsdt.asl b/src/mainboard/intel/emeraldlake2/dsdt.asl index fc6fd1e..26c41c4 100644 --- a/src/mainboard/intel/emeraldlake2/dsdt.asl +++ b/src/mainboard/intel/emeraldlake2/dsdt.asl @@ -37,7 +37,7 @@ // General Purpose Events //#include "acpi/gpe.asl" - #include "../../../cpu/intel/model_206ax/acpi/cpu.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) diff --git a/src/mainboard/lippert/frontrunner-af/mainboard.c b/src/mainboard/lippert/frontrunner-af/mainboard.c index 80810cc..3866035 100644 --- a/src/mainboard/lippert/frontrunner-af/mainboard.c +++ b/src/mainboard/lippert/frontrunner-af/mainboard.c @@ -21,8 +21,8 @@ #include <device/pci_def.h> #include <southbridge/amd/sb800/sb800.h> #include <arch/acpi.h> -#include "SBPLATFORM.h" -#include "OEM.h" /* SMBUS0_BASE_ADDRESS */ +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> +#include <vendorcode/amd/cimx/sb800/OEM.h> /* SMBUS0_BASE_ADDRESS */ #include <southbridge/amd/cimx/sb800/gpio_oem.h> #include "sema.h" diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c index e8257bd..e4a1051 100644 --- a/src/mainboard/lippert/frontrunner-af/mptable.c +++ b/src/mainboard/lippert/frontrunner-af/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> @@ -21,7 +20,7 @@ #include <arch/ioapic.h> #include <string.h> #include <stdint.h> -#include <SBPLATFORM.h> +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> u8 intr_data[] = { [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index c6ab265..3de388b 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -21,8 +21,8 @@ #include <device/pci_def.h> #include <southbridge/amd/sb800/sb800.h> #include <arch/acpi.h> -#include "SBPLATFORM.h" -#include "OEM.h" /* SMBUS0_BASE_ADDRESS */ +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> +#include <vendorcode/amd/cimx/sb800/OEM.h> /* SMBUS0_BASE_ADDRESS */ #include <southbridge/amd/cimx/sb800/gpio_oem.h> #include "mainboard/lippert/frontrunner-af/sema.h" diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c index e8257bd..e4a1051 100644 --- a/src/mainboard/lippert/toucan-af/mptable.c +++ b/src/mainboard/lippert/toucan-af/mptable.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> @@ -21,7 +20,7 @@ #include <arch/ioapic.h> #include <string.h> #include <stdint.h> -#include <SBPLATFORM.h> +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> u8 intr_data[] = { [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.c b/src/mainboard/pcengines/apu1/gpio_ftns.c index 018fc0a..74c3b7b 100644 --- a/src/mainboard/pcengines/apu1/gpio_ftns.c +++ b/src/mainboard/pcengines/apu1/gpio_ftns.c @@ -15,7 +15,7 @@ #include <stdint.h> #include <arch/io.h> -#include "SBPLATFORM.h" +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/cimx/cimx_util.h> #include "gpio_ftns.h" diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index de94937..1105d5f 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -24,7 +24,7 @@ #include <arch/acpi.h> #include <smbios.h> #include <string.h> -#include "SBPLATFORM.h" +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/cimx/sb800/pci_devs.h> #include <northbridge/amd/agesa/family14/pci_devs.h> #include <superio/nuvoton/nct5104d/nct5104d.h> diff --git a/src/mainboard/pcengines/apu1/mptable.c b/src/mainboard/pcengines/apu1/mptable.c index 94a7d6f..eacdc73 100644 --- a/src/mainboard/pcengines/apu1/mptable.c +++ b/src/mainboard/pcengines/apu1/mptable.c @@ -14,14 +14,13 @@ * GNU General Public License for more details. */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> #include <arch/io.h> #include <string.h> #include <stdint.h> -#include <SBPLATFORM.h> +#include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/common/amd_pci_util.h> #include <drivers/generic/ioapic/chip.h> #include <arch/ioapic.h> diff --git a/src/mainboard/samsung/lumpy/acpi/superio.asl b/src/mainboard/samsung/lumpy/acpi/superio.asl index 0de8650..988ec42 100644 --- a/src/mainboard/samsung/lumpy/acpi/superio.asl +++ b/src/mainboard/samsung/lumpy/acpi/superio.asl @@ -31,4 +31,4 @@ #define SIO_ENABLE_SMBX // pnp 2e.9: Enable Mailbox #define SIO_SMBX_IO0 0xa00 // pnp 2e.9: io 0xa00 -#include "superio/smsc/mec1308/acpi/superio.asl" +#include <superio/smsc/mec1308/acpi/superio.asl> diff --git a/src/mainboard/samsung/stumpy/acpi/superio.asl b/src/mainboard/samsung/stumpy/acpi/superio.asl index 1262211..5ec96a4 100644 --- a/src/mainboard/samsung/stumpy/acpi/superio.asl +++ b/src/mainboard/samsung/stumpy/acpi/superio.asl @@ -28,4 +28,4 @@ #define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 #define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 -#include "superio/ite/it8772f/acpi/superio.asl" +#include <superio/ite/it8772f/acpi/superio.asl> -- To view, visit https://review.coreboot.org/29098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ib39305effdb00e032ca07e6d0e0d84cdf3dcf916 Gerrit-Change-Number: 29098 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/lowrisc: Remove the remains of a LowRISC soc
by Philipp Hug (Code Review) 18 Oct '18

18 Oct '18

Philipp Hug has posted comments on this change. ( https://review.coreboot.org/29165 ) Change subject: soc/lowrisc: Remove the remains of a LowRISC soc ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/29165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I03c5860b27d04b6e1d7868ba8ea7b52d1075aa6a Gerrit-Change-Number: 29165 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 18 Oct 2018 12:24:22 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/kahlee/variants/liara: enable 2T mode for liara.
by chris wang (Code Review) 18 Oct '18

18 Oct '18

chris wang has posted comments on this change. ( https://review.coreboot.org/29179 ) Change subject: mb/google/kahlee/variants/liara: enable 2T mode for liara. ...................................................................... Patch Set 2: Hi Martin, I revert the NB P-state disabling and use 2T mode instead. To enable 2T mode will help this not happened. It might be a workaround but can increase the power saving on liara. Do you have any suggestion ? -- To view, visit https://review.coreboot.org/29179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3a96276d88ffb70530d72b15c07b59a01cc6209a Gerrit-Change-Number: 29179 Gerrit-PatchSet: 2 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: chris wang <Chris.Wang(a)amd.com> Gerrit-Comment-Date: Thu, 18 Oct 2018 11:46:08 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit October 2018