coreboot-gerrit October 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: FSP headers for my fsp build
by Bora Guvendik (Code Review) 03 Oct '18

03 Oct '18

Bora Guvendik has abandoned this change. ( https://review.coreboot.org/23525 ) Change subject: FSP headers for my fsp build ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/23525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Ic2c7714124668361adbd8775ad9bf14d1eafa9f2 Gerrit-Change-Number: 23525 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Andrex Andraos <andrex.andraos(a)intel.corp-partner.google.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Wei-nan Liu <wei-nan.liu(a)intel.com>

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Change in coreboot[master]: [DO NOT MERGE] sd testing for cnl
by Bora Guvendik (Code Review) 03 Oct '18

03 Oct '18

Bora Guvendik has abandoned this change. ( https://review.coreboot.org/22573 ) Change subject: [DO NOT MERGE] sd testing for cnl ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/22573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I0da3ab7ad9210263bb7334bff266e302698a8c44 Gerrit-Change-Number: 22573 Gerrit-PatchSet: 2 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com>

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Change in coreboot[master]: GLK: SD card changes
by Bora Guvendik (Code Review) 03 Oct '18

03 Oct '18

Bora Guvendik has abandoned this change. ( https://review.coreboot.org/20195 ) Change subject: GLK: SD card changes ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/20195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Ife26dd5d8245a3cc617523eaa532946502d5165e Gerrit-Change-Number: 20195 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Andrex Andraos <andrex.andraos(a)intel.corp-partner.google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Hima B Chilmakuru <hima.b.chilmakuru(a)intel.com>

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Change in coreboot[master]: src/lib/edid.c: Replace #if 1 with something useful
by Julius Werner (Code Review) 03 Oct '18

03 Oct '18

Julius Werner has posted comments on this change. ( https://review.coreboot.org/28872 ) Change subject: src/lib/edid.c: Replace #if 1 with something useful ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28872/2/src/lib/edid.c File src/lib/edid.c: https://review.coreboot.org/#/c/28872/2/src/lib/edid.c@208 PS2, Line 208: if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8)) { Default log level isn't guaranteed to be the same as effective log level. What you want is if (console_log_level(BIOS_SPEW)) -- To view, visit https://review.coreboot.org/28872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I93dcab3db958480626fea6d99ab5289ebff04e8f Gerrit-Change-Number: 28872 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 02 Oct 2018 22:44:07 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: Change SlowSlewRate settings for L...
by Furquan Shaikh (Code Review) 03 Oct '18

03 Oct '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/28785 ) Change subject: mb/google/poppy/variants/nautilus: Change SlowSlewRate settings for LTE sku ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/28785/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28785/2//COMMIT_MSG@11 PS2, Line 11: Space not required. https://review.coreboot.org/#/c/28785/2//COMMIT_MSG@12 PS2, Line 12: abnormal reset This line seems to be longer than required? -- To view, visit https://review.coreboot.org/28785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7fa0041989113097e3b283dbcf4ca2a73629fe54 Gerrit-Change-Number: 28785 Gerrit-PatchSet: 2 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Oct 2018 22:00:32 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: cbfstool: Empty entry not followed by CBFS_COMPONENT_NULL
by Daisuke Nojiri (Code Review) 02 Oct '18

02 Oct '18

Daisuke Nojiri has uploaded this change for review. ( https://review.coreboot.org/28886 Change subject: cbfstool: Empty entry not followed by CBFS_COMPONENT_NULL ...................................................................... cbfstool: Empty entry not followed by CBFS_COMPONENT_NULL Currently, an entry is cleared only if the adjacent entry is also null or deleted. This patch ensures the entry to be removed is cleared regardless of the next entry type. Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> BUG=chromium:889716 BRANCH=none TEST=Run cbfstool bios.bin remove -n ecrw -vvv. Verify bios.bin has FF in the space of the removed entry. TEST=Run sign_official_build.sh on recovery_image.bin. Extract firmware contents from chromeos-firmwareupdate in the resigned image. Run 'futility vbutil_firmware --verify' for vblock_A's and FW_MAIN_A extracted from bios.bin. See the bug for details. Change-Id: I62540483da6cc35d0a604ec49b2f2b7b11ba9ce5 --- M util/cbfstool/cbfs_image.c 1 file changed, 15 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/28886/1 diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 306fc29..18b3b49 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -1611,7 +1611,7 @@ { struct cbfs_file *next; uint8_t *name; - uint32_t type, addr, last_addr; + uint32_t type, addr, next_addr; type = ntohl(entry->type); if (type == CBFS_COMPONENT_DELETED) { @@ -1625,32 +1625,21 @@ if (type != CBFS_COMPONENT_NULL) return 0; - next = cbfs_find_next_entry(image, entry); - - while (next && cbfs_is_valid_entry(image, next)) { - type = ntohl(next->type); - if (type == CBFS_COMPONENT_DELETED) { - type = CBFS_COMPONENT_NULL; - next->type = htonl(type); - } - if (type != CBFS_COMPONENT_NULL) - return 0; - - addr = cbfs_get_entry_addr(image, entry); - last_addr = cbfs_get_entry_addr( - image, cbfs_find_next_entry(image, next)); - - // Now, we find two deleted/empty entries; try to merge now. - DEBUG("join_empty_entry: combine 0x%x+0x%x and 0x%x+0x%x.\n", - cbfs_get_entry_addr(image, entry), ntohl(entry->len), - cbfs_get_entry_addr(image, next), ntohl(next->len)); - cbfs_create_empty_entry(entry, CBFS_COMPONENT_NULL, - (last_addr - addr - - cbfs_calculate_file_header_size("")), - ""); - DEBUG("new empty entry: length=0x%x\n", ntohl(entry->len)); - next = cbfs_find_next_entry(image, entry); + /* Loop until non-null entry is found, starting from current entry. + * After loop, next_addr should point to the adjacent non-null entry. */ + next = entry; + while (next->type == CBFS_COMPONENT_DELETED || + next->type == CBFS_COMPONENT_NULL) { + next = cbfs_find_next_entry(image, next); + next_addr = cbfs_get_entry_addr(image, next); + if (!next || !cbfs_is_valid_entry(image, next)) + break; } + + /* New we're creating one null entry for the combined empty spaces */ + addr = cbfs_get_entry_addr(image, entry); + cbfs_create_empty_entry(entry, CBFS_COMPONENT_NULL, + (next_addr - addr - cbfs_calculate_file_header_size("")), ""); return 0; } -- To view, visit https://review.coreboot.org/28886 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I62540483da6cc35d0a604ec49b2f2b7b11ba9ce5 Gerrit-Change-Number: 28886 Gerrit-PatchSet: 1 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org>

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Change in coreboot[master]: soc/amd/stoneyridge: Add IOMMU support
by Marc Jones (Code Review) 02 Oct '18

02 Oct '18

Hello Marshall Dawson, build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/28753 to look at the new patch set (#2). Change subject: soc/amd/stoneyridge: Add IOMMU support ...................................................................... soc/amd/stoneyridge: Add IOMMU support Enable the IOMMU in AGESA and copy the AGESA generated IVRS ACPI table. BUG=b:116196614 TEST=Check dmesg for AMD-Vi messages. Change-Id: I688d867c7bd4949a57b27c1b6a793c6a6e4a717a Signed-off-by: Marc Jones <marc.jones(a)scarletltd.com> --- M src/include/device/pci_ids.h M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/stoneyridge/Makefile.inc A src/soc/amd/stoneyridge/iommu.c M src/soc/amd/stoneyridge/northbridge.c 5 files changed, 61 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/28753/2 -- To view, visit https://review.coreboot.org/28753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I688d867c7bd4949a57b27c1b6a793c6a6e4a717a Gerrit-Change-Number: 28753 Gerrit-PatchSet: 2 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/amd/stoneyridge: Add IOMMU support
by Marc Jones (Code Review) 02 Oct '18

02 Oct '18

Marc Jones has posted comments on this change. ( https://review.coreboot.org/28753 ) Change subject: soc/amd/stoneyridge: Add IOMMU support ...................................................................... Patch Set 1: (2 comments) > Patch Set 1: > > (2 comments) https://review.coreboot.org/#/c/28753/1/src/soc/amd/stoneyridge/iommu.c File src/soc/amd/stoneyridge/iommu.c: https://review.coreboot.org/#/c/28753/1/src/soc/amd/stoneyridge/iommu.c@30 PS1, Line 30: 0x44 > Any reason this value was chosen? no, it is an arbitrary id for the resource. It is used by other iommu.c resource, so we should be consitent. *shrug* https://review.coreboot.org/#/c/28753/1/src/soc/amd/stoneyridge/iommu.c@38 PS1, Line 38: static void iommu_set_resources(struct device *dev) : { : pci_dev_set_resources(dev); : } > Get rid of this and call pci_dev_set_resources directly from the ops table? Done -- To view, visit https://review.coreboot.org/28753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I688d867c7bd4949a57b27c1b6a793c6a6e4a717a Gerrit-Change-Number: 28753 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Oct 2018 20:54:28 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: amd/stoneyridge: Use BIOS_DEBUG to log PM1 and PMxC0 status
by Raul Rangel (Code Review) 02 Oct '18

02 Oct '18

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/28885 ) Change subject: amd/stoneyridge: Use BIOS_DEBUG to log PM1 and PMxC0 status ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If7da8c7c86e90a661338903ad05cc41e11f507d2 Gerrit-Change-Number: 28885 Gerrit-PatchSet: 1 Gerrit-Owner: Edward Hill <ecgh(a)chromium.org> Gerrit-Reviewer: Edward Hill <ecgh(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Tue, 02 Oct 2018 20:29:29 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: amd/stoneyridge: Use BIOS_DEBUG to log PM1 and PMxC0 status
by Edward Hill (Code Review) 02 Oct '18

02 Oct '18

Edward Hill has uploaded this change for review. ( https://review.coreboot.org/28885 Change subject: amd/stoneyridge: Use BIOS_DEBUG to log PM1 and PMxC0 status ...................................................................... amd/stoneyridge: Use BIOS_DEBUG to log PM1 and PMxC0 status Use BIOS_DEBUG consistently to log PM1 and PMxC0 status registers on boot. print_num_status_bits() was already using BIOS_DEBUG. TEST=Inspect console for Grunt BUG=b:110788201 Change-Id: If7da8c7c86e90a661338903ad05cc41e11f507d2 Signed-off-by: Edward Hill <ecgh(a)chromium.org> --- M src/soc/amd/stoneyridge/southbridge.c 1 file changed, 6 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/28885/1 diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index b122f83..763ddd7 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -667,7 +667,7 @@ /* PMxC0 S5/Reset Status shows the source of previous reset. */ uint32_t pmxc0_status = pm_read32(PM_RST_STATUS); - static const char *const pmxc0_status_bits[] = { + static const char *const pmxc0_status_bits[32] = { [0] = "ThermalTrip", [1] = "FourSecondPwrBtn", [2] = "Shutdown", @@ -688,13 +688,12 @@ [27] = "SyncFlood", [28] = "HangReset", [29] = "EcWatchdogRst", - [31] = "BIT31", }; - printk(BIOS_SPEW, "PMxC0 STATUS: 0x%x ", pmxc0_status); + printk(BIOS_DEBUG, "PMxC0 STATUS: 0x%x ", pmxc0_status); print_num_status_bits(ARRAY_SIZE(pmxc0_status_bits), pmxc0_status, pmxc0_status_bits); - printk(BIOS_SPEW, "\n"); + printk(BIOS_DEBUG, "\n"); } /* After console init */ @@ -763,7 +762,7 @@ static uint16_t print_pm1_status(uint16_t pm1_sts) { - static const char *const pm1_sts_bits[] = { + static const char *const pm1_sts_bits[16] = { [0] = "TMROF", [4] = "BMSTATUS", [5] = "GBL", @@ -776,9 +775,9 @@ if (!pm1_sts) return 0; - printk(BIOS_SPEW, "PM1_STS: "); + printk(BIOS_DEBUG, "PM1_STS: "); print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits); - printk(BIOS_SPEW, "\n"); + printk(BIOS_DEBUG, "\n"); return pm1_sts; } -- To view, visit https://review.coreboot.org/28885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If7da8c7c86e90a661338903ad05cc41e11f507d2 Gerrit-Change-Number: 28885 Gerrit-PatchSet: 1 Gerrit-Owner: Edward Hill <ecgh(a)chromium.org>

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coreboot-gerrit October 2018