coreboot-gerrit October 2018

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Change in coreboot[master]: src/mb: Fix "CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8" if statement
by Nico Huber (Code Review) 02 Oct '18

02 Oct '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/28876 ) Change subject: src/mb: Fix "CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8" if statement ...................................................................... Patch Set 2: I have doubts this would compile at all. Please use a C `if` (no #if) and fix errors if they occur. Alternatively: Remove the dead code altogether. -- To view, visit https://review.coreboot.org/28876 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I318de3e7c807bb5b5efdf61fef387d34225a8149 Gerrit-Change-Number: 28876 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Oct 2018 16:09:39 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: libpayload/x86/exception: Add ability to ignore unknown interrupts
by Raul Rangel (Code Review) 02 Oct '18

02 Oct '18

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/28882 Change subject: libpayload/x86/exception: Add ability to ignore unknown interrupts ...................................................................... libpayload/x86/exception: Add ability to ignore unknown interrupts This will make enabling the APIC safer by ignoring unknown interrupts and not halting the system. Once all interrupt sources have been found and handled DIE_ON_UNKNOWN_INTERRUPT can be set if desired. BUG=b:116777191 TEST=Booted grunt, halted the kernel, and pushed the power button while in S5. Verified that depthcharge logged the unknown exception. APIC Init Started APIC Configured Ignoring interrupt vector 39 Change-Id: If4ed566ec284d69786c369f37e4e331d7f892c74 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M payloads/libpayload/arch/x86/Kconfig M payloads/libpayload/arch/x86/exception.c 2 files changed, 32 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/28882/1 diff --git a/payloads/libpayload/arch/x86/Kconfig b/payloads/libpayload/arch/x86/Kconfig index cbb21cb..129ff5f 100644 --- a/payloads/libpayload/arch/x86/Kconfig +++ b/payloads/libpayload/arch/x86/Kconfig @@ -37,4 +37,21 @@ config ENABLE_APIC bool "Enables the Local APIC" +choice + prompt "Interrupt Handling" + default LOG_UNKNOWN_INTERRUPTS if ENABLE_APIC + default DIE_ON_UNKNOWN_INTERRUPT + +config IGNORE_UNKNOWN_INTERRUPTS + bool "Ignore unknown user defined interrupts" + +config LOG_UNKNOWN_INTERRUPTS + bool "Logs unknown user defined interrupts to the console" + +config DIE_ON_UNKNOWN_INTERRUPT + bool "Die if an unknown user defined interrupt is encountered" + +endchoice + + endif diff --git a/payloads/libpayload/arch/x86/exception.c b/payloads/libpayload/arch/x86/exception.c index 1fa1304..983a9f3 100644 --- a/payloads/libpayload/arch/x86/exception.c +++ b/payloads/libpayload/arch/x86/exception.c @@ -171,9 +171,14 @@ if (handlers[vec]) { handlers[vec](vec); - if (IS_ENABLED(CONFIG_LP_ENABLE_APIC)) - apic_eoi(vec); - return; + goto success; + } else if (vec >= EXC_COUNT + && IS_ENABLED(CONFIG_LP_IGNORE_UNKNOWN_INTERRUPTS)) { + goto success; + } else if (vec >= EXC_COUNT + && IS_ENABLED(CONFIG_LP_LOG_UNKNOWN_INTERRUPTS)) { + printf("Ignoring interrupt vector %u\n", vec); + goto success; } die_if(vec >= EXC_COUNT || !names[vec], "Bad exception vector %u\n", @@ -181,7 +186,14 @@ dump_exception_state(); dump_stack(exception_state->regs.esp, 512); + /* We don't call apic_eoi because we don't want to ack the interrupt and + allow another interrupt to wake the processor. */ halt(); + return; + +success: + if (IS_ENABLED(CONFIG_LP_ENABLE_APIC)) + apic_eoi(vec); } void exception_init(void) -- To view, visit https://review.coreboot.org/28882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If4ed566ec284d69786c369f37e4e331d7f892c74 Gerrit-Change-Number: 28882 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>

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Change in coreboot[master]: libpayload/x86/exception.c: Remove exception_install_hook
by Raul Rangel (Code Review) 02 Oct '18

02 Oct '18

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/28881 Change subject: libpayload/x86/exception.c: Remove exception_install_hook ...................................................................... libpayload/x86/exception.c: Remove exception_install_hook Not used by x86 code anymore. BUG=b:116777191 TEST=Validated that depthcharge can be built. Change-Id: I25ad3903989a5433ce73d657cfdb93dd1f34f7b5 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M payloads/libpayload/arch/x86/exception.c 1 file changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/28881/1 diff --git a/payloads/libpayload/arch/x86/exception.c b/payloads/libpayload/arch/x86/exception.c index 3cd95bb..1fa1304 100644 --- a/payloads/libpayload/arch/x86/exception.c +++ b/payloads/libpayload/arch/x86/exception.c @@ -37,8 +37,6 @@ u32 exception_stack[0x400] __attribute__((aligned(8))); -static exception_hook hook; - static interrupt_handler handlers[256]; static const char *names[EXC_COUNT] = { @@ -181,9 +179,6 @@ die_if(vec >= EXC_COUNT || !names[vec], "Bad exception vector %u\n", vec); - if (hook && hook(vec)) - return; - dump_exception_state(); dump_stack(exception_state->regs.esp, 512); halt(); @@ -195,12 +190,6 @@ exception_init_asm(); } -void exception_install_hook(exception_hook h) -{ - die_if(hook, "Implement support for a list of hooks if you need it."); - hook = h; -} - void set_interrupt_handler(u8 vector, interrupt_handler handler) { handlers[vector] = handler; -- To view, visit https://review.coreboot.org/28881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I25ad3903989a5433ce73d657cfdb93dd1f34f7b5 Gerrit-Change-Number: 28881 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>

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Change in coreboot[master]: libpayload/apic: Register a spurious interrupt vector
by Raul Rangel (Code Review) 02 Oct '18

02 Oct '18

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/28880 Change subject: libpayload/apic: Register a spurious interrupt vector ...................................................................... libpayload/apic: Register a spurious interrupt vector We should have a spurious interrupt vector just incase we get one. The handler doesn't need to do anything. BUG=b:116777191 TEST=Booted depthcharge on grunt and inspected the register. I can't generate a spurious interrupt, so I can't validate that the handler gets called. Change-Id: I9e49e617f4375eb5eb00d0715c1902f77e2bf284 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M payloads/libpayload/arch/x86/apic.c 1 file changed, 21 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/28880/1 diff --git a/payloads/libpayload/arch/x86/apic.c b/payloads/libpayload/arch/x86/apic.c index 3b294cb..db81ea1 100644 --- a/payloads/libpayload/arch/x86/apic.c +++ b/payloads/libpayload/arch/x86/apic.c @@ -42,7 +42,6 @@ #define XAPIC_ENABLED_BIT (1 << 11) #define X2APIC_ENABLED_BIT (1 << 10) #define APIC_MASKED_BIT (1 << 16) -#define APIC_SW_ENABLED_BIT (1 << 8) #define APIC_ID 0x020 #define APIC_ID_SHIFT 24 @@ -54,6 +53,9 @@ #define APIC_TASK_PRIORITY_MASK 0xFFUL #define APIC_EOI 0x0B0 #define APIC_SPURIOUS 0x0F0 +#define APIC_SW_ENABLED_BIT (1 << 8) +#define APIC_SPURIOUS_VECTOR_MASK 0xFFUL +#define APIC_SPURIOUS 0x0F0 #define APIC_LVT_TIMER 0x320 #define APIC_TIMER_INIT_COUNT 0x380 #define APIC_TIMER_CUR_COUNT 0x390 @@ -63,7 +65,8 @@ #define APIC_LVT_SIZE 0x010 -#define APIC_TIMER_VECTOR 0x20 +#define APIC_TIMER_VECTOR 0x20UL +#define APIC_SPURIOUS_VECTOR 0xFFUL static uint32_t apic_bar; static int _apic_initialized; @@ -143,6 +146,8 @@ timer_waiting = 0; } +static void suprious_interrupt_handler(u8 vector) {} + void apic_eoi(uint8_t vector) { die_if(!apic_bar, "APIC is not initialized"); @@ -255,6 +260,17 @@ apic_write32(APIC_SPURIOUS, reg); } +static void apic_setup_spurious(void) +{ + uint32_t reg = apic_read32(APIC_SPURIOUS); + + reg &= ~APIC_SPURIOUS_VECTOR_MASK; + + reg |= APIC_SPURIOUS_VECTOR; + + apic_write32(APIC_SPURIOUS, reg); +} + void apic_init(void) { uint64_t apic_bar_reg; @@ -274,12 +290,15 @@ apic_reset_all_lvts(); apic_set_task_priority(0); + apic_setup_spurious(); apic_sw_enable(); apic_init_timer(); set_interrupt_handler(APIC_TIMER_VECTOR, &timer_interrupt_handler); + set_interrupt_handler(APIC_SPURIOUS_VECTOR, + &suprious_interrupt_handler); _apic_initialized = 1; -- To view, visit https://review.coreboot.org/28880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9e49e617f4375eb5eb00d0715c1902f77e2bf284 Gerrit-Change-Number: 28880 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>

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Change in coreboot[master]: libpayload/apic: Only ACK interrupts triggered by the APIC
by Raul Rangel (Code Review) 02 Oct '18

02 Oct '18

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/28879 Change subject: libpayload/apic: Only ACK interrupts triggered by the APIC ...................................................................... libpayload/apic: Only ACK interrupts triggered by the APIC Only set end of interrupt (EOI) when the APIC In-Service vector matches the interrupt vector. This makes it so we don't EOI a non APIC interrupt. BUG=b:116777191 TEST=Booted grunt with APIC enabled and verified depthcharge still works. Change-Id: I00bd1e7a0fcf2fc004feadc40d22ebfefe68b384 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M payloads/libpayload/arch/x86/apic.c M payloads/libpayload/arch/x86/exception.c M payloads/libpayload/include/x86/arch/apic.h 3 files changed, 27 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/28879/1 diff --git a/payloads/libpayload/arch/x86/apic.c b/payloads/libpayload/arch/x86/apic.c index 048cc66..3b294cb 100644 --- a/payloads/libpayload/arch/x86/apic.c +++ b/payloads/libpayload/arch/x86/apic.c @@ -58,6 +58,8 @@ #define APIC_TIMER_INIT_COUNT 0x380 #define APIC_TIMER_CUR_COUNT 0x390 #define APIC_TIMER_DIV_CFG 0x3E0 +#define APIC_ISR_0 0x100 +#define APIC_ISR_OFFSET 0x010 #define APIC_LVT_SIZE 0x010 @@ -141,11 +143,28 @@ timer_waiting = 0; } -void apic_eoi(void) +void apic_eoi(uint8_t vector) { die_if(!apic_bar, "APIC is not initialized"); - apic_write32(APIC_EOI, 0); + /* + * Local and I/O APICs support 240 vectors (in the range of 16 to 255) + * as valid interrupts. + */ + if (vector <= 15) + return; + + /* Each bank handles 32 vectors */ + uint8_t bank = vector / 32; + + uint32_t offset = APIC_ISR_0 + bank * APIC_ISR_OFFSET; + + uint32_t mask = apic_read32(offset); + + uint8_t shift = vector % 32; + + if (mask & (1 << shift)) + apic_write32(APIC_EOI, 0); } static enum APIC_CAPABILITY apic_capabilities(void) diff --git a/payloads/libpayload/arch/x86/exception.c b/payloads/libpayload/arch/x86/exception.c index 2691c85..3cd95bb 100644 --- a/payloads/libpayload/arch/x86/exception.c +++ b/payloads/libpayload/arch/x86/exception.c @@ -34,13 +34,6 @@ #include <arch/apic.h> #define IF_FLAG (1 << 9) -/* - * Local and I/O APICs support 240 vectors (in the range of 16 to 255) as valid - * interrupts. The Intel 64 and IA-32 architectures reserve vectors 16 - * through 31 for predefined interrupts, exceptions, and Intel-reserved - * encodings. -*/ -#define FIRST_USER_DEFINED_VECTOR 32 u32 exception_stack[0x400] __attribute__((aligned(8))); @@ -173,15 +166,15 @@ void exception_dispatch(void) { - u32 vec = exception_state->vector; + die_if(exception_state->vector >= ARRAY_SIZE(handlers), + "Invalid vector %u\n", exception_state->vector); - die_if(vec >= ARRAY_SIZE(handlers), "Invalid vector %u\n", vec); + u8 vec = exception_state->vector; if (handlers[vec]) { handlers[vec](vec); - if (IS_ENABLED(CONFIG_LP_ENABLE_APIC) - && vec >= FIRST_USER_DEFINED_VECTOR) - apic_eoi(); + if (IS_ENABLED(CONFIG_LP_ENABLE_APIC)) + apic_eoi(vec); return; } diff --git a/payloads/libpayload/include/x86/arch/apic.h b/payloads/libpayload/include/x86/arch/apic.h index c28fc0f..1eb3508 100644 --- a/payloads/libpayload/include/x86/arch/apic.h +++ b/payloads/libpayload/include/x86/arch/apic.h @@ -38,7 +38,7 @@ uint8_t apic_id(void); /** Signal the end of the interrupt handler. */ -void apic_eoi(void); +void apic_eoi(uint8_t vector); void apic_delay(unsigned int usec); -- To view, visit https://review.coreboot.org/28879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I00bd1e7a0fcf2fc004feadc40d22ebfefe68b384 Gerrit-Change-Number: 28879 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org>

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Change in coreboot[master]: src/nb/i945: Fix "CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8" if statement
by Elyes HAOUAS (Code Review) 02 Oct '18

02 Oct '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28878 Change subject: src/nb/i945: Fix "CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8" if statement ...................................................................... src/nb/i945: Fix "CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8" if statement 8 is the highest level. Change-Id: I1ff87c76b3aef4af93d88dd9c02a743656aacfc0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/early_init.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/28878/1 diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 7de2c73..f9906d7 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -952,7 +952,7 @@ i945_setup_root_complex_topology(); #if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 +#if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8)) #if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) sdram_dump_mchbar_registers(); -- To view, visit https://review.coreboot.org/28878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1ff87c76b3aef4af93d88dd9c02a743656aacfc0 Gerrit-Change-Number: 28878 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: amd/stoneyridge: Prepare for vboot rebooting system
by Marshall Dawson (Code Review) 02 Oct '18

02 Oct '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28877 Change subject: amd/stoneyridge: Prepare for vboot rebooting system ...................................................................... amd/stoneyridge: Prepare for vboot rebooting system Implement the function vboot_platform_prepare_reboot() which is normally a weak function. The SlpTyp field of the PM1 register is not reset to its default value when the APU restarts. This change prevents a failing condition if vboot decides to reset the system instead of allowing an S3 resume to continue. TEST=Resume Grunt when vboot attempts a reset, verify a fresh boot instead BUG=b:117089826 Change-Id: I6e0e3e541bad89ca5b23d6ddb6e5c0df7f762f10 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/pmutil.c 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/28877/1 diff --git a/src/soc/amd/stoneyridge/pmutil.c b/src/soc/amd/stoneyridge/pmutil.c index baabba5..2d603d0 100644 --- a/src/soc/amd/stoneyridge/pmutil.c +++ b/src/soc/amd/stoneyridge/pmutil.c @@ -32,3 +32,15 @@ return acpi_sleep_from_pm1(inw(pm_acpi_pm_cnt_blk())) == ACPI_S3; } + +/* If vboot requests a system reset, modify the PM1 register so it will never be + * misinterpreted as an S3 resume. */ +void vboot_platform_prepare_reboot(void) +{ + uint32_t pm1; + + pm1 = inw(pm_acpi_pm_cnt_blk()); + pm1 &= ~SLP_TYP; + pm1 |= SLP_TYP_S5 << SLP_TYP_SHIFT; + outw(pm1, pm_acpi_pm_cnt_blk()); +} -- To view, visit https://review.coreboot.org/28877 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6e0e3e541bad89ca5b23d6ddb6e5c0df7f762f10 Gerrit-Change-Number: 28877 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: src/mb: Fix "CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8" if statement
by Elyes HAOUAS (Code Review) 02 Oct '18

02 Oct '18

Elyes HAOUAS has posted comments on this change. ( https://review.coreboot.org/28876 ) Change subject: src/mb: Fix "CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8" if statement ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/28876 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I318de3e7c807bb5b5efdf61fef387d34225a8149 Gerrit-Change-Number: 28876 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Oct 2018 15:26:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: src/mb: Fix "CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8" if statement
by Elyes HAOUAS (Code Review) 02 Oct '18

02 Oct '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28876 Change subject: src/mb: Fix "CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8" if statement ...................................................................... src/mb: Fix "CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8" if statement 8 is highest level, so "CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8" will never happen Change-Id: I318de3e7c807bb5b5efdf61fef387d34225a8149 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/roda/rk886ex/romstage.c 11 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/28876/1 diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index ee322ae..769dcb8 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -269,7 +269,7 @@ /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 +if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8)) dump_spd_registers(); #endif diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index dacc396..ebace70 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -231,7 +231,7 @@ /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 +if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8)) dump_spd_registers(); #endif diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 7498247..5803347 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -281,7 +281,7 @@ /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 +if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8)) dump_spd_registers(); #endif diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index 49a25af..1777ed3 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -185,7 +185,7 @@ /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 +if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8)) dump_spd_registers(); #endif diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 78ec5ed..b49aa82 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -235,7 +235,7 @@ /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 +if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8)) dump_spd_registers(); #endif diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 57f32c2..0b67a0c 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -162,7 +162,7 @@ /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 +if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8)) dump_spd_registers(); #endif diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 467606a..f29ee43 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -331,7 +331,7 @@ /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 +if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8)) dump_spd_registers(); #endif diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index e4a8efb..50b8840 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -219,7 +219,7 @@ /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 +if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8)) dump_spd_registers(); #endif diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 81ee5da..c5a9198 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -221,7 +221,7 @@ /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 +if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8)) dump_spd_registers(); #endif diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 94c8a8f..97a9d76 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -219,7 +219,7 @@ /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 +if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8)) dump_spd_registers(); #endif diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 7f233e8..4279334 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -254,7 +254,7 @@ /* Enable SPD ROMs and DDR-II DRAM */ enable_smbus(); -#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 +if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8)) dump_spd_registers(); #endif -- To view, visit https://review.coreboot.org/28876 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I318de3e7c807bb5b5efdf61fef387d34225a8149 Gerrit-Change-Number: 28876 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: mb/emulation/spike-riscv: Implement mtime_init
by Jonathan Neuschäfer (Code Review) 02 Oct '18

02 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28873 to look at the new patch set (#2). Change subject: mb/emulation/spike-riscv: Implement mtime_init ...................................................................... mb/emulation/spike-riscv: Implement mtime_init This patch lets spike boot to "Payload not loaded" again. Because soc/ucb/riscv/ is does not represent a real SoC, but is a dummy directory for emulators, and different emulators might have different memory maps, I moved mtime_init to the mainboard-specific directories for Spike and QEMU. Change-Id: I080f7f81df752e25478bd277637bf894bbee4cb2 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/mainboard/emulation/qemu-riscv/Makefile.inc R src/mainboard/emulation/qemu-riscv/mtime.c M src/mainboard/emulation/spike-riscv/Makefile.inc A src/mainboard/emulation/spike-riscv/clint.c M src/soc/ucb/riscv/Makefile.inc 5 files changed, 30 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/28873/2 -- To view, visit https://review.coreboot.org/28873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I080f7f81df752e25478bd277637bf894bbee4cb2 Gerrit-Change-Number: 28873 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit October 2018