coreboot-gerrit October 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/poppy/variants/rammus: oem_table_id is too long to be recog...
by Marx Wang (Code Review) 02 Oct '18

02 Oct '18

Marx Wang has uploaded this change for review. ( https://review.coreboot.org/28870 Change subject: mb/google/poppy/variants/rammus: oem_table_id is too long to be recognized ...................................................................... mb/google/poppy/variants/rammus: oem_table_id is too long to be recognized This patch is to modify "the oem_table_id" from "RAMMUSMAX" to "RAMMUS" so that the topology firmware can be loaded properly. BUG=b:112945714 BRANCH=master TEST=There is no error message like "failed to load topology firmware" in kernel log. Change-Id: I66a38ea38791dd3d9606a05b7b696236c350237f Signed-off-by: Marx Wang <marx.wang(a)intel.com> --- M src/mainboard/google/poppy/variants/rammus/nhlt.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/28870/1 diff --git a/src/mainboard/google/poppy/variants/rammus/nhlt.c b/src/mainboard/google/poppy/variants/rammus/nhlt.c index 70c2524..efa08ee 100644 --- a/src/mainboard/google/poppy/variants/rammus/nhlt.c +++ b/src/mainboard/google/poppy/variants/rammus/nhlt.c @@ -38,6 +38,6 @@ uint32_t *oem_revision) { *oem_id = "GOOGLE"; - *oem_table_id = "RAMMUSMAX"; + *oem_table_id = "RAMMUS"; *oem_revision = 0; } -- To view, visit https://review.coreboot.org/28870 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I66a38ea38791dd3d9606a05b7b696236c350237f Gerrit-Change-Number: 28870 Gerrit-PatchSet: 1 Gerrit-Owner: Marx Wang <marx.wang(a)intel.com>

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Change in coreboot[master]: google/grunt: Update Audio/TP i2c timing
by Kevin Chiu (Code Review) 02 Oct '18

02 Oct '18

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/28868 Change subject: google/grunt: Update Audio/TP i2c timing ...................................................................... google/grunt: Update Audio/TP i2c timing After adjustment on Careena DVT Audio: 402.805 KHz -> 396.8 KHz TP: 406.1 KHz -> 399.5 KHz BUG=b:110984023 BRANCH=master TEST=emerge-grunt coreboot Change-Id: Ia3eb91ca3772d5f122498e3989ec03838fce06a5 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/kahlee/variants/careena/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/28868/1 diff --git a/src/mainboard/google/kahlee/variants/careena/devicetree.cb b/src/mainboard/google/kahlee/variants/careena/devicetree.cb index d633134..9769c42 100644 --- a/src/mainboard/google/kahlee/variants/careena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/careena/devicetree.cb @@ -27,7 +27,7 @@ # Enable I2C0 for audio, USB3 hub at 400kHz register "i2c[0]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 95, + .rise_time_ns = 58, .fall_time_ns = 3, }" @@ -42,8 +42,8 @@ # Enable I2C2 for trackpad, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 67, - .fall_time_ns = 55, + .rise_time_ns = 25, + .fall_time_ns = 11, }" # Enable I2C3 for touchscreen at 400kHz -- To view, visit https://review.coreboot.org/28868 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia3eb91ca3772d5f122498e3989ec03838fce06a5 Gerrit-Change-Number: 28868 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com>

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: set GPP_C19 to NF1
by Furquan Shaikh (Code Review) 02 Oct '18

02 Oct '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/28867 ) Change subject: mb/google/poppy/variant/nocturne: set GPP_C19 to NF1 ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28867/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28867/1//COMMIT_MSG@7 PS1, Line 7: set GPP_C19 to NF1 It might be better to just say that this CL is updating GPIO configuration since it is affecting more than GPP_C19. -- To view, visit https://review.coreboot.org/28867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9e972dbe4214cdd15d80d63dfa058e7755f7ecbb Gerrit-Change-Number: 28867 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Oct 2018 00:25:47 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: set GPP_C19 to NF1
by Furquan Shaikh (Code Review) 02 Oct '18

02 Oct '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/28867 ) Change subject: mb/google/poppy/variant/nocturne: set GPP_C19 to NF1 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9e972dbe4214cdd15d80d63dfa058e7755f7ecbb Gerrit-Change-Number: 28867 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 02 Oct 2018 00:22:43 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: set GPP_C19 to NF1
by Nick Vaccaro (Code Review) 02 Oct '18

02 Oct '18

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/28867 Change subject: mb/google/poppy/variant/nocturne: set GPP_C19 to NF1 ...................................................................... mb/google/poppy/variant/nocturne: set GPP_C19 to NF1 GPP_C19 was not being set as the code was incorrectly setting GPP_C16 instead, so this change sets C19 to NF1. Initialize GPP_E3 to a no connect. BUG=b:117124878 TEST: 'emerge-coreboot chromeos-bootimage', flash nocturne and verify that i2c transactions work for the left SAR sensor. Change-Id: I9e972dbe4214cdd15d80d63dfa058e7755f7ecbb Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/poppy/variants/nocturne/gpio.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/28867/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index 15a97c3..7724bc3 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -151,7 +151,7 @@ /* C18 : I2C1_SDA ==> PCH_I2C1_DISPLAY_SAR_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* C19 : I2C1_SCL ==> PCH_I2C1_DISPLAY_SAR_SCL */ - PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ @@ -217,6 +217,8 @@ /* E2 : SATAXPCIE2 ==> BT_DISABLE_L */ PAD_CFG_GPO(GPP_E2, 1, DEEP), /* E3 : CPU_GP0 ==> NC */ + PAD_CFG_NC(GPP_E3), + /* E3 : DEVSLP0 ==> NC */ PAD_CFG_NC(GPP_E4), /* E5 : SATA_DEVSLP1 ==> NC */ PAD_CFG_NC(GPP_E5), -- To view, visit https://review.coreboot.org/28867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9e972dbe4214cdd15d80d63dfa058e7755f7ecbb Gerrit-Change-Number: 28867 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com>

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: increase touchscreen reset delay
by Caveh Jalali (Code Review) 02 Oct '18

02 Oct '18

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/28803 ) Change subject: mb/google/poppy/variant/nocturne: increase touchscreen reset delay ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/28803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I102b57ea5a10d22bee6d4f7c6f114b380a5d586b Gerrit-Change-Number: 28803 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Oct 2018 00:12:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: increase touchscreen reset delay
by Furquan Shaikh (Code Review) 02 Oct '18

02 Oct '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/28803 ) Change subject: mb/google/poppy/variant/nocturne: increase touchscreen reset delay ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/28803 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I102b57ea5a10d22bee6d4f7c6f114b380a5d586b Gerrit-Change-Number: 28803 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 01 Oct 2018 23:28:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: amd/stoneyridge: Comment PCI and AcpiMmio registers in ASL
by Marshall Dawson (Code Review) 01 Oct '18

01 Oct '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28865 Change subject: amd/stoneyridge: Comment PCI and AcpiMmio registers in ASL ...................................................................... amd/stoneyridge: Comment PCI and AcpiMmio registers in ASL TEST=Build Grunt BUG=b:77602074 Change-Id: I24a46cc3e766ba7e9199723b042476064a698bf2 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl 1 file changed, 38 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/28865/1 diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index a639260..15e4d2f 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -188,6 +188,7 @@ OperationRegion(SMIC, SystemMemory, 0xfed80000, 0x80000) Field( SMIC, ByteAcc, NoLock, Preserve) { + /* MISC registers */ offset (0x03ee), U3PS, 2, /* Usb3PowerSel */ @@ -197,6 +198,7 @@ U2RP, 1, /* Usb2 Ref Clock Powerdown */ U3RP, 1, /* Usb3 Ref Clock Powerdown */ + /* XHCI_PM registers */ offset (0x1c00), , 1, ,6, @@ -217,70 +219,71 @@ offset (0x1c08), UA08, 32, - offset (0x1e4a), + /* AOAC Registers */ + offset (0x1e4a), /* I2C0 D3 Control */ I0TD, 2, , 1, I0PD, 1, - offset (0x1e4b), + offset (0x1e4b), /* I2C0 D3 State */ I0DS, 3, - offset (0x1e4c), + offset (0x1e4c), /* I2C1 D3 Control */ I1TD, 2, , 1, I1PD, 1, - offset (0x1e4d), + offset (0x1e4d), /* I2C1 D3 State */ I1DS, 3, - offset (0x1e4e), + offset (0x1e4e), /* I2C2 D3 Control */ I2TD, 2, , 1, I2PD, 1, - offset (0x1e4f), + offset (0x1e4f), /* I2C2 D3 State */ I2DS, 3, - offset (0x1e50), + offset (0x1e50), /* I2C3 D3 Control */ I3TD, 2, , 1, I3PD, 1, - offset (0x1e51), + offset (0x1e51), /* I2C3 D3 State */ I3DS, 3, - offset (0x1e56), + offset (0x1e56), /* UART0 D3 Control */ U0TD, 2, , 1, U0PD, 1, - offset (0x1e57), + offset (0x1e57), /* UART0 D3 State */ U0DS, 3, - offset (0x1e58), + offset (0x1e58), /* UART1 D3 Control */ U1TD, 2, , 1, U1PD, 1, - offset (0x1e59), + offset (0x1e59), /* UART1 D3 State */ U1DS, 3, - offset (0x1e5e), + offset (0x1e5e), /* SATA D3 Control */ SATD, 2, , 1, SAPD, 1, - offset (0x1e5f), + offset (0x1e5f), /* SATA D3 State */ SADS, 3, - offset (0x1e64), + offset (0x1e64), /* USB2 D3 Control */ U2TD, 2, , 1, U2PD, 1, - offset (0x1e65), + offset (0x1e65), /* USB2 D3 State */ U2DS, 3, - offset (0x1e6e), + offset (0x1e6e), /* USB3 D3 Control */ U3TD, 2, , 1, U3PD, 1, - offset (0x1e6f), + offset (0x1e6f), /* USB3 D3 State */ U3DS, 3, - offset (0x1e70), + offset (0x1e70), /* SD D3 Control */ SDTD, 2, , 1, , 1, @@ -288,10 +291,10 @@ SDRT, 1, SDSC, 1, - offset (0x1e71), + offset (0x1e71), /* SD D3 State */ SDDS, 3, - offset (0x1e80), + offset (0x1e80), /* Shadow Register Request */ , 15, RQ15, 1, , 2, @@ -301,7 +304,7 @@ RQ24, 1, , 5, RQTY, 1, - offset (0x1e84), + offset (0x1e84), /* Shadow Register Status */ , 15, SASR, 1, /* SATA 15 Shadow Reg Request Status Register */ , 2, @@ -310,13 +313,13 @@ U3SR, 1, /* USB3 23 Shadow Reg Request Status Register */ SDSR, 1, /* SD 24 Shadow Reg Request Status Register */ - offset (0x1ea0), + offset (0x1ea0), /* PwrGood Control */ PG1A, 1, PG2_, 1, ,1, U3PG, 1, /* Usb3 Power Good BIT3 */ - offset (0x1ea3), /* Power Good Control */ + offset (0x1ea3), /* PwrGood Control b[31:24] */ PGA3, 8 , } @@ -324,35 +327,35 @@ Field(FCFG, DwordAcc, NoLock, Preserve) { /* XHCI */ - Offset(0x00080010), + Offset(0x00080010), /* Base address */ XHBA, 32, - Offset(0x0008002c), + Offset(0x0008002c), /* Subsystem ID / Vendor ID */ XH2C, 32, - Offset(0x00080048), + Offset(0x00080048), /* Indirect PCI Index Register */ IDEX, 32, DATA, 32, - Offset(0x00080054), + Offset(0x00080054), /* PME Control / Status */ U_PS, 2, /* EHCI */ - Offset(0x00090004), + Offset(0x00090004), /* Control */ , 1, EHME, 1, - Offset(0x00090010), + Offset(0x00090010), /* Base address */ EHBA, 32, - Offset(0x0009002c), + Offset(0x0009002c), /* Subsystem ID / Vendor ID */ EH2C, 32, - Offset(0x00090054), + Offset(0x00090054), /* EHCI Spare 1 */ EH54, 8, - Offset(0x00090064), + Offset(0x00090064), /* Misc Control 2 */ EH64, 8, - Offset(0x000900c4), + Offset(0x000900c4), /* PME Control / Status */ E_PS, 2, /* LPC Bridge */ - Offset(0x000a30cb), + Offset(0x000a30cb), /* ClientRomProtect[31:24] */ , 7, AUSS, 1, /* AutoSizeStart */ } -- To view, visit https://review.coreboot.org/28865 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I24a46cc3e766ba7e9199723b042476064a698bf2 Gerrit-Change-Number: 28865 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Remove unused registers from ASL
by Marshall Dawson (Code Review) 01 Oct '18

01 Oct '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28864 Change subject: amd/stoneyridge: Remove unused registers from ASL ...................................................................... amd/stoneyridge: Remove unused registers from ASL Remove AcpiMmio and PCI config registers that are not used. TEST=build Grunt BUG=b:77602074 Change-Id: I62f40e421eba41c4a49d85efc975096171cb72fa Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl 1 file changed, 0 insertions(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/28864/1 diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 7ac9139..a639260 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -309,12 +309,6 @@ , 4, U3SR, 1, /* USB3 23 Shadow Reg Request Status Register */ SDSR, 1, /* SD 24 Shadow Reg Request Status Register */ - offset (0x1e88), - SRSA, 32, /* Shadow Reg SRAM Addr */ - SRSD, 32, /* Shadow Reg SRAM DATA */ - - offset (0x1e94), - SRDY, 1, /* S0i3 bios ready */ offset (0x1ea0), PG1A, 1, @@ -341,40 +335,6 @@ Offset(0x00080054), U_PS, 2, - /* SATA */ - Offset(0x00088010), - ST10, 32, - ST14, 32, - ST18, 32, - ST1C, 32, - ST20, 32, - ST24, 32, - - Offset(0x0008802c), - ST2C, 32, - - Offset(0x00088040), - ST40, 1, - - Offset(0x00088044), - ST44, 1, - - Offset(0x0008804c), - , 2, - DDIC, 1, /* DisableDynamicInterfaceClockPowerSaving */ - - Offset(0x00088064), - S_PS, 2, - - Offset(0x00088084), - , 1, - ST84, 1, - , 28, - DSDN, 1, /* DShutDowN */ - - Offset(0x0008808c), - ST8C, 8, - /* EHCI */ Offset(0x00090004), , 1, @@ -392,40 +352,9 @@ E_PS, 2, /* LPC Bridge */ - Offset(0x000a3078), - , 2, - LDQ0, 1, - Offset(0x000a30cb), , 7, AUSS, 1, /* AutoSizeStart */ - - /* SD */ - Offset(0x000a7004), - , 1, - SDME, 1, - - Offset(0x000a7010), - SDBA, 32, - Offset(0x000a702c), - SD2C, 32, - Offset(0x000a7094), - D_PS, 2, - , 6, - SDPE, 1, - , 6, - PMES, 1, - - Offset(0x000a70b3), /* Version 2.0 = 0x1, Version 3.0 = 0x2 */ - SDB3, 8, - Offset(0x000a70b4), /* Set Enable */ - , 8, - SETE, 1, - - Offset(0x000a70d0), - , 17, - FC18, 1, /* Force 1.8v */ - } /* -- To view, visit https://review.coreboot.org/28864 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I62f40e421eba41c4a49d85efc975096171cb72fa Gerrit-Change-Number: 28864 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Remove SATA D0 on suspend
by Marshall Dawson (Code Review) 01 Oct '18

01 Oct '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/28863 Change subject: amd/stoneyridge: Remove SATA D0 on suspend ...................................................................... amd/stoneyridge: Remove SATA D0 on suspend Remove the step of setting the SATA controller to S0 as the system is entering S3. This had been duplicated from AMD's FchCarrizo.asl file, but upon closer inspection, the conditions for this step to run cannot be met. This does not affect Grunt's behavior, as the SATA controller is disabled. TEST=Suspend and resume Grunt BUG=b:77602074 Change-Id: Ib269a5363d03c7048abd0c8a9a28df92a773790c Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/28863/1 diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 77c288b..7ac9139 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -592,10 +592,6 @@ if(LNotEqual(U2TD, 0x03)) { FDDC(18, 3) } - - if(LNotEqual(SATD, 0x00)) { - FDDC(15, 0) /* wake SATA before sleep */ - } } Method(FWAK,0, Serialized) /* FCH _WAK */ -- To view, visit https://review.coreboot.org/28863 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib269a5363d03c7048abd0c8a9a28df92a773790c Gerrit-Change-Number: 28863 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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coreboot-gerrit October 2018