coreboot-gerrit October 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: drivers/spi: Winbond specific write-protection enable
by build bot (Jenkins) (Code Review) 02 Oct '18

02 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25105 ) Change subject: drivers/spi: Winbond specific write-protection enable ...................................................................... Patch Set 25: (1 comment) https://review.coreboot.org/#/c/25105/25/src/drivers/spi/winbond.c File src/drivers/spi/winbond.c: https://review.coreboot.org/#/c/25105/25/src/drivers/spi/winbond.c@33 PS25, Line 33: #define CMD_VOLATILE_SREG_WREN 0x50 /* Write Enable for Volatile Status Register */ line over 80 characters -- To view, visit https://review.coreboot.org/25105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie3765b013855538eca37bc7800d3f9d5d09b8402 Gerrit-Change-Number: 25105 Gerrit-PatchSet: 25 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Tue, 02 Oct 2018 11:15:34 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: drivers/spi/winbond: Add function to lock flash's status register
by build bot (Jenkins) (Code Review) 02 Oct '18

02 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28697 ) Change subject: drivers/spi/winbond: Add function to lock flash's status register ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/#/c/28697/8/src/drivers/spi/winbond.c File src/drivers/spi/winbond.c: https://review.coreboot.org/#/c/28697/8/src/drivers/spi/winbond.c@565 PS8, Line 565: const enum spi_flash_status_reg_lockdown mode, code indent should use tabs where possible https://review.coreboot.org/#/c/28697/8/src/drivers/spi/winbond.c@566 PS8, Line 566: const bool non_volatile) code indent should use tabs where possible -- To view, visit https://review.coreboot.org/28697 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I90e0fcdcf531b53c0fc1ffcfdb3b5ab522f088f5 Gerrit-Change-Number: 28697 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Oct 2018 11:14:49 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/nvidia/tegra124: Increase bootblock size
by Patrick Rudolph (Code Review) 02 Oct '18

02 Oct '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/28875 Change subject: soc/nvidia/tegra124: Increase bootblock size ...................................................................... soc/nvidia/tegra124: Increase bootblock size Increase bootblock size by 4KiB and reduce romstage by 4 KiB. Change-Id: I604fd9c63a4cf6fb7b18249a6d73cd637e184a71 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/nvidia/tegra124/include/soc/memlayout.ld 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/28875/1 diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld index 6e596f3..615f0563 100644 --- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld @@ -31,9 +31,9 @@ PRERAM_CBFS_CACHE(0x40006000, 16K) VBOOT2_WORK(0x4000A000, 16K) STACK(0x4000E000, 8K) - BOOTBLOCK(0x40010000, 26K) - VERSTAGE(0x40016800, 72K) - ROMSTAGE(0x40028800, 93K) + BOOTBLOCK(0x40010000, 30K) + VERSTAGE(0x40017800, 72K) + ROMSTAGE(0x40029800, 89K) TIMESTAMP(0x4003FC00, 1K) SRAM_END(0x40040000) -- To view, visit https://review.coreboot.org/28875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I604fd9c63a4cf6fb7b18249a6d73cd637e184a71 Gerrit-Change-Number: 28875 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: src/lib/edid.c: Replace #if 1 with something useful
by Nico Huber (Code Review) 02 Oct '18

02 Oct '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/28872 ) Change subject: src/lib/edid.c: Replace #if 1 with something useful ...................................................................... Patch Set 1: (1 comment) A bit too much bikeshedding (this crappy EDID code usually doesn't deserve my attention) but ignoring what dark corner this is about: we can do better ;) https://review.coreboot.org/#/c/28872/1/src/lib/edid.c File src/lib/edid.c: https://review.coreboot.org/#/c/28872/1/src/lib/edid.c@207 PS1, Line 207: #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 `> 8` means BIOS_NEVER. Probably not the intention, writing `> BIOS_SPEW` would have made that obvious :-P Also I see no real benefit of an #if at all. It's ramstage code (we don't have to save every single byte in flash) and it doesn't have side effects (beside the potential log output). And, anyway, you could write it in C and it would still be dropped from the binary in case: if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8)) { -- To view, visit https://review.coreboot.org/28872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I93dcab3db958480626fea6d99ab5289ebff04e8f Gerrit-Change-Number: 28872 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Oct 2018 11:12:39 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: Documentation/mainboard: Add emulation/spike-riscv.md
by Jonathan Neuschäfer (Code Review) 02 Oct '18

02 Oct '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/28874 Change subject: Documentation/mainboard: Add emulation/spike-riscv.md ...................................................................... Documentation/mainboard: Add emulation/spike-riscv.md Move the usage instructions from their ad-hoc place in Kconfig.name to the Documentation directory, and expand them a bit. Change-Id: Id6c7bbca40a21ecba00cab736af2f2662a985106 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- A Documentation/mainboard/emulation/spike-riscv.md M Documentation/mainboard/index.md M src/mainboard/emulation/spike-riscv/Kconfig.name 3 files changed, 29 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/28874/1 diff --git a/Documentation/mainboard/emulation/spike-riscv.md b/Documentation/mainboard/emulation/spike-riscv.md new file mode 100644 index 0000000..55e87d9 --- /dev/null +++ b/Documentation/mainboard/emulation/spike-riscv.md @@ -0,0 +1,23 @@ +# Spike RISC-V emulator + +[Spike], also known as riscv-isa-sim, is a commonly used [RISC-V] emulator. + + +## Installation + +- Download `riscv-fesvr` and `riscv-isa-sim` from <https://github.com/riscv/> +- Apply the two patches in <https://github.com/riscv/riscv-isa-sim/pull/53>, + which are necessary in order to have a serial console +- Compile `riscv-fesvr` and then `riscv-isa-sim` + + +## Building coreboot and running it in Spike + +- Configure coreboot and run `make` as usual +- Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to + convert coreboot to an ELF that Spike can load +- Run `spike -m1024 build/coreboot.elf` + + +[Spike]: https://github.com/riscv/riscv-isa-sim +[RISC-V]: https://riscv.org/ diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index c346a3b..c1e5262 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -10,6 +10,12 @@ - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md) +## Emulation + +The boards in this section are not real mainboards, but emulators. + +- [Spike RISC-V emulator](emulation/spike-riscv.md) + ## Foxconn - [D41S](foxconn/d41s.md) diff --git a/src/mainboard/emulation/spike-riscv/Kconfig.name b/src/mainboard/emulation/spike-riscv/Kconfig.name index 2869425..36dd509 100644 --- a/src/mainboard/emulation/spike-riscv/Kconfig.name +++ b/src/mainboard/emulation/spike-riscv/Kconfig.name @@ -1,7 +1,2 @@ config BOARD_EMULATION_SPIKE_UCB_RISCV bool "SPIKE ucb riscv" - help - To run coreboot in spike: - * run "make" as usual - * util/riscv/make-spike-elf.sh build/coreboot.{rom,elf} - * spike -m1024 build/coreboot.elf -- To view, visit https://review.coreboot.org/28874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id6c7bbca40a21ecba00cab736af2f2662a985106 Gerrit-Change-Number: 28874 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: mb/emulation/spike-riscv: Implement mtime_init
by Jonathan Neuschäfer (Code Review) 02 Oct '18

02 Oct '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/28873 Change subject: mb/emulation/spike-riscv: Implement mtime_init ...................................................................... mb/emulation/spike-riscv: Implement mtime_init This patch lets spike boot to "Payload not loaded" again. Because soc/ucb/riscv/ is does not represent a real SoC, but is a dummy directory for emulators, and different emulators might have different memory maps, I moved mtime_init to mb/emulation/spike-riscv. Change-Id: I080f7f81df752e25478bd277637bf894bbee4cb2 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/mainboard/emulation/spike-riscv/Makefile.inc R src/mainboard/emulation/spike-riscv/clint.c M src/soc/ucb/riscv/Makefile.inc 3 files changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/28873/1 diff --git a/src/mainboard/emulation/spike-riscv/Makefile.inc b/src/mainboard/emulation/spike-riscv/Makefile.inc index 36f1fca..38977b6 100644 --- a/src/mainboard/emulation/spike-riscv/Makefile.inc +++ b/src/mainboard/emulation/spike-riscv/Makefile.inc @@ -14,11 +14,13 @@ bootblock-y += uart.c bootblock-y += rom_media.c +bootblock-y += clint.c romstage-y += romstage.c romstage-y += uart.c romstage-y += rom_media.c ramstage-y += uart.c ramstage-y += rom_media.c +ramstage-y += clint.c bootblock-y += memlayout.ld romstage-y += memlayout.ld diff --git a/src/soc/ucb/riscv/mtime.c b/src/mainboard/emulation/spike-riscv/clint.c similarity index 76% rename from src/soc/ucb/riscv/mtime.c rename to src/mainboard/emulation/spike-riscv/clint.c index f8c2717..7ad3f5a 100644 --- a/src/soc/ucb/riscv/mtime.c +++ b/src/mainboard/emulation/spike-riscv/clint.c @@ -15,8 +15,12 @@ #include <mcall.h> -/* FIXME: This is an empty implementation, please improve */ +#define SPIKE_CLINT_BASE 0x02000000 + /* This function is used to initialize HLS()->time/HLS()->timecmp */ void mtime_init(void) { + long hart_id = read_csr(mhartid); + HLS()->time = (uint64_t *)(SPIKE_CLINT_BASE + 0xbff8); + HLS()->timecmp = (uint64_t *)(SPIKE_CLINT_BASE + 0x4000 + 8 * hart_id); } diff --git a/src/soc/ucb/riscv/Makefile.inc b/src/soc/ucb/riscv/Makefile.inc index a10f3aa..1072a2b 100644 --- a/src/soc/ucb/riscv/Makefile.inc +++ b/src/soc/ucb/riscv/Makefile.inc @@ -1,8 +1,6 @@ ifeq ($(CONFIG_SOC_UCB_RISCV),y) -bootblock-y += mtime.c romstage-y += cbmem.c ramstage-y += cbmem.c -ramstage-y += mtime.c endif -- To view, visit https://review.coreboot.org/28873 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I080f7f81df752e25478bd277637bf894bbee4cb2 Gerrit-Change-Number: 28873 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: src/lib/edid.c: Replace #if 1 with something useful
by Jonathan Neuschäfer (Code Review) 02 Oct '18

02 Oct '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/28872 ) Change subject: src/lib/edid.c: Replace #if 1 with something useful ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/28872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I93dcab3db958480626fea6d99ab5289ebff04e8f Gerrit-Change-Number: 28872 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Oct 2018 10:22:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/lib/edid.c: Replace #if 1 with something useful
by Angel Pons (Code Review) 02 Oct '18

02 Oct '18

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/28872 Change subject: src/lib/edid.c: Replace #if 1 with something useful ...................................................................... src/lib/edid.c: Replace #if 1 with something useful Since `#if 1` is rather useless, and the code inside it is just several `printk(BIOS_SPEW)`, using `CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8` instead seems more reasonable. Change-Id: I93dcab3db958480626fea6d99ab5289ebff04e8f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/lib/edid.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/28872/1 diff --git a/src/lib/edid.c b/src/lib/edid.c index 9cf9b8a..28773a4 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -204,7 +204,7 @@ { struct edid *out = &tmp_edid; int i; -#if 1 +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 printk(BIOS_SPEW, "Hex of detail: "); for (i = 0; i < 18; i++) printk(BIOS_SPEW, "%02x", x[i]); -- To view, visit https://review.coreboot.org/28872 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I93dcab3db958480626fea6d99ab5289ebff04e8f Gerrit-Change-Number: 28872 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: Change SlowSlewRate settings for L...
by Seunghwan Kim (Code Review) 02 Oct '18

02 Oct '18

Seunghwan Kim has posted comments on this change. ( https://review.coreboot.org/28785 ) Change subject: mb/google/poppy/variants/nautilus: Change SlowSlewRate settings for LTE sku ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/28785 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7fa0041989113097e3b283dbcf4ca2a73629fe54 Gerrit-Change-Number: 28785 Gerrit-PatchSet: 2 Gerrit-Owner: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-Comment-Date: Tue, 02 Oct 2018 08:30:48 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: src: Fix MSR_PKG_CST_CONFIG_CONTROL register name
by Elyes HAOUAS (Code Review) 02 Oct '18

02 Oct '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28871 Change subject: src: Fix MSR_PKG_CST_CONFIG_CONTROL register name ...................................................................... src: Fix MSR_PKG_CST_CONFIG_CONTROL register name Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/fsp_model_206ax/finalize.c M src/cpu/intel/fsp_model_206ax/model_206ax.h M src/cpu/intel/fsp_model_406dx/model_406dx.h M src/cpu/intel/haswell/finalize.c M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_106cx/model_106cx_init.c M src/cpu/intel/model_2065x/finalize.c M src/cpu/intel/model_206ax/finalize.c M src/cpu/intel/model_206ax/model_206ax_init.c M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_6fx/model_6fx_init.c M src/include/cpu/intel/speedstep.h M src/soc/intel/apollolake/cpu.c M src/soc/intel/baytrail/cpu.c M src/soc/intel/baytrail/include/soc/msr.h M src/soc/intel/braswell/cpu.c M src/soc/intel/braswell/include/soc/msr.h M src/soc/intel/broadwell/cpu.c M src/soc/intel/broadwell/include/soc/msr.h M src/soc/intel/common/block/include/intelblocks/msr.h M src/soc/intel/denverton_ns/include/soc/msr.h M src/soc/intel/fsp_baytrail/cpu.c M src/soc/intel/fsp_baytrail/include/soc/msr.h 25 files changed, 38 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/28871/1 diff --git a/src/cpu/intel/fsp_model_206ax/finalize.c b/src/cpu/intel/fsp_model_206ax/finalize.c index 2d5973b..d143497 100644 --- a/src/cpu/intel/fsp_model_206ax/finalize.c +++ b/src/cpu/intel/fsp_model_206ax/finalize.c @@ -45,7 +45,7 @@ void intel_model_206ax_finalize_smm(void) { /* Lock C-State MSR */ - msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); + msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ if (cpuid_ecx(1) & (1 << 25)) diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h index e65b370..1af54df 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax.h +++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h @@ -43,7 +43,7 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_MISC_PWR_MGMT 0x1aa diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h index 87daeac..c40b597 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h @@ -45,7 +45,7 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_MISC_PWR_MGMT 0x1aa diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c index ce22e62..b170215 100644 --- a/src/cpu/intel/haswell/finalize.c +++ b/src/cpu/intel/haswell/finalize.c @@ -48,7 +48,7 @@ { #if 0 /* Lock C-State MSR */ - msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); + msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ if (cpuid_ecx(1) & (1 << 25)) diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 8498c1a..8e59ccb 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -58,7 +58,7 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_MISC_PWR_MGMT 0x1aa diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 24de43e..bba1410 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -486,7 +486,7 @@ { msr_t msr; - msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); msr.lo |= (1 << 30); // Package c-state Undemotion Enable msr.lo |= (1 << 29); // Package c-state Demotion Enable msr.lo |= (1 << 28); // C1 Auto Undemotion Enable @@ -495,7 +495,7 @@ msr.lo |= (1 << 25); // C3 Auto Demotion Enable msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection /* The deepest package c-state defaults to factory-configured value. */ - wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE); msr.lo &= ~0xffff; diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 0d9169b..f304b94 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -63,7 +63,7 @@ const int cst_range = (c6 ? 6 : (c5 ? 5 : 4)) - 2; /* zero means lvl2 */ - msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk msr.lo |= (1 << 8); if (quad) @@ -79,7 +79,7 @@ msr.lo |= (1 << 10); /* Enable IO MWAIT redirection. */ if (c6) msr.lo |= (1 << 25); - wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE */ msr.hi = 0; @@ -129,10 +129,10 @@ wrmsr(IA32_PERF_CTL, msr); } - msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); msr.lo &= ~(1 << 11); /* Enable hw coordination. */ msr.lo |= (1 << 15); /* Lock config until next reset. */ - wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); } #define MSR_EMTTM_CR_TABLE(x) (0xa8 + (x)) diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index dd7bbc8..780575a 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -32,14 +32,14 @@ { msr_t msr; - msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); msr.lo |= (1 << 15); // Lock configuration msr.lo |= (1 << 10); // redirect IO-based CState transition requests to // MWAIT msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 // TODO Do we want Deep C4 and Dynamic L2 shrinking? - wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE (P_BLK) */ msr.hi = 0; diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index 8425f6a..08541c0 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -46,7 +46,7 @@ void intel_model_2065x_finalize_smm(void) { /* Lock C-State MSR */ - msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); + msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ if (cpuid_ecx(1) & (1 << 25)) diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 7d3cc2e..5c69ffc 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -46,7 +46,7 @@ void intel_model_206ax_finalize_smm(void) { /* Lock C-State MSR */ - msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); + msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ if (cpuid_ecx(1) & (1 << 25)) diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 3cc8d82..ece8971 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -252,14 +252,14 @@ { msr_t msr; - msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); msr.lo |= (1 << 28); // C1 Auto Undemotion Enable msr.lo |= (1 << 27); // C3 Auto Undemotion Enable msr.lo |= (1 << 26); // C1 Auto Demotion Enable msr.lo |= (1 << 25); // C3 Auto Demotion Enable msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection msr.lo |= 7; // No package C-state limit - wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); msr = rdmsr(MSR_PMG_IO_CAPTURE_ADDR); msr.lo &= ~0x7ffff; diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 96830c4..68be567 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -33,7 +33,7 @@ { msr_t msr; - msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); msr.lo |= (1 << 15); // config lock until next reset msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk @@ -43,7 +43,7 @@ msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 - wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE (P_BLK) */ msr.hi = 0; diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index a1433f6..642201c 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -33,7 +33,7 @@ { msr_t msr; - msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); msr.lo |= (1 << 15); // config lock until next reset msr.lo |= (1 << 14); // Deeper Sleep msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States @@ -44,7 +44,7 @@ msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3 - wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); /* Set Processor MWAIT IO BASE (P_BLK) */ msr.hi = 0; diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 4b556b7..5390781 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -43,7 +43,7 @@ #define MSR_EBC_FREQUENCY_ID 0x2c #define MSR_FSB_FREQ 0xcd #define MSR_FSB_CLOCK_VCC 0xce -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_BASE_ADDR 0xe3 #define MSR_PMG_IO_CAPTURE_ADDR 0xe4 #define MSR_EXTENDED_CONFIG 0xee diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index caa3bbf..e745996 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -47,7 +47,7 @@ static const struct reg_script core_msr_script[] = { #if !IS_ENABLED(CONFIG_SOC_INTEL_GLK) /* Enable C-state and IO/MWAIT redirect */ - REG_MSR_WRITE(MSR_PMG_CST_CONFIG_CONTROL, + REG_MSR_WRITE(MSR_PKG_CST_CONFIG_CONTROL, (PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK | IO_MWAIT_REDIRECT_MASK | CST_CFG_LOCK_MASK)), /* Power Management I/O base address for I/O trapping to C-states */ diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 618430b..9bbeafb 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -35,7 +35,7 @@ /* Core level MSRs */ const struct reg_script core_msr_script[] = { /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ - REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), + REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), REG_MSR_RMW(MSR_POWER_MISC, ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0), /* Disable C1E */ diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h index 689d4d5..b332478 100644 --- a/src/soc/intel/baytrail/include/soc/msr.h +++ b/src/soc/intel/baytrail/include/soc/msr.h @@ -19,7 +19,7 @@ #define MSR_IA32_PLATFORM_ID 0x17 #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define SINGLE_PCTL (1 << 11) #define MSR_POWER_MISC 0x120 #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 85b04ac..6ed12af 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -36,7 +36,7 @@ /* Core level MSRs */ static const struct reg_script core_msr_script[] = { /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ - REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), + REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008), REG_MSR_RMW(MSR_POWER_MISC, ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0), /* Disable C1E */ diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h index 47e9bcd..1a79b2f 100644 --- a/src/soc/intel/braswell/include/soc/msr.h +++ b/src/soc/intel/braswell/include/soc/msr.h @@ -21,7 +21,7 @@ #define MSR_IA32_BIOS_SIGN_ID 0x8B #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define SINGLE_PCTL (1 << 11) #define MSR_POWER_MISC 0x120 #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index ee1fd52..3ef0d72 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -394,7 +394,7 @@ { msr_t msr; - msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); msr.lo |= (1 << 31); // Timed MWAIT Enable msr.lo |= (1 << 30); // Package c-state Undemotion Enable msr.lo |= (1 << 29); // Package c-state Demotion Enable @@ -404,7 +404,7 @@ msr.lo |= (1 << 25); // C3 Auto Demotion Enable msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection /* The deepest package c-state defaults to factory-configured value. */ - wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); + wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr); msr = rdmsr(MSR_MISC_PWR_MGMT); msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index 41ce17c..c2a939e 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -23,7 +23,7 @@ #define CPUID_SMX (1 << 6) #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_FEATURE_CONFIG 0x13c #define SMM_MCA_CAP_MSR 0x17d diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index e1fc431..154f03b 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -25,14 +25,14 @@ #define SGX_GLOBAL_ENABLE (1 << 18) #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PLATFORM_INFO 0xce -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 -/* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 +/* Set MSR_PKG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ #define PKG_C_STATE_LIMIT_C2_MASK 0x2 -/* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/ +/* Set MSR_PKG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/ #define CORE_C_STATE_LIMIT_C10_MASK 0x70 -/* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */ +/* Set MSR_PKG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */ #define IO_MWAIT_REDIRECT_MASK 0x400 -/* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */ +/* Set MSR_PKG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */ #define CST_CFG_LOCK_MASK 0x8000 #define MSR_BIOS_UPGD_TRIG 0x7a #define SGX_ACTIVATE_BIT (1) diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 4d1ac70..a2a42f1 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -26,7 +26,7 @@ #define CPUID_SMX (1 << 6) #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 #define MSR_FEATURE_CONFIG 0x13c #define SMM_MCA_CAP_MSR 0x17d diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index a69d046..89ea4c2 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -35,7 +35,7 @@ /* Core level MSRs */ static const struct reg_script core_msr_script[] = { /* Dynamic L2 shrink enable and threshold */ - REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008), + REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008), /* Disable C1E */ REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), REG_MSR_OR(MSR_POWER_MISC, 0x44), diff --git a/src/soc/intel/fsp_baytrail/include/soc/msr.h b/src/soc/intel/fsp_baytrail/include/soc/msr.h index ea1d790..4435256 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/msr.h +++ b/src/soc/intel/fsp_baytrail/include/soc/msr.h @@ -19,7 +19,7 @@ #define MSR_IA32_PLATFORM_ID 0x17 #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce -#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_PKG_CST_CONFIG_CONTROL 0xe2 #define MSR_POWER_MISC 0x120 #define MSR_IA32_PERF_CTL 0x199 #define MSR_IA32_MISC_ENABLES 0x1a0 -- To view, visit https://review.coreboot.org/28871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f Gerrit-Change-Number: 28871 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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coreboot-gerrit October 2018