coreboot-gerrit October 2018

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Change in coreboot[master]: soc/amd/stoneyridge: Allow mainboard to update I2C at runtime
by build bot (Jenkins) (Code Review) 03 Oct '18

03 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28904 ) Change subject: soc/amd/stoneyridge: Allow mainboard to update I2C at runtime ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28904/2/src/soc/amd/stoneyridge/i2c.c File src/soc/amd/stoneyridge/i2c.c: https://review.coreboot.org/#/c/28904/2/src/soc/amd/stoneyridge/i2c.c@59 PS2, Line 59: void __weak mb_update_i2c(unsigned int bus, const struct dw_i2c_bus_config **i2c_vals) {} line over 80 characters -- To view, visit https://review.coreboot.org/28904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id00c352a04b3d7845027882bcfcee09518787067 Gerrit-Change-Number: 28904 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Comment-Date: Wed, 03 Oct 2018 19:04:00 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/kahlee: Update I2c values for older careena boards
by Martin Roth (Code Review) 03 Oct '18

03 Oct '18

Hello build bot (Jenkins), Kevin Chiu, Raul Rangel, Daniel Kurtz, I'd like you to reexamine a change. Please visit https://review.coreboot.org/28905 to look at the new patch set (#2). Change subject: mb/google/kahlee: Update I2c values for older careena boards ...................................................................... mb/google/kahlee: Update I2c values for older careena boards The I2C values are typically set in devicetree.cb, but there's an issue where the values need to change between board versions. This allows the mainboard to update the settings at runtime. BUG=B:110984023 TEST=I2C is set correctly on each version. Change-Id: I1d17c502244c43e9a8f89471f7b04b3467a6e486 Signed-off-by: Martin Roth <martinroth(a)chromium.org> --- M src/mainboard/google/kahlee/variants/careena/Makefile.inc A src/mainboard/google/kahlee/variants/careena/i2c.c 2 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/28905/2 -- To view, visit https://review.coreboot.org/28905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I1d17c502244c43e9a8f89471f7b04b3467a6e486 Gerrit-Change-Number: 28905 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/kahlee: Set 100MHz fast spi read for supported boards
by Raul Rangel (Code Review) 03 Oct '18

03 Oct '18

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/28906 ) Change subject: mb/google/kahlee: Set 100MHz fast spi read for supported boards ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9ad95c858376ad0e6c9e787055d3fa72b5682191 Gerrit-Change-Number: 28906 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Wed, 03 Oct 2018 18:47:02 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge: Allow mainboard to update I2C at runtime
by Raul Rangel (Code Review) 03 Oct '18

03 Oct '18

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/28904 ) Change subject: soc/amd/stoneyridge: Allow mainboard to update I2C at runtime ...................................................................... Patch Set 1: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/28904/1/src/soc/amd/stoneyridge/include/soc… File src/soc/amd/stoneyridge/include/soc/southbridge.h: https://review.coreboot.org/#/c/28904/1/src/soc/amd/stoneyridge/include/soc… PS1, Line 562: pointer pointer to the pointer of the i2c value structure. Or can i2c_vals be made a single pointer instead of double? -- To view, visit https://review.coreboot.org/28904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id00c352a04b3d7845027882bcfcee09518787067 Gerrit-Change-Number: 28904 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 03 Oct 2018 18:45:53 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/kahlee: Update I2c values for older careena boards
by Raul Rangel (Code Review) 03 Oct '18

03 Oct '18

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/28905 ) Change subject: mb/google/kahlee: Update I2c values for older careena boards ...................................................................... Patch Set 1: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/28905/1/src/mainboard/google/kahlee/variant… File src/mainboard/google/kahlee/variants/careena/i2c.c: https://review.coreboot.org/#/c/28905/1/src/mainboard/google/kahlee/variant… PS1, Line 42: Ah, I see you are just replacing the whole struct instead of updating each value. -- To view, visit https://review.coreboot.org/28905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1d17c502244c43e9a8f89471f7b04b3467a6e486 Gerrit-Change-Number: 28905 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 03 Oct 2018 18:45:48 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/kahlee: Set 100MHz fast spi read for supported boards
by Martin Roth (Code Review) 03 Oct '18

03 Oct '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/28906 Change subject: mb/google/kahlee: Set 100MHz fast spi read for supported boards ...................................................................... mb/google/kahlee: Set 100MHz fast spi read for supported boards BUG=b:116737547 TEST=Boot Careena, look at signal on a scope. Change-Id: I9ad95c858376ad0e6c9e787055d3fa72b5682191 Signed-off-by: Martin Roth <martinroth(a)chromium.org> --- M src/mainboard/google/kahlee/bootblock/bootblock.c 1 file changed, 31 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/28906/1 diff --git a/src/mainboard/google/kahlee/bootblock/bootblock.c b/src/mainboard/google/kahlee/bootblock/bootblock.c index 8531fc0..40fd390 100644 --- a/src/mainboard/google/kahlee/bootblock/bootblock.c +++ b/src/mainboard/google/kahlee/bootblock/bootblock.c @@ -14,6 +14,7 @@ */ #include <baseboard/variants.h> +#include <boardid.h> #include <bootblock_common.h> #include <soc/gpio.h> #include <soc/southbridge.h> @@ -32,34 +33,49 @@ sb_program_gpios(gpios, num_gpios); } +/* Use 100MHz on on boards that can support it */ +static int set_100mhz_fast_read(void) +{ + uint32_t id = board_id(); + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CAREENA) && (id <= 2 || id >= 5)) + return 1; + + return 0; +} + void bootblock_mainboard_init(void) { + uint16_t normal = SPI_SPEED_33M; + uint16_t fast = SPI_SPEED_66M; + uint16_t altio = SPI_SPEED_66M; + + /* + * W25Q128FW Setup + * Normal Read 40MHz + * Fast Read 104MHz + * Dual Read IO (1-2-2) + */ + if (IS_ENABLED(CONFIG_EM100)) { /* * We should be able to rely on defaults, but it seems safer * to explicitly set up these registers. */ sb_read_mode(SPI_READ_MODE_NOM); - sb_set_spi100(SPI_SPEED_16M, /* Normal */ - SPI_SPEED_16M, /* Fast */ - SPI_SPEED_16M, /* AltIO */ - SPI_SPEED_66M); /* TPM */ + + normal = SPI_SPEED_16M; + fast = SPI_SPEED_16M; + altio = SPI_SPEED_16M; } else { - /* - * W25Q128FW Setup - * Normal Read 40MHz - * Fast Read 104MHz - * Dual Read IO (1-2-2) - */ sb_read_mode(SPI_READ_MODE_DUAL122); - /* Set SPI speeds before verstage. Needed for TPM */ - sb_set_spi100(SPI_SPEED_33M, /* Normal */ - SPI_SPEED_66M, /* Fast */ - SPI_SPEED_66M, /* AltIO */ - SPI_SPEED_66M); /* TPM */ + if (set_100mhz_fast_read()) + fast = SPI_SPEED_100M; } + /* Normal, Fast, AltIO, TPM */ + sb_set_spi100(normal, fast, altio, SPI_SPEED_66M); + /* Setup TPM decode before verstage */ sb_tpm_decode_spi(); } -- To view, visit https://review.coreboot.org/28906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9ad95c858376ad0e6c9e787055d3fa72b5682191 Gerrit-Change-Number: 28906 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Allow mainboard to update I2C at runtime
by build bot (Jenkins) (Code Review) 03 Oct '18

03 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28904 ) Change subject: soc/amd/stoneyridge: Allow mainboard to update I2C at runtime ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28904/1/src/soc/amd/stoneyridge/i2c.c File src/soc/amd/stoneyridge/i2c.c: https://review.coreboot.org/#/c/28904/1/src/soc/amd/stoneyridge/i2c.c@59 PS1, Line 59: void __weak mb_update_i2c(unsigned int bus, const struct dw_i2c_bus_config **i2c_vals) {} line over 80 characters -- To view, visit https://review.coreboot.org/28904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id00c352a04b3d7845027882bcfcee09518787067 Gerrit-Change-Number: 28904 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 03 Oct 2018 18:38:43 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/kahlee: Update I2c values for older careena boards
by Martin Roth (Code Review) 03 Oct '18

03 Oct '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/28905 Change subject: mb/google/kahlee: Update I2c values for older careena boards ...................................................................... mb/google/kahlee: Update I2c values for older careena boards The I2C values are typically set in devicetree.cb, but there's an issue where the values need to change between board versions. This allows the mainboard to update the settings at runtime. BUG=B:110984023 TEST=I2C is set correctly on each version. Change-Id: I1d17c502244c43e9a8f89471f7b04b3467a6e486 Signed-off-by: Martin Roth <martinroth(a)chromium.org> --- M src/mainboard/google/kahlee/variants/careena/Makefile.inc A src/mainboard/google/kahlee/variants/careena/i2c.c 2 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/28905/1 diff --git a/src/mainboard/google/kahlee/variants/careena/Makefile.inc b/src/mainboard/google/kahlee/variants/careena/Makefile.inc index 0579e18..559b70d 100644 --- a/src/mainboard/google/kahlee/variants/careena/Makefile.inc +++ b/src/mainboard/google/kahlee/variants/careena/Makefile.inc @@ -15,6 +15,9 @@ subdirs-y += ../baseboard/spd +bootblock-y += i2c.c + romstage-y += ../baseboard/romstage.c ramstage-y += ../baseboard/mainboard.c +ramstage-y += i2c.c diff --git a/src/mainboard/google/kahlee/variants/careena/i2c.c b/src/mainboard/google/kahlee/variants/careena/i2c.c new file mode 100644 index 0000000..2c06fc1 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/careena/i2c.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <ec/google/chromeec/ec.h> +#include <soc/southbridge.h> + +/* I2C0 for audio, USB3 hub at 400kHz */ +struct dw_i2c_bus_config careena4_i2c_0 = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 95, + .fall_time_ns = 3, +}; + +/* I2C2 for trackpad */ +struct dw_i2c_bus_config careena4_i2c_2 = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 67, + .fall_time_ns = 55, +}; + +/* Change timings for older revisions of the board */ +void mb_update_i2c(unsigned int bus, const struct dw_i2c_bus_config **i2c_vals) +{ + uint32_t board_id = board_id(); + + if (board_id > 2 && board_id < 5) { + switch (bus) { + case 0: + *i2c_vals = &careena4_i2c_0; + break; + case 2: + *i2c_vals = &careena4_i2c_2; + break; + } + } +} -- To view, visit https://review.coreboot.org/28905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1d17c502244c43e9a8f89471f7b04b3467a6e486 Gerrit-Change-Number: 28905 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Allow mainboard to update I2C at runtime
by Martin Roth (Code Review) 03 Oct '18

03 Oct '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/28904 Change subject: soc/amd/stoneyridge: Allow mainboard to update I2C at runtime ...................................................................... soc/amd/stoneyridge: Allow mainboard to update I2C at runtime The I2C values are typically set in devicetree.cb, but there's an issue where the values need to change between board versions. This allows the mainboard to update the settings at runtime. BUG=B:110984023 TEST= See that I2C is set correctly on each version. Change-Id: Id00c352a04b3d7845027882bcfcee09518787067 Signed-off-by: Martin Roth <martinroth(a)chromium.org> --- M src/soc/amd/stoneyridge/i2c.c M src/soc/amd/stoneyridge/include/soc/southbridge.h 2 files changed, 17 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/28904/1 diff --git a/src/soc/amd/stoneyridge/i2c.c b/src/soc/amd/stoneyridge/i2c.c index b90e5d7..beac139 100644 --- a/src/soc/amd/stoneyridge/i2c.c +++ b/src/soc/amd/stoneyridge/i2c.c @@ -56,18 +56,24 @@ return dev->chip_info; } +void __weak mb_update_i2c(unsigned int bus, const struct dw_i2c_bus_config **i2c_vals) {} + const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) { const struct soc_amd_stoneyridge_config *config; - + const struct dw_i2c_bus_config *i2c_vals; if (bus >= ARRAY_SIZE(i2c_bus_address)) return NULL; config = get_soc_config(); if (config == NULL) return NULL; + i2c_vals = &config->i2c[bus]; - return &config->i2c[bus]; + /* Allow mainboard to update the i2c bus settings */ + mb_update_i2c(bus, &i2c_vals); + + return i2c_vals; } const char *i2c_acpi_name(const struct device *dev) diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index a3c4c7c..40e988e 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -556,4 +556,13 @@ /* Initialize all the i2c buses that are not marked with early init. */ void i2c_soc_init(void); +/** + * @brief Allow the mainboard to update i2c values + * + * @param i2c_vals = pointer to the i2c value structure + * + * @return none + */ +void mb_update_i2c(unsigned int bus, const struct dw_i2c_bus_config **i2c_vals); + #endif /* __STONEYRIDGE_H__ */ -- To view, visit https://review.coreboot.org/28904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id00c352a04b3d7845027882bcfcee09518787067 Gerrit-Change-Number: 28904 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: sb/intel/common: Add common reset handler
by Nico Huber (Code Review) 03 Oct '18

03 Oct '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/28862 ) Change subject: sb/intel/common: Add common reset handler ...................................................................... Patch Set 2: I guess vboot is calling the wrong reset function for everything APL/SKL+. Nice mess Intel! -- To view, visit https://review.coreboot.org/28862 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590 Gerrit-Change-Number: 28862 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 03 Oct 2018 14:11:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit October 2018