coreboot-gerrit October 2018

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Change in coreboot[master]: mb/google/kahlee: Don't set stapm parameters
by Raul Rangel (Code Review) 04 Oct '18

04 Oct '18

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/28925 ) Change subject: mb/google/kahlee: Don't set stapm parameters ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2299ab81fcc2af0529bfac3be562b05116c64a49 Gerrit-Change-Number: 28925 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 04 Oct 2018 20:07:19 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/kahlee: Don't set stapm parameters
by Martin Roth (Code Review) 04 Oct '18

04 Oct '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/28925 Change subject: mb/google/kahlee: Don't set stapm parameters ...................................................................... mb/google/kahlee: Don't set stapm parameters Setting the stapm parameters is causing S3 resume failures and performance issues. Removing these settings until more testing is done and the issues are solved. BUG=b:117252463, b:116870267 TEST=boot grunt Change-Id: I2299ab81fcc2af0529bfac3be562b05116c64a49 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/kahlee/variants/careena/devicetree.cb M src/mainboard/google/kahlee/variants/grunt/devicetree.cb 2 files changed, 10 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/28925/1 diff --git a/src/mainboard/google/kahlee/variants/careena/devicetree.cb b/src/mainboard/google/kahlee/variants/careena/devicetree.cb index eb2acb9..08d4d4d 100644 --- a/src/mainboard/google/kahlee/variants/careena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/careena/devicetree.cb @@ -20,9 +20,11 @@ register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" register "uma_size" = "32 * MiB" - register "stapm_percent" = "68" - register "stapm_time" = "2500" - register "stapm_power" = "7800" + + # Don't set STAPM values for now + # register "stapm_percent" = "68" + # register "stapm_time" = "2500" + # register "stapm_power" = "7800" # Enable I2C0 for audio, USB3 hub at 400kHz register "i2c[0]" = "{ diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb index 228ead2..128de7d 100644 --- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb @@ -20,9 +20,11 @@ register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" register "uma_size" = "32 * MiB" - register "stapm_percent" = "80" - register "stapm_time" = "2500" - register "stapm_power" = "7800" + + # For now, don't set STAPM values + # register "stapm_percent" = "80" + # register "stapm_time" = "2500" + # register "stapm_power" = "7800" # Enable I2C0 for audio, USB3 hub at 400kHz register "i2c[0]" = "{ -- To view, visit https://review.coreboot.org/28925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2299ab81fcc2af0529bfac3be562b05116c64a49 Gerrit-Change-Number: 28925 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: soc/intel/common, mb/google, mb/siemens: Use lower case x for RXD
by build bot (Jenkins) (Code Review) 04 Oct '18

04 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28924 ) Change subject: soc/intel/common, mb/google, mb/siemens: Use lower case x for RXD ...................................................................... Patch Set 2: (12 comments) https://review.coreboot.org/#/c/28924/2/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/ampton/gpio.c: https://review.coreboot.org/#/c/28924/2/src/mainboard/google/octopus/varian… PS2, Line 147: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ line over 80 characters https://review.coreboot.org/#/c/28924/2/src/mainboard/google/octopus/varian… PS2, Line 204: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_140 -- PEN_RESET */ line over 80 characters https://review.coreboot.org/#/c/28924/2/src/mainboard/google/octopus/varian… PS2, Line 246: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* EN_PP3300_WLAN */ line over 80 characters https://review.coreboot.org/#/c/28924/2/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/baseboard/gpio.c: https://review.coreboot.org/#/c/28924/2/src/mainboard/google/octopus/varian… PS2, Line 149: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ line over 80 characters https://review.coreboot.org/#/c/28924/2/src/mainboard/google/octopus/varian… PS2, Line 205: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_140 -- PEN_RESET */ line over 80 characters https://review.coreboot.org/#/c/28924/2/src/mainboard/google/octopus/varian… PS2, Line 226: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, Tx1RxDCRx0, DISPUPD), /* AVS_I2S1_MCLK -- LTE_OFF_ODL */ line over 80 characters https://review.coreboot.org/#/c/28924/2/src/mainboard/google/octopus/varian… PS2, Line 247: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* EN_PP3300_WLAN */ line over 80 characters https://review.coreboot.org/#/c/28924/2/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/bip/gpio.c: https://review.coreboot.org/#/c/28924/2/src/mainboard/google/octopus/varian… PS2, Line 147: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ line over 80 characters https://review.coreboot.org/#/c/28924/2/src/mainboard/google/octopus/varian… PS2, Line 204: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_140 -- PEN_RESET */ line over 80 characters https://review.coreboot.org/#/c/28924/2/src/mainboard/google/octopus/varian… PS2, Line 246: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* EN_PP3300_WLAN */ line over 80 characters https://review.coreboot.org/#/c/28924/2/src/mainboard/google/reef/variants/… File src/mainboard/google/reef/variants/baseboard/gpio.c: https://review.coreboot.org/#/c/28924/2/src/mainboard/google/reef/variants/… PS2, Line 330: PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */ line over 80 characters https://review.coreboot.org/#/c/28924/2/src/mainboard/google/reef/variants/… File src/mainboard/google/reef/variants/coral/gpio.c: https://review.coreboot.org/#/c/28924/2/src/mainboard/google/reef/variants/… PS2, Line 330: PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */ line over 80 characters -- To view, visit https://review.coreboot.org/28924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6b1ce259ed184bcf8224dff334fcf0a0289f1788 Gerrit-Change-Number: 28924 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 04 Oct 2018 18:29:17 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/common, mb/google, mb/siemens: Use lower case x for RXD
by build bot (Jenkins) (Code Review) 04 Oct '18

04 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28924 ) Change subject: soc/intel/common, mb/google, mb/siemens: Use lower case x for RXD ...................................................................... Patch Set 1: (9 comments) https://review.coreboot.org/#/c/28924/1/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/baseboard/gpio.c: https://review.coreboot.org/#/c/28924/1/src/mainboard/google/octopus/varian… PS1, Line 149: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ line over 80 characters https://review.coreboot.org/#/c/28924/1/src/mainboard/google/octopus/varian… PS1, Line 205: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_140 -- PEN_RESET */ line over 80 characters https://review.coreboot.org/#/c/28924/1/src/mainboard/google/octopus/varian… PS1, Line 226: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, Tx1RxDCRx0, DISPUPD), /* AVS_I2S1_MCLK -- LTE_OFF_ODL */ line over 80 characters https://review.coreboot.org/#/c/28924/1/src/mainboard/google/octopus/varian… PS1, Line 247: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* EN_PP3300_WLAN */ line over 80 characters https://review.coreboot.org/#/c/28924/1/src/mainboard/google/octopus/varian… File src/mainboard/google/octopus/variants/bip/gpio.c: https://review.coreboot.org/#/c/28924/1/src/mainboard/google/octopus/varian… PS1, Line 147: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ line over 80 characters https://review.coreboot.org/#/c/28924/1/src/mainboard/google/octopus/varian… PS1, Line 204: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_140 -- PEN_RESET */ line over 80 characters https://review.coreboot.org/#/c/28924/1/src/mainboard/google/octopus/varian… PS1, Line 246: PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* EN_PP3300_WLAN */ line over 80 characters https://review.coreboot.org/#/c/28924/1/src/mainboard/google/reef/variants/… File src/mainboard/google/reef/variants/baseboard/gpio.c: https://review.coreboot.org/#/c/28924/1/src/mainboard/google/reef/variants/… PS1, Line 330: PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */ line over 80 characters https://review.coreboot.org/#/c/28924/1/src/mainboard/google/reef/variants/… File src/mainboard/google/reef/variants/coral/gpio.c: https://review.coreboot.org/#/c/28924/1/src/mainboard/google/reef/variants/… PS1, Line 330: PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */ line over 80 characters -- To view, visit https://review.coreboot.org/28924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6b1ce259ed184bcf8224dff334fcf0a0289f1788 Gerrit-Change-Number: 28924 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 04 Oct 2018 18:18:26 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/common, mb/google, mb/siemens: Use lower case x for RXD
by Furquan Shaikh (Code Review) 04 Oct '18

04 Oct '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/28924 Change subject: soc/intel/common, mb/google, mb/siemens: Use lower case x for RXD ...................................................................... soc/intel/common, mb/google, mb/siemens: Use lower case x for RXD In order to make the macro name consistent for all PAD_CFG1_IOSSTATE_* macros, this change uses lower case x for *RXD*. It helps avoid confusion when using the macros. Change-Id: I6b1ce259ed184bcf8224dff334fcf0a0289f1788 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/variants/baseboard/gpio.c M src/mainboard/google/octopus/variants/bip/gpio.c M src/mainboard/google/reef/variants/baseboard/gpio.c M src/mainboard/google/reef/variants/coral/gpio.c M src/mainboard/google/reef/variants/coral/mainboard.c M src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 7 files changed, 15 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/28924/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c index 2b9d4b4..4719a09 100644 --- a/src/mainboard/google/octopus/variants/baseboard/gpio.c +++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c @@ -146,7 +146,7 @@ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/* PMU_SLP_S4_B */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1),/* SUSPWRDNACK */ PAD_NC(GPIO_104, UP_20K),/* EMMC_DNX_PWR_EN_B - unused */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_BATLOW_B */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_107, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_RESETBUTTON_B */ PAD_NC(GPIO_108, NONE),/* PMU_SUSCLK -- unused */ @@ -202,7 +202,7 @@ PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_137 -- HP_INT_ODL */ PAD_CFG_GPI_APIC_IOS(GPIO_138, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_PDCT_ODL */ PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_139 -- PEN_INT_ODL */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 1, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_140 -- PEN_RESET */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_140 -- PEN_RESET */ // Also we may be able to use eSPI WAKE# Virtual Wire instead PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */ PAD_CFG_GPI_SCI_LOW(GPIO_142, NONE, DEEP, LEVEL),/* GPIO_142 -- TRACKPAD_INT2_1V8_ODL */ @@ -223,7 +223,7 @@ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S0_WS_SYNC */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S0_SDI */ PAD_NC(GPIO_160, DN_20K), /* AVS_I2S0_SDO -- unused */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, Tx1RXDCRx0, DISPUPD), /* AVS_I2S1_MCLK -- LTE_OFF_ODL */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, Tx1RxDCRx0, DISPUPD), /* AVS_I2S1_MCLK -- LTE_OFF_ODL */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_BCLK */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_WS_SYNC */ PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ @@ -244,7 +244,7 @@ /* SCC COMMUNITY GPIOS */ PAD_NC(GPIO_176, UP_20K), /* SMB_ALERTB -- unused */ PAD_NC(GPIO_177, UP_20K), /* SMB_CLK -- unused */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 1, DEEP, NONE, Tx1RXDCRx0, DISPUPD), /* EN_PP3300_WLAN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* EN_PP3300_WLAN */ PAD_NC(GPIO_179, NONE), /* SDCARD_CLK -- unused */ PAD_NC(GPIO_180, NONE), /* SDCARD_CMD -- unused */ PAD_NC(GPIO_181, UP_20K), /* SDCARD_D0 -- unused */ @@ -335,7 +335,7 @@ /* GPIO settings before entering slp_s5. */ static const struct pad_config sleep_s5_gpio_table[] = { /* BT_DISABLE_L */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_109, 0, DEEP, NONE, Tx0RXDCRx1, SAME), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_109, 0, DEEP, NONE, Tx0RxDCRx1, SAME), }; const struct pad_config *__weak diff --git a/src/mainboard/google/octopus/variants/bip/gpio.c b/src/mainboard/google/octopus/variants/bip/gpio.c index 1e94b0e..b319a0e 100644 --- a/src/mainboard/google/octopus/variants/bip/gpio.c +++ b/src/mainboard/google/octopus/variants/bip/gpio.c @@ -144,7 +144,7 @@ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/* PMU_SLP_S4_B */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1),/* SUSPWRDNACK */ PAD_NC(GPIO_104, UP_20K),/* EMMC_DNX_PWR_EN_B - unused */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_BATLOW_B */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_107, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_RESETBUTTON_B */ PAD_NC(GPIO_108, NONE),/* PMU_SUSCLK -- unused */ @@ -201,7 +201,7 @@ DISPUPD),/* GPIO_137 -- HP_INT_ODL */ PAD_CFG_GPI_APIC_IOS(GPIO_138, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_PDCT_ODL */ PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_139 -- PEN_INT_ODL */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RXDCRx0, DISPUPD),/* GPIO_140 -- PEN_RESET */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 0, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_140 -- PEN_RESET */ // Also we may be able to use eSPI WAKE# Virtual Wire instead PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */ PAD_CFG_GPI_SCI_LOW(GPIO_142, NONE, DEEP, LEVEL),/* GPIO_142 -- TRACKPAD_INT2_1V8_ODL */ @@ -243,7 +243,7 @@ /* SCC COMMUNITY GPIOS */ PAD_NC(GPIO_176, UP_20K), /* SMB_ALERTB -- unused */ PAD_NC(GPIO_177, UP_20K), /* SMB_CLK -- unused */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 1, DEEP, NONE, Tx1RXDCRx0, DISPUPD), /* EN_PP3300_WLAN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* EN_PP3300_WLAN */ PAD_NC(GPIO_179, NONE), /* SDCARD_CLK -- unused */ PAD_NC(GPIO_180, NONE), /* SDCARD_CMD -- unused */ PAD_NC(GPIO_181, UP_20K), /* SDCARD_D0 -- unused */ diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index 3cd765b..8df5873 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -327,7 +327,7 @@ PAD_CFG_GPO(GPIO_44, 1, DEEP), /* GPS_RST_ODL */ PAD_CFG_GPI(GPIO_45, NONE, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ - PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RXDCRx0), /* LPSS_UART2_TXD */ + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */ PAD_CFG_GPI(GPIO_48, UP_20K, DEEP), /* LPSS_UART2_RTS - unused */ PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE), /* LPSS_UART2_CTS - EC_SMI_L */ diff --git a/src/mainboard/google/reef/variants/coral/gpio.c b/src/mainboard/google/reef/variants/coral/gpio.c index e89e5b5..0c762c0 100644 --- a/src/mainboard/google/reef/variants/coral/gpio.c +++ b/src/mainboard/google/reef/variants/coral/gpio.c @@ -327,7 +327,7 @@ PAD_CFG_GPO(GPIO_44, 1, DEEP), /* GPS_RST_ODL */ PAD_CFG_GPI(GPIO_45, NONE, DEEP), /* LPSS_UART1_CTS - MEM_CONFIG3 */ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ - PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RXDCRx0), /* LPSS_UART2_TXD */ + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* LPSS_UART2_TXD */ PAD_CFG_GPI(GPIO_48, UP_20K, DEEP), /* LPSS_UART2_RTS - unused */ PAD_CFG_GPI_SMI_LOW(GPIO_49, NONE, DEEP, EDGE_SINGLE), /* LPSS_UART2_CTS - EC_SMI_L */ diff --git a/src/mainboard/google/reef/variants/coral/mainboard.c b/src/mainboard/google/reef/variants/coral/mainboard.c index f998763..aad65f0 100644 --- a/src/mainboard/google/reef/variants/coral/mainboard.c +++ b/src/mainboard/google/reef/variants/coral/mainboard.c @@ -136,9 +136,9 @@ static const struct pad_config nasher_gpio_tables[] = { /* AVS_DMIC_CLK_A1 */ - PAD_CFG_NF_IOSSTATE(GPIO_79, NATIVE, DEEP, NF1, Tx1RXDCRx0), + PAD_CFG_NF_IOSSTATE(GPIO_79, NATIVE, DEEP, NF1, Tx1RxDCRx0), /* AVS_DMIC_CLK_B1 */ - PAD_CFG_NF_IOSSTATE(GPIO_80, NATIVE, DEEP, NF1, Tx1RXDCRx0), + PAD_CFG_NF_IOSSTATE(GPIO_80, NATIVE, DEEP, NF1, Tx1RxDCRx0), }; const struct pad_config *variant_sku_gpio_table(size_t *num) diff --git a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c index 28aad8a..c4dcc76 100644 --- a/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/baseboard/gpio.c @@ -332,7 +332,7 @@ PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - unused */ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ /* LPSS_UART2_TXD */ - PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RXDCRx0), + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RxDCRx0), PAD_CFG_GPI(GPIO_48, DN_20K, DEEP), /* LPSS_UART2_RTS - unused */ PAD_CFG_GPI(GPIO_49, UP_20K, DEEP), /* LPSS_UART2_CTS - unused */ diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index a8d5ac9..855659a 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -84,10 +84,10 @@ #define PAD_CFG1_IOSSTATE_Tx0RxDCRx0 (0x1 << 14) /* Tx enabled driving 0, Rx disabled and Rx driving 1 back to its controller * internally */ -#define PAD_CFG1_IOSSTATE_Tx0RXDCRx1 (0x2 << 14) +#define PAD_CFG1_IOSSTATE_Tx0RxDCRx1 (0x2 << 14) /* Tx enabled driving 1, Rx disabled and Rx driving 0 back to its controller * internally */ -#define PAD_CFG1_IOSSTATE_Tx1RXDCRx0 (0x3 << 14) +#define PAD_CFG1_IOSSTATE_Tx1RxDCRx0 (0x3 << 14) /* Tx enabled driving 1, Rx disabled and Rx driving 1 back to its controller * internally */ #define PAD_CFG1_IOSSTATE_Tx1RxDCRx1 (0x4 << 14) -- To view, visit https://review.coreboot.org/28924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6b1ce259ed184bcf8224dff334fcf0a0289f1788 Gerrit-Change-Number: 28924 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: nb/intel/{gm45, i945, pineview}: Use macro instead of GGC address
by Nico Huber (Code Review) 04 Oct '18

04 Oct '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/28909 ) Change subject: nb/intel/{gm45,i945,pineview}: Use macro instead of GGC address ...................................................................... Patch Set 2: >> (1 comment) > > regarding the datasheet, it is 16bits. The register read was already 16 bits. That has nothing to do with the variable you store the value in. > > by the way, there is a conflict with this change : > https://review.coreboot.org/#/c/coreboot/+/17645/ > so maybe I have to keep only changes related to pineview and i945. Doesn't matter. 17645 needs an update anyway. -- To view, visit https://review.coreboot.org/28909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I233e835180fd445961b6deb74ea7afc2821c236e Gerrit-Change-Number: 28909 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 04 Oct 2018 15:28:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: libpayload/x86/exception: Add ability to ignore unknown interrupts
by Martin Roth (Code Review) 04 Oct '18

04 Oct '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28882 ) Change subject: libpayload/x86/exception: Add ability to ignore unknown interrupts ...................................................................... libpayload/x86/exception: Add ability to ignore unknown interrupts This will make enabling the APIC safer by ignoring unknown interrupts and not halting the system. Once all interrupt sources have been found and handled DIE_ON_UNKNOWN_INTERRUPT can be set if desired. BUG=b:116777191 TEST=Booted grunt, halted the kernel, and pushed the power button while in S5. Verified that depthcharge logged the unknown exception. APIC Init Started APIC Configured Ignoring interrupt vector 39 Change-Id: If4ed566ec284d69786c369f37e4e331d7f892c74 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Reviewed-on: https://review.coreboot.org/28882 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M payloads/libpayload/arch/x86/Kconfig M payloads/libpayload/arch/x86/exception.c 2 files changed, 32 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/payloads/libpayload/arch/x86/Kconfig b/payloads/libpayload/arch/x86/Kconfig index cbb21cb..129ff5f 100644 --- a/payloads/libpayload/arch/x86/Kconfig +++ b/payloads/libpayload/arch/x86/Kconfig @@ -37,4 +37,21 @@ config ENABLE_APIC bool "Enables the Local APIC" +choice + prompt "Interrupt Handling" + default LOG_UNKNOWN_INTERRUPTS if ENABLE_APIC + default DIE_ON_UNKNOWN_INTERRUPT + +config IGNORE_UNKNOWN_INTERRUPTS + bool "Ignore unknown user defined interrupts" + +config LOG_UNKNOWN_INTERRUPTS + bool "Logs unknown user defined interrupts to the console" + +config DIE_ON_UNKNOWN_INTERRUPT + bool "Die if an unknown user defined interrupt is encountered" + +endchoice + + endif diff --git a/payloads/libpayload/arch/x86/exception.c b/payloads/libpayload/arch/x86/exception.c index 1fa1304..983a9f3 100644 --- a/payloads/libpayload/arch/x86/exception.c +++ b/payloads/libpayload/arch/x86/exception.c @@ -171,9 +171,14 @@ if (handlers[vec]) { handlers[vec](vec); - if (IS_ENABLED(CONFIG_LP_ENABLE_APIC)) - apic_eoi(vec); - return; + goto success; + } else if (vec >= EXC_COUNT + && IS_ENABLED(CONFIG_LP_IGNORE_UNKNOWN_INTERRUPTS)) { + goto success; + } else if (vec >= EXC_COUNT + && IS_ENABLED(CONFIG_LP_LOG_UNKNOWN_INTERRUPTS)) { + printf("Ignoring interrupt vector %u\n", vec); + goto success; } die_if(vec >= EXC_COUNT || !names[vec], "Bad exception vector %u\n", @@ -181,7 +186,14 @@ dump_exception_state(); dump_stack(exception_state->regs.esp, 512); + /* We don't call apic_eoi because we don't want to ack the interrupt and + allow another interrupt to wake the processor. */ halt(); + return; + +success: + if (IS_ENABLED(CONFIG_LP_ENABLE_APIC)) + apic_eoi(vec); } void exception_init(void) -- To view, visit https://review.coreboot.org/28882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: If4ed566ec284d69786c369f37e4e331d7f892c74 Gerrit-Change-Number: 28882 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: libpayload/x86/exception.c: Remove exception_install_hook
by Martin Roth (Code Review) 04 Oct '18

04 Oct '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28881 ) Change subject: libpayload/x86/exception.c: Remove exception_install_hook ...................................................................... libpayload/x86/exception.c: Remove exception_install_hook Not used by x86 code anymore. BUG=b:116777191 TEST=Validated that depthcharge can be built. Change-Id: I25ad3903989a5433ce73d657cfdb93dd1f34f7b5 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Reviewed-on: https://review.coreboot.org/28881 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M payloads/libpayload/arch/x86/exception.c 1 file changed, 0 insertions(+), 11 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/payloads/libpayload/arch/x86/exception.c b/payloads/libpayload/arch/x86/exception.c index 3cd95bb..1fa1304 100644 --- a/payloads/libpayload/arch/x86/exception.c +++ b/payloads/libpayload/arch/x86/exception.c @@ -37,8 +37,6 @@ u32 exception_stack[0x400] __attribute__((aligned(8))); -static exception_hook hook; - static interrupt_handler handlers[256]; static const char *names[EXC_COUNT] = { @@ -181,9 +179,6 @@ die_if(vec >= EXC_COUNT || !names[vec], "Bad exception vector %u\n", vec); - if (hook && hook(vec)) - return; - dump_exception_state(); dump_stack(exception_state->regs.esp, 512); halt(); @@ -195,12 +190,6 @@ exception_init_asm(); } -void exception_install_hook(exception_hook h) -{ - die_if(hook, "Implement support for a list of hooks if you need it."); - hook = h; -} - void set_interrupt_handler(u8 vector, interrupt_handler handler) { handlers[vector] = handler; -- To view, visit https://review.coreboot.org/28881 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I25ad3903989a5433ce73d657cfdb93dd1f34f7b5 Gerrit-Change-Number: 28881 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: libpayload/apic: Register a spurious interrupt vector
by Martin Roth (Code Review) 04 Oct '18

04 Oct '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28880 ) Change subject: libpayload/apic: Register a spurious interrupt vector ...................................................................... libpayload/apic: Register a spurious interrupt vector We should have a spurious interrupt vector just incase we get one. The handler doesn't need to do anything. BUG=b:116777191 TEST=Booted depthcharge on grunt and inspected the register. I can't generate a spurious interrupt, so I can't validate that the handler gets called. Change-Id: I9e49e617f4375eb5eb00d0715c1902f77e2bf284 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Reviewed-on: https://review.coreboot.org/28880 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M payloads/libpayload/arch/x86/apic.c 1 file changed, 21 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/payloads/libpayload/arch/x86/apic.c b/payloads/libpayload/arch/x86/apic.c index 3b294cb..db81ea1 100644 --- a/payloads/libpayload/arch/x86/apic.c +++ b/payloads/libpayload/arch/x86/apic.c @@ -42,7 +42,6 @@ #define XAPIC_ENABLED_BIT (1 << 11) #define X2APIC_ENABLED_BIT (1 << 10) #define APIC_MASKED_BIT (1 << 16) -#define APIC_SW_ENABLED_BIT (1 << 8) #define APIC_ID 0x020 #define APIC_ID_SHIFT 24 @@ -54,6 +53,9 @@ #define APIC_TASK_PRIORITY_MASK 0xFFUL #define APIC_EOI 0x0B0 #define APIC_SPURIOUS 0x0F0 +#define APIC_SW_ENABLED_BIT (1 << 8) +#define APIC_SPURIOUS_VECTOR_MASK 0xFFUL +#define APIC_SPURIOUS 0x0F0 #define APIC_LVT_TIMER 0x320 #define APIC_TIMER_INIT_COUNT 0x380 #define APIC_TIMER_CUR_COUNT 0x390 @@ -63,7 +65,8 @@ #define APIC_LVT_SIZE 0x010 -#define APIC_TIMER_VECTOR 0x20 +#define APIC_TIMER_VECTOR 0x20UL +#define APIC_SPURIOUS_VECTOR 0xFFUL static uint32_t apic_bar; static int _apic_initialized; @@ -143,6 +146,8 @@ timer_waiting = 0; } +static void suprious_interrupt_handler(u8 vector) {} + void apic_eoi(uint8_t vector) { die_if(!apic_bar, "APIC is not initialized"); @@ -255,6 +260,17 @@ apic_write32(APIC_SPURIOUS, reg); } +static void apic_setup_spurious(void) +{ + uint32_t reg = apic_read32(APIC_SPURIOUS); + + reg &= ~APIC_SPURIOUS_VECTOR_MASK; + + reg |= APIC_SPURIOUS_VECTOR; + + apic_write32(APIC_SPURIOUS, reg); +} + void apic_init(void) { uint64_t apic_bar_reg; @@ -274,12 +290,15 @@ apic_reset_all_lvts(); apic_set_task_priority(0); + apic_setup_spurious(); apic_sw_enable(); apic_init_timer(); set_interrupt_handler(APIC_TIMER_VECTOR, &timer_interrupt_handler); + set_interrupt_handler(APIC_SPURIOUS_VECTOR, + &suprious_interrupt_handler); _apic_initialized = 1; -- To view, visit https://review.coreboot.org/28880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I9e49e617f4375eb5eb00d0715c1902f77e2bf284 Gerrit-Change-Number: 28880 Gerrit-PatchSet: 3 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: libpayload/apic: Only ACK interrupts triggered by the APIC
by Martin Roth (Code Review) 04 Oct '18

04 Oct '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/28879 ) Change subject: libpayload/apic: Only ACK interrupts triggered by the APIC ...................................................................... libpayload/apic: Only ACK interrupts triggered by the APIC Only set end of interrupt (EOI) when the APIC In-Service vector matches the interrupt vector. This makes it so we don't EOI a non APIC interrupt. BUG=b:116777191 TEST=Booted grunt with APIC enabled and verified depthcharge still works. Change-Id: I00bd1e7a0fcf2fc004feadc40d22ebfefe68b384 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Reviewed-on: https://review.coreboot.org/28879 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M payloads/libpayload/arch/x86/apic.c M payloads/libpayload/arch/x86/exception.c M payloads/libpayload/include/x86/arch/apic.h 3 files changed, 27 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/payloads/libpayload/arch/x86/apic.c b/payloads/libpayload/arch/x86/apic.c index 048cc66..3b294cb 100644 --- a/payloads/libpayload/arch/x86/apic.c +++ b/payloads/libpayload/arch/x86/apic.c @@ -58,6 +58,8 @@ #define APIC_TIMER_INIT_COUNT 0x380 #define APIC_TIMER_CUR_COUNT 0x390 #define APIC_TIMER_DIV_CFG 0x3E0 +#define APIC_ISR_0 0x100 +#define APIC_ISR_OFFSET 0x010 #define APIC_LVT_SIZE 0x010 @@ -141,11 +143,28 @@ timer_waiting = 0; } -void apic_eoi(void) +void apic_eoi(uint8_t vector) { die_if(!apic_bar, "APIC is not initialized"); - apic_write32(APIC_EOI, 0); + /* + * Local and I/O APICs support 240 vectors (in the range of 16 to 255) + * as valid interrupts. + */ + if (vector <= 15) + return; + + /* Each bank handles 32 vectors */ + uint8_t bank = vector / 32; + + uint32_t offset = APIC_ISR_0 + bank * APIC_ISR_OFFSET; + + uint32_t mask = apic_read32(offset); + + uint8_t shift = vector % 32; + + if (mask & (1 << shift)) + apic_write32(APIC_EOI, 0); } static enum APIC_CAPABILITY apic_capabilities(void) diff --git a/payloads/libpayload/arch/x86/exception.c b/payloads/libpayload/arch/x86/exception.c index 2691c85..3cd95bb 100644 --- a/payloads/libpayload/arch/x86/exception.c +++ b/payloads/libpayload/arch/x86/exception.c @@ -34,13 +34,6 @@ #include <arch/apic.h> #define IF_FLAG (1 << 9) -/* - * Local and I/O APICs support 240 vectors (in the range of 16 to 255) as valid - * interrupts. The Intel 64 and IA-32 architectures reserve vectors 16 - * through 31 for predefined interrupts, exceptions, and Intel-reserved - * encodings. -*/ -#define FIRST_USER_DEFINED_VECTOR 32 u32 exception_stack[0x400] __attribute__((aligned(8))); @@ -173,15 +166,15 @@ void exception_dispatch(void) { - u32 vec = exception_state->vector; + die_if(exception_state->vector >= ARRAY_SIZE(handlers), + "Invalid vector %u\n", exception_state->vector); - die_if(vec >= ARRAY_SIZE(handlers), "Invalid vector %u\n", vec); + u8 vec = exception_state->vector; if (handlers[vec]) { handlers[vec](vec); - if (IS_ENABLED(CONFIG_LP_ENABLE_APIC) - && vec >= FIRST_USER_DEFINED_VECTOR) - apic_eoi(); + if (IS_ENABLED(CONFIG_LP_ENABLE_APIC)) + apic_eoi(vec); return; } diff --git a/payloads/libpayload/include/x86/arch/apic.h b/payloads/libpayload/include/x86/arch/apic.h index c28fc0f..1eb3508 100644 --- a/payloads/libpayload/include/x86/arch/apic.h +++ b/payloads/libpayload/include/x86/arch/apic.h @@ -38,7 +38,7 @@ uint8_t apic_id(void); /** Signal the end of the interrupt handler. */ -void apic_eoi(void); +void apic_eoi(uint8_t vector); void apic_delay(unsigned int usec); -- To view, visit https://review.coreboot.org/28879 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I00bd1e7a0fcf2fc004feadc40d22ebfefe68b384 Gerrit-Change-Number: 28879 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit October 2018