coreboot-gerrit October 2018

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Change in coreboot[master]: src: Use tabs for code indent
by build bot (Jenkins) (Code Review) 05 Oct '18

05 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28934 ) Change subject: src: Use tabs for code indent ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/28934/2/src/soc/qualcomm/ipq806x/gpio.c File src/soc/qualcomm/ipq806x/gpio.c: https://review.coreboot.org/#/c/28934/2/src/soc/qualcomm/ipq806x/gpio.c@66 PS2, Line 66: unsigned val = 0; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/28934/2/src/soc/qualcomm/ipq806x/gpio.c@96 PS2, Line 96: unsigned val; Prefer 'unsigned int' to bare use of 'unsigned' -- To view, visit https://review.coreboot.org/28934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba Gerrit-Change-Number: 28934 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 05 Oct 2018 09:31:18 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src: Use tabs for code indent
by Elyes HAOUAS (Code Review) 05 Oct '18

05 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28934 to look at the new patch set (#2). Change subject: src: Use tabs for code indent ...................................................................... src: Use tabs for code indent Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/hypertransport.c M src/drivers/i2c/at24rf08c/at24rf08c.c M src/drivers/i2c/at24rf08c/lenovo_serials.c M src/drivers/intel/gma/int15.c M src/drivers/intel/gma/intel_bios.h M src/drivers/intel/wifi/wifi.c M src/drivers/vpd/lib_vpd.h M src/ec/roda/it8518/acpi/ec.asl M src/ec/smsc/mec1308/acpi/ec.asl M src/northbridge/amd/amdfam10/amdfam10_util.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/via/vx900/lpc.c M src/soc/imgtec/pistachio/bootblock.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/nhlt.c M src/soc/intel/baytrail/gpio.c M src/soc/intel/baytrail/pmutil.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/cannonlake/cbmem.c M src/soc/intel/cannonlake/nhlt.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/fsp_baytrail/gpio.c M src/soc/intel/skylake/acpi/dptf/thermal.asl M src/soc/intel/skylake/acpi/xhci.asl M src/soc/intel/skylake/nhlt/max98373.c M src/soc/mediatek/mt8173/dramc_pi_basic_api.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/mediatek/mt8173/mt6391.c M src/soc/nvidia/tegra/i2c.c M src/soc/nvidia/tegra124/chip.h M src/soc/nvidia/tegra124/display.c M src/soc/nvidia/tegra124/dp.c M src/soc/nvidia/tegra210/dc.c M src/soc/nvidia/tegra210/dsi.c M src/soc/nvidia/tegra210/romstage_asm.S M src/soc/nvidia/tegra210/stack.S M src/soc/qualcomm/ipq806x/gpio.c M src/soc/samsung/exynos5420/clock_init.c M src/soc/samsung/exynos5420/fimd.c M src/southbridge/intel/bd82x6x/acpi/platform.asl M src/southbridge/intel/bd82x6x/acpi/usb.asl M src/southbridge/intel/lynxpoint/early_pch.c 43 files changed, 144 insertions(+), 144 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/28934/2 -- To view, visit https://review.coreboot.org/28934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba Gerrit-Change-Number: 28934 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src/nb: Use tabs for code indent
by Elyes HAOUAS (Code Review) 05 Oct '18

05 Oct '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28934 Change subject: src/nb: Use tabs for code indent ...................................................................... src/nb: Use tabs for code indent Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/amdfam10/amdfam10_util.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/via/vx900/lpc.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/28934/1 diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c index e0195c6..9d249e2 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_util.c +++ b/src/northbridge/amd/amdfam10/amdfam10_util.c @@ -26,7 +26,7 @@ #include <include/device/pci_def.h> u32 Get_NB32(u32 dev, u32 reg) { - return pci_read_config32(dev_find_slot(0, PCI_DEV2DEVFN(dev)), reg); + return pci_read_config32(dev_find_slot(0, PCI_DEV2DEVFN(dev)), reg); } #endif diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index 8704d39..64131d8 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -43,7 +43,7 @@ static void set_db(const struct sysinfo *s, struct dll_setting *dq_dqs_setting) { - struct db_limit limit; + struct db_limit limit; switch (s->selected_timings.mem_clk) { default: diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index b90e2d4..b9dac56 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -209,7 +209,7 @@ static void vx900_lpc_set_resources(struct device *dev) { struct resource *mmio, *spi; - u32 reg; + u32 reg; mmio = find_resource(dev, VX900_MMCONFIG_MBAR); if (mmio) { -- To view, visit https://review.coreboot.org/28934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba Gerrit-Change-Number: 28934 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: acpi: Reverse logic for setting PCIEXP_WAKE_DIS bit in PM1_EN_STS
by Nick Vaccaro (Code Review) 05 Oct '18

05 Oct '18

Nick Vaccaro has abandoned this change. ( https://review.coreboot.org/28932 ) Change subject: acpi: Reverse logic for setting PCIEXP_WAKE_DIS bit in PM1_EN_STS ...................................................................... Abandoned This change is wrong. -- To view, visit https://review.coreboot.org/28932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Id8b14ae2ae4d97e184906dec468b405134d590da Gerrit-Change-Number: 28932 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: acpi: Reverse logic for setting PCIEXP_WAKE_DIS bit in PM1_EN_STS
by Nick Vaccaro (Code Review) 05 Oct '18

05 Oct '18

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/28932 ) Change subject: acpi: Reverse logic for setting PCIEXP_WAKE_DIS bit in PM1_EN_STS ...................................................................... Patch Set 2: (6 comments) Based on Furquan's explanation, I'm abandoning this change as this code was not doing what I though it was doing. Sorry for the thrash. https://review.coreboot.org/#/c/28932/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28932/2//COMMIT_MSG@9 PS2, Line 9: The logic for setting PCIEXP_WAKE_DIS bit is backwards > The function you are changing does not enable or disable PCIEXP_WAKE_DIS. It looks like that's where it sets the PCIEXP_WAKE_DIS bit in pm1_en. https://review.coreboot.org/#/c/28932/2//COMMIT_MSG@21 PS2, Line 21: TEST > I am really surprised that the changes in this CL actually help. They haven't shown to help, which is why I have it set to -1. https://review.coreboot.org/#/c/28932/2/src/soc/intel/skylake/acpi.c File src/soc/intel/skylake/acpi.c: https://review.coreboot.org/#/c/28932/2/src/soc/intel/skylake/acpi.c@691 PS2, Line 691: soc_fill_acpi_wake > This function, as the comment says above, is used to only identify the wake source during resume. […] Ack https://review.coreboot.org/#/c/28932/2/src/soc/intel/skylake/acpi.c@718 PS2, Line 718: if ((config->deep_sx_config & DSX_EN_WAKE_PIN) == 0) > if (!(config->deep_sx_config & DSX_EN_WAKE_PIN)) Ack https://review.coreboot.org/#/c/28932/2/src/soc/intel/skylake/acpi.c@719 PS2, Line 719: pm1_en |= PCIEXPWAK_STS; > The intent of this code is to check if DSX_EN_WAKE_PIN was enabled for wake and if yes, then set PCI […] Ack https://review.coreboot.org/#/c/28932/2/src/soc/intel/skylake/acpi.c@722 PS2, Line 722: *pm1 = ps->pm1_sts & pm1_en; : > This is where it masks the status read from PM1_STS using the valid bits that were set in pm1_en. […] Ack -- To view, visit https://review.coreboot.org/28932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id8b14ae2ae4d97e184906dec468b405134d590da Gerrit-Change-Number: 28932 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 05 Oct 2018 06:39:51 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/var/ampton: Get rid of min board id for DRAM in CBI
by Furquan Shaikh (Code Review) 05 Oct '18

05 Oct '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/28933 Change subject: mb/google/poppy/var/ampton: Get rid of min board id for DRAM in CBI ...................................................................... mb/google/poppy/var/ampton: Get rid of min board id for DRAM in CBI All ampton boards should have the DRAM info configured in CBI and so DRAM_PART_NUM_ALWAYS_IN_CBI is already selected for ampton. This change gets rid of the redundant minimum board id value for Ampton. BUG=b:117071184 Change-Id: I59f60b8c5aa34b55b8e473c06cc49ea7ae284d62 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/octopus/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/28933/1 diff --git a/src/mainboard/google/octopus/Kconfig b/src/mainboard/google/octopus/Kconfig index ba1e861..62a7486 100644 --- a/src/mainboard/google/octopus/Kconfig +++ b/src/mainboard/google/octopus/Kconfig @@ -133,7 +133,6 @@ default 2 if BOARD_GOOGLE_FLEEX default 9 if BOARD_GOOGLE_BOBBA default 1 if BOARD_GOOGLE_MEEP - default 255 if BOARD_GOOGLE_AMPTON default 255 if BOARD_GOOGLE_OCTOPUS endif # BOARD_GOOGLE_OCTOPUS -- To view, visit https://review.coreboot.org/28933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I59f60b8c5aa34b55b8e473c06cc49ea7ae284d62 Gerrit-Change-Number: 28933 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: Disable WAKE# signal
by Furquan Shaikh (Code Review) 05 Oct '18

05 Oct '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/28926 ) Change subject: mb/google/poppy/variant/nocturne: Disable WAKE# signal ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28926/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nocturne/devicetree.cb: https://review.coreboot.org/#/c/28926/1/src/mainboard/google/poppy/variants… PS1, Line 396: GPE0_PCI_EXP This should also be updated as it is not correct. -- To view, visit https://review.coreboot.org/28926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1c25e4ba28cd2b8807cd155d47c29c0d3ee9e8a5 Gerrit-Change-Number: 28926 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 05 Oct 2018 06:30:21 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: acpi: Reverse logic for setting PCIEXP_WAKE_DIS bit in PM1_EN_STS
by Furquan Shaikh (Code Review) 05 Oct '18

05 Oct '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/28932 ) Change subject: acpi: Reverse logic for setting PCIEXP_WAKE_DIS bit in PM1_EN_STS ...................................................................... Patch Set 2: (5 comments) https://review.coreboot.org/#/c/28932/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28932/2//COMMIT_MSG@9 PS2, Line 9: The logic for setting PCIEXP_WAKE_DIS bit is backwards The function you are changing does not enable or disable PCIEXP_WAKE_DIS. https://review.coreboot.org/#/c/28932/2//COMMIT_MSG@21 PS2, Line 21: TEST I am really surprised that the changes in this CL actually help. https://review.coreboot.org/#/c/28932/2/src/soc/intel/skylake/acpi.c File src/soc/intel/skylake/acpi.c: https://review.coreboot.org/#/c/28932/2/src/soc/intel/skylake/acpi.c@691 PS2, Line 691: soc_fill_acpi_wake This function, as the comment says above, is used to only identify the wake source during resume. It does not actually write to PM1_EN_STS register to enable/disable any wake bits. https://review.coreboot.org/#/c/28932/2/src/soc/intel/skylake/acpi.c@719 PS2, Line 719: pm1_en |= PCIEXPWAK_STS; The intent of this code is to check if DSX_EN_WAKE_PIN was enabled for wake and if yes, then set PCIEXPWAK_STS to mask the pm1_sts bits in order to identify the true wake source. It is not used to enable or disable wake using the WAKE# pin. That is the reason why it is using PCIEXPWAK_STS and not PCIEXPWAK_DIS macro. https://review.coreboot.org/#/c/28932/2/src/soc/intel/skylake/acpi.c@722 PS2, Line 722: *pm1 = ps->pm1_sts & pm1_en; : This is where it masks the status read from PM1_STS using the valid bits that were set in pm1_en. The logic here is that some bits in PM1_EN get lost when waking from Deep Sx. This is because the bits reside in different power wells as indicated by the comment in line 710. Hence, the code in this function: 1. Reads current pm1_en from ps->pm1_en into pm1_en 2. ORs pm1_en with PWRBTN_STS and PCIEXPWAK_STS if DSX_EN_WAKE_PIN is set. This mask obtained using #1 and #2 is used to identify the wake source from pm1_sts. -- To view, visit https://review.coreboot.org/28932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id8b14ae2ae4d97e184906dec468b405134d590da Gerrit-Change-Number: 28932 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 05 Oct 2018 06:30:13 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: acpi: Reverse logic for setting PCIEXP_WAKE_DIS bit in PM1_EN_STS
by Lijian Zhao (Code Review) 05 Oct '18

05 Oct '18

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/28932 ) Change subject: acpi: Reverse logic for setting PCIEXP_WAKE_DIS bit in PM1_EN_STS ...................................................................... Patch Set 2: (1 comment) I don't think the change can fix the problem are facing now, I will suggest a force programming in mainboard smi, or just regular boot stage. https://review.coreboot.org/#/c/28932/2/src/soc/intel/skylake/acpi.c File src/soc/intel/skylake/acpi.c: https://review.coreboot.org/#/c/28932/2/src/soc/intel/skylake/acpi.c@718 PS2, Line 718: if ((config->deep_sx_config & DSX_EN_WAKE_PIN) == 0) if (!(config->deep_sx_config & DSX_EN_WAKE_PIN)) -- To view, visit https://review.coreboot.org/28932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id8b14ae2ae4d97e184906dec468b405134d590da Gerrit-Change-Number: 28932 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 05 Oct 2018 04:35:34 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: acpi: Reverse logic for setting PCIEXP_WAKE_DIS bit in PM1_EN_STS
by Nick Vaccaro (Code Review) 05 Oct '18

05 Oct '18

Hello Duncan Laurie, Lijian Zhao, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/28932 to look at the new patch set (#2). Change subject: acpi: Reverse logic for setting PCIEXP_WAKE_DIS bit in PM1_EN_STS ...................................................................... acpi: Reverse logic for setting PCIEXP_WAKE_DIS bit in PM1_EN_STS The logic for setting PCIEXP_WAKE_DIS bit is backwards. According to EDS, PCIEXP_WAKE_DIS bit should be set to disable "the inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register from waking the system", but the logic was setting that bit if DSX_EN_WAKE_PIN is enabled, not disabled. This was causing spurious wake issues on nocturne. Changed logic to set the PCIEXP_WAKE_DIS (PCIEXPWAK_STS) bit if DSX_EN_WAKE_PIN is not defined in deep_sx_config register in devicetree.cb. BUG=b:111683988 TEST="emerge-nocturne coreboot chromeos-bootimage', flash build onto nocturne, boot nocturne, and verify that pulling WAKE# pin low does not wake the system. Change-Id: Id8b14ae2ae4d97e184906dec468b405134d590da Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/soc/intel/skylake/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/28932/2 -- To view, visit https://review.coreboot.org/28932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id8b14ae2ae4d97e184906dec468b405134d590da Gerrit-Change-Number: 28932 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit October 2018