Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/28578 )
Change subject: [WIP]KBL: Update FSP headers - upgrade to FSP 3.6.2
......................................................................
Patch Set 1: Code-Review-2
We will directly use the FSP from the github repo See. 28593
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Gerrit-Change-Id: I827fa17bef597178016782e13499efe751d7b675
Gerrit-Change-Number: 28578
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Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/28775 )
Change subject: 3rdparty/fsp: update to current master
......................................................................
3rdparty/fsp: update to current master
This includes the SplitFspBin.py script.
Change-Id: I6323a7a1a2bd9b5e11c0b21e5ea991a3fbd3daac
Signed-off-by: Patrick Georgi <pgeorgi(a)google.com>
Reviewed-on: https://review.coreboot.org/28775
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
M 3rdparty/fsp
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Philipp Deppenwiese: Looks good to me, approved
diff --git a/3rdparty/fsp b/3rdparty/fsp
index 7431e4f..162719b 160000
--- a/3rdparty/fsp
+++ b/3rdparty/fsp
@@ -1 +1 @@
-Subproject commit 7431e4f3399a5081c956753b5fa3bcd764196723
+Subproject commit 162719b6cb5efc6c50dcb23dfdb378358573e2b6
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Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/28775 )
Change subject: 3rdparty/fsp: update to current master
......................................................................
Patch Set 3: Code-Review+2
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Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/28908 )
Change subject: LinuxBoot/arm64: Remove firmware from defconfig
......................................................................
LinuxBoot/arm64: Remove firmware from defconfig
The extra firmware is not part of upstream kernel.
Fixes build error if the firmware is not present.
Change-Id: Ifbcb0bb0e2edf3aa260b40dfa339812019f9f0b3
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Reviewed-on: https://review.coreboot.org/28908
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
---
M payloads/external/LinuxBoot/arm64/defconfig
1 file changed, 0 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Philipp Deppenwiese: Looks good to me, approved
Angel Pons: Looks good to me, but someone else must approve
diff --git a/payloads/external/LinuxBoot/arm64/defconfig b/payloads/external/LinuxBoot/arm64/defconfig
index 6f68019..ffb6702 100644
--- a/payloads/external/LinuxBoot/arm64/defconfig
+++ b/payloads/external/LinuxBoot/arm64/defconfig
@@ -114,7 +114,6 @@
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_EXTRA_FIRMWARE="cpt8x-mc-ae.out cpt8x-mc-se.out"
CONFIG_DMA_CMA=y
CONFIG_MTD=y
CONFIG_MTD_NAND=y
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Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/28908 )
Change subject: LinuxBoot/arm64: Remove firmware from defconfig
......................................................................
Patch Set 1: Code-Review+2
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Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/28861 )
Change subject: drivers/spi/winbond: Add new chip
......................................................................
drivers/spi/winbond: Add new chip
The W25Q128J is a QSPI flash chip, without ~HOLD and ~WP.
Add the device id to make coreboot boot from it.
Change-Id: I623fdf7d7e30eb28259bec6294785ad873f1f503
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Reviewed-on: https://review.coreboot.org/28861
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
---
M src/drivers/spi/winbond.c
1 file changed, 10 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Philipp Deppenwiese: Looks good to me, approved
Julius Werner: Looks good to me, approved
Angel Pons: Looks good to me, but someone else must approve
diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c
index a6089b5..e2c6538 100644
--- a/src/drivers/spi/winbond.c
+++ b/src/drivers/spi/winbond.c
@@ -179,6 +179,16 @@
.bp_bits = 3,
},
{
+ .id = 0x7018,
+ .l2_page_size_shift = 8,
+ .pages_per_sector_shift = 4,
+ .sectors_per_block_shift = 4,
+ .nr_blocks_shift = 8,
+ .name = "W25Q128J",
+ .protection_granularity_shift = 18,
+ .bp_bits = 3,
+ },
+ {
.id = 0x4019,
.l2_page_size_shift = 8,
.pages_per_sector_shift = 4,
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Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/28861 )
Change subject: drivers/spi/winbond: Add new chip
......................................................................
Patch Set 3: Code-Review+2
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Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/28932 )
Change subject: acpi: Reverse logic for setting PCIEXPWAK_STS bit in PM1_EN_STS
......................................................................
Patch Set 1: Code-Review-1
I am still in process of verifying out this change, but since I will not be available tomorrow, I wanted to get this CL posted where others can get to it.
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Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/28932
Change subject: acpi: Reverse logic for setting PCIEXPWAK_STS bit in PM1_EN_STS
......................................................................
acpi: Reverse logic for setting PCIEXPWAK_STS bit in PM1_EN_STS
The logic for setting the PCIEXPWAK_STS is backwards. According
to EDS, PCIEXPWAK_STS should be set to disable "the inputs to
the PCIEXP_WAKE_STS bit in the PM1 Status register from waking the
system", but the logic was setting that bit if DSX_EN_WAKE_PIN is
enabled, not disabled. This was causing spurious wake issues on
nocturne.
Changed logic to set the PCIEXPWAK_STS bit if DSX_EN_WAKE_PIN is
not defined in deep_sx_config register in devicetree.cb.
BUG=b:111683988
TEST="emerge-nocturne coreboot chromeos-bootimage', flash build
onto nocturne, boot nocturne, and verify that pulling WAKE# pin
low does not wake the system.
Change-Id: Id8b14ae2ae4d97e184906dec468b405134d590da
Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com>
---
M src/soc/intel/skylake/acpi.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/28932/1
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index d2ec7e7..bc3ea45 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -715,7 +715,7 @@
pm1_en |= PWRBTN_STS; /* Always enabled as wake source */
if (config->deep_sx_config & DSX_EN_LAN_WAKE_PIN)
gpe0_std |= LAN_WAK_EN;
- if (config->deep_sx_config & DSX_EN_WAKE_PIN)
+ if ((config->deep_sx_config & DSX_EN_WAKE_PIN) == 0)
pm1_en |= PCIEXPWAK_STS;
}
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