coreboot-gerrit October 2018

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Change in coreboot[master]: commonlib/region: Add region protect API
by build bot (Jenkins) (Code Review) 04 Oct '18

04 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28724 ) Change subject: commonlib/region: Add region protect API ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/28724/4/src/commonlib/include/commonlib/reg… File src/commonlib/include/commonlib/region.h: https://review.coreboot.org/#/c/28724/4/src/commonlib/include/commonlib/reg… PS4, Line 97: int (*protect)(const struct region *); function definition argument 'const struct region *' should also have an identifier name -- To view, visit https://review.coreboot.org/28724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a Gerrit-Change-Number: 28724 Gerrit-PatchSet: 4 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 04 Oct 2018 14:54:58 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/{gm45, i945, pineview}: Use macro instead of GGC address
by Elyes HAOUAS (Code Review) 04 Oct '18

04 Oct '18

Elyes HAOUAS has posted comments on this change. ( https://review.coreboot.org/28909 ) Change subject: nb/intel/{gm45,i945,pineview}: Use macro instead of GGC address ...................................................................... Patch Set 2: > (1 comment) regarding the datasheet, it is 16bits. by the way, there is a conflict with this change : https://review.coreboot.org/#/c/coreboot/+/17645/ so maybe I have to keep only changes related to pineview and i945. -- To view, visit https://review.coreboot.org/28909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I233e835180fd445961b6deb74ea7afc2821c236e Gerrit-Change-Number: 28909 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 04 Oct 2018 14:42:36 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/{gm45, i945, pineview}: Use macro instead of GGC address
by Nico Huber (Code Review) 04 Oct '18

04 Oct '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/28909 ) Change subject: nb/intel/{gm45,i945,pineview}: Use macro instead of GGC address ...................................................................... Patch Set 2: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/28909/1/src/northbridge/intel/gm45/iommu.c File src/northbridge/intel/gm45/iommu.c: https://review.coreboot.org/#/c/28909/1/src/northbridge/intel/gm45/iommu.c@… PS1, Line 49: u16 gtt > u16 ? You can use u16, but it might be slower (not sure how Intel implements it). -- To view, visit https://review.coreboot.org/28909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I233e835180fd445961b6deb74ea7afc2821c236e Gerrit-Change-Number: 28909 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 04 Oct 2018 13:05:00 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/{gm45, i945, pineview}: Use macro instead of GGC address
by Elyes HAOUAS (Code Review) 04 Oct '18

04 Oct '18

Hello build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/28909 to look at the new patch set (#2). Change subject: nb/intel/{gm45,i945,pineview}: Use macro instead of GGC address ...................................................................... nb/intel/{gm45,i945,pineview}: Use macro instead of GGC address Change-Id: I233e835180fd445961b6deb74ea7afc2821c236e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/gm45/iommu.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/pineview/gma.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/28909/2 -- To view, visit https://review.coreboot.org/28909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I233e835180fd445961b6deb74ea7afc2821c236e Gerrit-Change-Number: 28909 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/{gm45, i945, pineview}: Use macro instead of GGC address
by Elyes HAOUAS (Code Review) 04 Oct '18

04 Oct '18

Elyes HAOUAS has posted comments on this change. ( https://review.coreboot.org/28909 ) Change subject: nb/intel/{gm45,i945,pineview}: Use macro instead of GGC address ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28909/1/src/northbridge/intel/gm45/iommu.c File src/northbridge/intel/gm45/iommu.c: https://review.coreboot.org/#/c/28909/1/src/northbridge/intel/gm45/iommu.c@… PS1, Line 49: u32 gtt u16 ? -- To view, visit https://review.coreboot.org/28909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I233e835180fd445961b6deb74ea7afc2821c236e Gerrit-Change-Number: 28909 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 04 Oct 2018 11:58:12 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/{gm45, i945, pineview}: Use macro instead of GGC address
by Elyes HAOUAS (Code Review) 04 Oct '18

04 Oct '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28909 Change subject: nb/intel/{gm45,i945,pineview}: Use macro instead of GGC address ...................................................................... nb/intel/{gm45,i945,pineview}: Use macro instead of GGC address Change-Id: I233e835180fd445961b6deb74ea7afc2821c236e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/gm45/iommu.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/pineview/gma.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/28909/1 diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 0108116..3a93dc5 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -46,7 +46,7 @@ MCHBAR32(0x20) = IOMMU_BASE4 | 1; /* all other DMA sources */ /* clear GTT */ - u32 gtt = pci_read_config16(PCI_DEV(0, 0, 0), 0x52); + u32 gtt = pci_read_config16(PCI_DEV(0, 0, 0), D0F0_GGC); if (gtt & 0x400) { /* VT mode */ pci_devfn_t igd = PCI_DEV(0, 2, 0); diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 7de2c73..a38874a 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -685,7 +685,7 @@ if (reg32 == 0x030000) { printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n"); reg16 = (1 << 1); - pci_write_config16(PCI_DEV(0, 0x0, 0), 0x52, reg16); + pci_write_config16(PCI_DEV(0, 0x0, 0), GGC, reg16); reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), DEVEN); reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1); diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index eb67c65..e075ac1 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -98,7 +98,7 @@ gtt_setup(mmio); - pci_write_config16(vga, 0x52, 0x130); + pci_write_config16(vga, GGC, 0x130); /* Disable VGA. */ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -- To view, visit https://review.coreboot.org/28909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I233e835180fd445961b6deb74ea7afc2821c236e Gerrit-Change-Number: 28909 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: LinuxBoot/arm64: Remove firmware from defconfig
by Patrick Rudolph (Code Review) 04 Oct '18

04 Oct '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/28908 Change subject: LinuxBoot/arm64: Remove firmware from defconfig ...................................................................... LinuxBoot/arm64: Remove firmware from defconfig The extra firmware is not part of upstream kernel. Fixes build error if the firmware is not present. Change-Id: Ifbcb0bb0e2edf3aa260b40dfa339812019f9f0b3 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M payloads/external/LinuxBoot/arm64/defconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/28908/1 diff --git a/payloads/external/LinuxBoot/arm64/defconfig b/payloads/external/LinuxBoot/arm64/defconfig index 6f68019..ffb6702 100644 --- a/payloads/external/LinuxBoot/arm64/defconfig +++ b/payloads/external/LinuxBoot/arm64/defconfig @@ -114,7 +114,6 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y -CONFIG_EXTRA_FIRMWARE="cpt8x-mc-ae.out cpt8x-mc-se.out" CONFIG_DMA_CMA=y CONFIG_MTD=y CONFIG_MTD_NAND=y -- To view, visit https://review.coreboot.org/28908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifbcb0bb0e2edf3aa260b40dfa339812019f9f0b3 Gerrit-Change-Number: 28908 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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Change in coreboot[master]: amd/stoneyridge: Use BIOS_DEBUG to log PM1 and PMxC0 status
by Patrick Georgi (Code Review) 04 Oct '18

04 Oct '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28885 ) Change subject: amd/stoneyridge: Use BIOS_DEBUG to log PM1 and PMxC0 status ...................................................................... amd/stoneyridge: Use BIOS_DEBUG to log PM1 and PMxC0 status Use BIOS_DEBUG consistently to log PM1 and PMxC0 status registers on boot. print_num_status_bits() was already using BIOS_DEBUG. TEST=Inspect console for Grunt BUG=b:110788201 Change-Id: If7da8c7c86e90a661338903ad05cc41e11f507d2 Signed-off-by: Edward Hill <ecgh(a)chromium.org> Reviewed-on: https://review.coreboot.org/28885 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/stoneyridge/southbridge.c 1 file changed, 6 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index b122f83..763ddd7 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -667,7 +667,7 @@ /* PMxC0 S5/Reset Status shows the source of previous reset. */ uint32_t pmxc0_status = pm_read32(PM_RST_STATUS); - static const char *const pmxc0_status_bits[] = { + static const char *const pmxc0_status_bits[32] = { [0] = "ThermalTrip", [1] = "FourSecondPwrBtn", [2] = "Shutdown", @@ -688,13 +688,12 @@ [27] = "SyncFlood", [28] = "HangReset", [29] = "EcWatchdogRst", - [31] = "BIT31", }; - printk(BIOS_SPEW, "PMxC0 STATUS: 0x%x ", pmxc0_status); + printk(BIOS_DEBUG, "PMxC0 STATUS: 0x%x ", pmxc0_status); print_num_status_bits(ARRAY_SIZE(pmxc0_status_bits), pmxc0_status, pmxc0_status_bits); - printk(BIOS_SPEW, "\n"); + printk(BIOS_DEBUG, "\n"); } /* After console init */ @@ -763,7 +762,7 @@ static uint16_t print_pm1_status(uint16_t pm1_sts) { - static const char *const pm1_sts_bits[] = { + static const char *const pm1_sts_bits[16] = { [0] = "TMROF", [4] = "BMSTATUS", [5] = "GBL", @@ -776,9 +775,9 @@ if (!pm1_sts) return 0; - printk(BIOS_SPEW, "PM1_STS: "); + printk(BIOS_DEBUG, "PM1_STS: "); print_num_status_bits(ARRAY_SIZE(pm1_sts_bits), pm1_sts, pm1_sts_bits); - printk(BIOS_SPEW, "\n"); + printk(BIOS_DEBUG, "\n"); return pm1_sts; } -- To view, visit https://review.coreboot.org/28885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: If7da8c7c86e90a661338903ad05cc41e11f507d2 Gerrit-Change-Number: 28885 Gerrit-PatchSet: 2 Gerrit-Owner: Edward Hill <ecgh(a)chromium.org> Gerrit-Reviewer: Edward Hill <ecgh(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: cpu/intel/car: Fix typo
by Patrick Georgi (Code Review) 04 Oct '18

04 Oct '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28805 ) Change subject: cpu/intel/car: Fix typo ...................................................................... cpu/intel/car: Fix typo Change-Id: If71ab647f012a735c6aa6939463414407757ab9a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/28805 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S 3 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index f47e812..9a433d6 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -55,7 +55,7 @@ wrmsr jnz clear_fixed_mtrr - /* Figure put how many MTRRs we have, and clear them out */ + /* Figure out how many MTRRs we have, and clear them out */ mov $MTRR_CAP_MSR, %ecx rdmsr movzb %al, %ebx /* Number of variable MTRRs */ diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index b3bf230..121d169 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -43,7 +43,7 @@ wrmsr jnz clear_fixed_mtrr - /* Figure put how many MTRRs we have, and clear them out */ + /* Figure out how many MTRRs we have, and clear them out */ mov $MTRR_CAP_MSR, %ecx rdmsr movzb %al, %ebx /* Number of variable MTRRs */ diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 316d452..eb5e490 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -53,7 +53,7 @@ wrmsr jnz clear_fixed_mtrr - /* Figure put how many MTRRs we have, and clear them out */ + /* Figure out how many MTRRs we have, and clear them out */ mov $MTRR_CAP_MSR, %ecx rdmsr movzb %al, %ebx /* Number of variable MTRRs */ -- To view, visit https://review.coreboot.org/28805 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: If71ab647f012a735c6aa6939463414407757ab9a Gerrit-Change-Number: 28805 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: UPSTREAM: mb/google/octopus: Bobba Touchpad I2C CLK (406.3KHz)over sp...
by Pan Sheng-Liang (Code Review) 04 Oct '18

04 Oct '18

Hello Sheng-Liang Pan, I'd like you to do a code review. Please visit https://review.coreboot.org/28907 to review the following change. Change subject: UPSTREAM: mb/google/octopus: Bobba Touchpad I2C CLK (406.3KHz)over spec(400KHz) ...................................................................... UPSTREAM: mb/google/octopus: Bobba Touchpad I2C CLK (406.3KHz)over spec(400KHz) Need to tune I2C bus 6 clock frequency under the 400KHz Bug=b:117126484 TEST=flash coreboot to the DUT and measure I2C bus 6 clock frequency whether arrive to 396.8KHz Change-Id: Icb9592c688b864a21efd4963a4463845dfaa06fb Signed-off-by: Pan Sheng-Liang <sheng-liang.pan(a)quanta.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/bobba/overridetree.cb 1 file changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/28907/1 diff --git a/src/mainboard/google/octopus/variants/bobba/overridetree.cb b/src/mainboard/google/octopus/variants/bobba/overridetree.cb index acb1d50..600aaed 100644 --- a/src/mainboard/google/octopus/variants/bobba/overridetree.cb +++ b/src/mainboard/google/octopus/variants/bobba/overridetree.cb @@ -1,5 +1,45 @@ chip soc/intel/apollolake + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C5 | Audio | + #| I2C6 | Trackpad | + #| I2C7 | Touchscreen | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 152, + .fall_time_ns = 30, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }, + .i2c[6] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + .i2c[7] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 76, + .fall_time_ns = 164, + }, + }" + device domain 0 on device pci 16.0 on chip drivers/i2c/hid -- To view, visit https://review.coreboot.org/28907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icb9592c688b864a21efd4963a4463845dfaa06fb Gerrit-Change-Number: 28907 Gerrit-PatchSet: 1 Gerrit-Owner: Pan Sheng-Liang <sl.pan.quantw(a)gmail.com> Gerrit-Reviewer: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com>

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coreboot-gerrit October 2018