coreboot-gerrit October 2018

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Change in coreboot[master]: Unify all Lenovo t520 variants
by Peter Lemenkov (Code Review) 05 Oct '18

05 Oct '18

Peter Lemenkov has posted comments on this change. ( https://review.coreboot.org/28936 ) Change subject: Unify all Lenovo t520 variants ...................................................................... Patch Set 2: > Build Failed > > https://qa.coreboot.org/job/coreboot-gerrit/80240/ : FAILURE > > https://qa.coreboot.org/job/coreboot-checkpatch/33914/ : SUCCESS Not sure if I understand it correctly: #!!!!! Error: #if CONFIG_BOARD_LENOVO_T520 used at src/mainboard/lenovo/t520/smihandler.c:36. IS_ENABLED should be used for type 'bool' #!!!!! Error: #if CONFIG_BOARD_LENOVO_T520 used at src/mainboard/lenovo/t520/smihandler.c:46. IS_ENABLED should be used for type 'bool' # 2 errors Isn't this actually a proper declaration of a bool variable? config BOARD_LENOVO_L520 bool "ThinkPad L520" select BOARD_LENOVO_BASEBOARD_T520 -- To view, visit https://review.coreboot.org/28936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I936ec6e51dc74637439d8562070443904071708c Gerrit-Change-Number: 28936 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 05 Oct 2018 14:16:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: nb/i945: Check if IGD is enabled before R/W to dev(0, 2)
by Nico Huber (Code Review) 05 Oct '18

05 Oct '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/28935 ) Change subject: nb/i945: Check if IGD is enabled before R/W to dev(0, 2) ...................................................................... Patch Set 1: I don't see a way IGD could be disabled at this stage. But what about SKUs that don't have it at all? are there any (on supported boards)? -- To view, visit https://review.coreboot.org/28935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I51ab94393710ce0222b353ab0cef28621fafaacf Gerrit-Change-Number: 28935 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 05 Oct 2018 13:45:25 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: Unify all Lenovo t520 variants
by Peter Lemenkov (Code Review) 05 Oct '18

05 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28936 to look at the new patch set (#2). Change subject: Unify all Lenovo t520 variants ...................................................................... Unify all Lenovo t520 variants It looks that L520 is almost the same as other two T520 variants. So let's remove duplicated code. The only difference between l520 and t520/w520 which i'm not sure is cmos.layout and cmos.defaults settings. Here is a diff: ============================ diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default index 979f132863..6e61dae340 100644 --- a/src/mainboard/lenovo/t520/cmos.default +++ b/src/mainboard/lenovo/t520/cmos.default @@ -13,4 +13,5 @@ fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable backlight=Both +hybrid_graphics_mode=Integrated Only usb_always_on=Disable diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout index 60292a401b..1a7943e5a4 100644 --- a/src/mainboard/lenovo/t520/cmos.layout +++ b/src/mainboard/lenovo/t520/cmos.layout @@ -68,7 +68,7 @@ entries 416 1 e 1 trackpoint 417 1 e 1 fn_ctrl_swap 418 1 e 1 sticky_fn -419 2 e 12 usb_always_on +419 2 e 13 usb_always_on 421 1 e 9 sata_mode 422 2 e 10 backlight @@ -77,7 +77,8 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused +435 2 e 12 hybrid_graphics_mode +#437 3 r 0 unused 440 8 h 0 volume # SandyBridge MRC Scrambler Seed values @@ -126,9 +127,12 @@ enumerations 11 4 160M 11 5 192M 11 6 224M -12 0 Disable -12 1 AC and battery -12 2 AC only +12 0 Integrated Only +12 1 Discrete Only +12 2 Dual Graphics +13 0 Disable +13 1 AC and battery +13 2 AC only # ----------------------------------------------------------------- checksums ============================ The only change from L520 is the addition of a hybrid graphics field (12) and change usb_always_on from this 12 to the next value, e.g. 13. I believe this is ok, since these numbers are used by Coreboot itself so any new L520 user will have the updated cmos mappings. In the mean time I'm going to unify more Lenovo (if anyone finds it interesting and valuable). Then I'll try to fix autoport utility accordingly. Change-Id: I936ec6e51dc74637439d8562070443904071708c Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- D src/mainboard/lenovo/l520/Kconfig D src/mainboard/lenovo/l520/Kconfig.name D src/mainboard/lenovo/l520/Makefile.inc D src/mainboard/lenovo/l520/acpi/ec.asl D src/mainboard/lenovo/l520/acpi/platform.asl D src/mainboard/lenovo/l520/acpi/superio.asl D src/mainboard/lenovo/l520/acpi_tables.c D src/mainboard/lenovo/l520/cmos.default D src/mainboard/lenovo/l520/cmos.layout D src/mainboard/lenovo/l520/dsdt.asl D src/mainboard/lenovo/l520/hda_verb.c D src/mainboard/lenovo/l520/mainboard.c D src/mainboard/lenovo/l520/smihandler.c D src/mainboard/lenovo/l520/thermal.h M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t520/Kconfig.name M src/mainboard/lenovo/t520/acpi/ec.asl M src/mainboard/lenovo/t520/acpi/platform.asl M src/mainboard/lenovo/t520/acpi/superio.asl M src/mainboard/lenovo/t520/acpi_tables.c M src/mainboard/lenovo/t520/dsdt.asl M src/mainboard/lenovo/t520/hda_verb.c M src/mainboard/lenovo/t520/mainboard.c M src/mainboard/lenovo/t520/smihandler.c M src/mainboard/lenovo/t520/thermal.h R src/mainboard/lenovo/t520/variants/l520/board_info.txt R src/mainboard/lenovo/t520/variants/l520/devicetree.cb R src/mainboard/lenovo/t520/variants/l520/gpio.c R src/mainboard/lenovo/t520/variants/l520/romstage.c 29 files changed, 151 insertions(+), 629 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/28936/2 -- To view, visit https://review.coreboot.org/28936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I936ec6e51dc74637439d8562070443904071708c Gerrit-Change-Number: 28936 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: Unify all Lenovo t520 variants
by build bot (Jenkins) (Code Review) 05 Oct '18

05 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28936 ) Change subject: Unify all Lenovo t520 variants ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28936/1/src/mainboard/lenovo/t520/hda_verb.c File src/mainboard/lenovo/t520/hda_verb.c: https://review.coreboot.org/#/c/28936/1/src/mainboard/lenovo/t520/hda_verb.… PS1, Line 38: #define CODEC_VENDOR_DEVICE_ID 0x14f1506e // Conexant CX20590 - Schematic shows CX20672 line over 80 characters -- To view, visit https://review.coreboot.org/28936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I936ec6e51dc74637439d8562070443904071708c Gerrit-Change-Number: 28936 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 05 Oct 2018 13:09:24 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: Unify all Lenovo t520 variants
by Peter Lemenkov (Code Review) 05 Oct '18

05 Oct '18

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/28936 Change subject: Unify all Lenovo t520 variants ...................................................................... Unify all Lenovo t520 variants It looks that L520 is almost the same as other two T520 variants. So let's remove duplicated code. The only difference between l520 and t520/w520 which i'm not sure is cmos.layout and cmos.defaults settings. Here is a diff: ============================ diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default index 979f132863..6e61dae340 100644 --- a/src/mainboard/lenovo/t520/cmos.default +++ b/src/mainboard/lenovo/t520/cmos.default @@ -13,4 +13,5 @@ fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable backlight=Both +hybrid_graphics_mode=Integrated Only usb_always_on=Disable diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout index 60292a401b..1a7943e5a4 100644 --- a/src/mainboard/lenovo/t520/cmos.layout +++ b/src/mainboard/lenovo/t520/cmos.layout @@ -68,7 +68,7 @@ entries 416 1 e 1 trackpoint 417 1 e 1 fn_ctrl_swap 418 1 e 1 sticky_fn -419 2 e 12 usb_always_on +419 2 e 13 usb_always_on 421 1 e 9 sata_mode 422 2 e 10 backlight @@ -77,7 +77,8 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused +435 2 e 12 hybrid_graphics_mode +#437 3 r 0 unused 440 8 h 0 volume # SandyBridge MRC Scrambler Seed values @@ -126,9 +127,12 @@ enumerations 11 4 160M 11 5 192M 11 6 224M -12 0 Disable -12 1 AC and battery -12 2 AC only +12 0 Integrated Only +12 1 Discrete Only +12 2 Dual Graphics +13 0 Disable +13 1 AC and battery +13 2 AC only # ----------------------------------------------------------------- checksums ============================ The only change from L520 is the addition of a hybrid graphics field (12) and change usb_always_on from this 12 to the next value, e.g. 13. I believe this is ok, since these numbers are used by Coreboot itself so any new L520 user will have the updated cmos mappings. In the mean time I'm going to unify more Lenovo (if anyone finds it interesting and valuable). Then I'll try to fix autoport utility accordingly. Change-Id: I936ec6e51dc74637439d8562070443904071708c Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- D src/mainboard/lenovo/l520/Kconfig D src/mainboard/lenovo/l520/Kconfig.name D src/mainboard/lenovo/l520/Makefile.inc D src/mainboard/lenovo/l520/acpi/ec.asl D src/mainboard/lenovo/l520/acpi/platform.asl D src/mainboard/lenovo/l520/acpi/superio.asl D src/mainboard/lenovo/l520/acpi_tables.c D src/mainboard/lenovo/l520/cmos.default D src/mainboard/lenovo/l520/cmos.layout D src/mainboard/lenovo/l520/dsdt.asl D src/mainboard/lenovo/l520/hda_verb.c D src/mainboard/lenovo/l520/mainboard.c D src/mainboard/lenovo/l520/smihandler.c D src/mainboard/lenovo/l520/thermal.h M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t520/Kconfig.name M src/mainboard/lenovo/t520/acpi/ec.asl M src/mainboard/lenovo/t520/acpi/platform.asl M src/mainboard/lenovo/t520/acpi/superio.asl M src/mainboard/lenovo/t520/acpi_tables.c M src/mainboard/lenovo/t520/dsdt.asl M src/mainboard/lenovo/t520/hda_verb.c M src/mainboard/lenovo/t520/mainboard.c M src/mainboard/lenovo/t520/smihandler.c M src/mainboard/lenovo/t520/thermal.h R src/mainboard/lenovo/t520/variants/l520/board_info.txt R src/mainboard/lenovo/t520/variants/l520/devicetree.cb R src/mainboard/lenovo/t520/variants/l520/gpio.c R src/mainboard/lenovo/t520/variants/l520/romstage.c 29 files changed, 150 insertions(+), 628 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/28936/1 diff --git a/src/mainboard/lenovo/l520/Kconfig b/src/mainboard/lenovo/l520/Kconfig deleted file mode 100644 index 05174c2..0000000 --- a/src/mainboard/lenovo/l520/Kconfig +++ /dev/null @@ -1,57 +0,0 @@ -if BOARD_LENOVO_L520 - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select BOARD_ROMSIZE_KB_4096 - select CPU_INTEL_SOCKET_RPGA989 - select EC_LENOVO_H8 - select EC_LENOVO_PMH7 - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select INTEL_INT15 - select HAVE_OPTION_TABLE - select HAVE_CMOS_DEFAULT - select NORTHBRIDGE_INTEL_SANDYBRIDGE - select SANDYBRIDGE_IVYBRIDGE_LVDS - select SERIRQ_CONTINUOUS_MODE - select SOUTHBRIDGE_INTEL_BD82X6X - select SYSTEM_TYPE_LAPTOP - select USE_NATIVE_RAMINIT - -config MAINBOARD_DIR - string - default lenovo/l520 - -config MAINBOARD_PART_NUMBER - string - default "ThinkPad L520" - -config VGA_BIOS_FILE - string - default "pci8086,0126.rom" - -config VGA_BIOS_ID - string - default "8086,0126" - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21dd - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config DRAM_RESET_GATE_GPIO - int - default 10 - -config MAX_CPUS - int - default 8 - -config USBDEBUG_HCD_INDEX - int - default 2 - -endif diff --git a/src/mainboard/lenovo/l520/Kconfig.name b/src/mainboard/lenovo/l520/Kconfig.name deleted file mode 100644 index c20cbda..0000000 --- a/src/mainboard/lenovo/l520/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_LENOVO_L520 - bool "ThinkPad L520" diff --git a/src/mainboard/lenovo/l520/Makefile.inc b/src/mainboard/lenovo/l520/Makefile.inc deleted file mode 100644 index 892c815..0000000 --- a/src/mainboard/lenovo/l520/Makefile.inc +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -romstage-y += romstage.c -romstage-y += gpio.c -ramstage-y += acpi_tables.c -smm-y += smihandler.c diff --git a/src/mainboard/lenovo/l520/acpi/ec.asl b/src/mainboard/lenovo/l520/acpi/ec.asl deleted file mode 100644 index 9b60a68..0000000 --- a/src/mainboard/lenovo/l520/acpi/ec.asl +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2016 Patrick Rudolph <siro(a)das-labor.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <ec/lenovo/h8/acpi/ec.asl> - -Scope(\_SB.PCI0.LPCB.EC) -{ -} diff --git a/src/mainboard/lenovo/l520/acpi/platform.asl b/src/mainboard/lenovo/l520/acpi/platform.asl deleted file mode 100644 index c7aea62..0000000 --- a/src/mainboard/lenovo/l520/acpi/platform.asl +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2016 Patrick Rudolph <siro(a)das-labor.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Method(_WAK,1) -{ - /* ME may not be up yet. */ - Store (0, \_TZ.MEB1) - Store (0, \_TZ.MEB2) - Return(Package(){0,0}) -} - -Method(_PTS,1) -{ - \_SB.PCI0.LPCB.EC.MUTE(1) - \_SB.PCI0.LPCB.EC.USBP(0) - \_SB.PCI0.LPCB.EC.RADI(0) -} diff --git a/src/mainboard/lenovo/l520/acpi/superio.asl b/src/mainboard/lenovo/l520/acpi/superio.asl deleted file mode 100644 index 7b69fda..0000000 --- a/src/mainboard/lenovo/l520/acpi/superio.asl +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2016 Patrick Rudolph <siro(a)das-labor.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/l520/acpi_tables.c b/src/mainboard/lenovo/l520/acpi_tables.c deleted file mode 100644 index b861864..0000000 --- a/src/mainboard/lenovo/l520/acpi_tables.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - -#include <southbridge/intel/bd82x6x/nvs.h> -#include "thermal.h" - -static void acpi_update_thermal_table(global_nvs_t *gnvs) -{ - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; -} - -void acpi_create_gnvs(global_nvs_t *gnvs) -{ - /* Disable USB ports in S3 by default */ - gnvs->s3u0 = 0; - gnvs->s3u1 = 0; - - /* Disable USB ports in S5 by default */ - gnvs->s5u0 = 0; - gnvs->s5u1 = 0; - - - // the lid is open by default. - gnvs->lids = 1; - - acpi_update_thermal_table(gnvs); -} diff --git a/src/mainboard/lenovo/l520/cmos.default b/src/mainboard/lenovo/l520/cmos.default deleted file mode 100644 index 979f132..0000000 --- a/src/mainboard/lenovo/l520/cmos.default +++ /dev/null @@ -1,16 +0,0 @@ -boot_option=Fallback -debug_level=Debug -power_on_after_fail=Disable -nmi=Enable -volume=0x3 -first_battery=Primary -bluetooth=Enable -wwan=Enable -wlan=Enable -touchpad=Enable -sata_mode=AHCI -fn_ctrl_swap=Disable -sticky_fn=Disable -trackpoint=Enable -backlight=Both -usb_always_on=Disable diff --git a/src/mainboard/lenovo/l520/cmos.layout b/src/mainboard/lenovo/l520/cmos.layout deleted file mode 100644 index 9faee06..0000000 --- a/src/mainboard/lenovo/l520/cmos.layout +++ /dev/null @@ -1,135 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2014 Vladimir Serbinenko -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -#392 3 r 0 unused -395 4 e 6 debug_level -#399 1 r 0 unused - -#400 8 r 0 reserved for century byte - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail - -# coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 2 e 12 usb_always_on -421 1 e 9 sata_mode -422 2 e 10 backlight - -# coreboot config options: cpu -#424 8 r 0 unused - -# coreboot config options: northbridge -432 3 e 11 gfx_uma_size -#435 5 r 0 unused -440 8 h 0 volume - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk - -# coreboot config options: check sums -984 16 h 0 check_sum - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Disable -12 1 AC and battery -12 2 AC only - -# ----------------------------------------------------------------- -checksums - -checksum 392 447 984 diff --git a/src/mainboard/lenovo/l520/dsdt.asl b/src/mainboard/lenovo/l520/dsdt.asl deleted file mode 100644 index 42a61fb..0000000 --- a/src/mainboard/lenovo/l520/dsdt.asl +++ /dev/null @@ -1,44 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB -#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB -#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 -#define EC_LENOVO_H8_ME_WORKAROUND 1 -#define THINKPAD_EC_GPE 22 -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x03, // DSDT revision: ACPI v3.0 - "COREv4", // OEM id - "COREBOOT", // OEM table id - 0x20141018 // OEM revision -) -{ - // Some generic macros - #include "acpi/platform.asl" - #include <cpu/intel/model_206ax/acpi/cpu.asl> - #include <southbridge/intel/bd82x6x/acpi/platform.asl> - /* global NVS and variables. */ - #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> - #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - #include <southbridge/intel/bd82x6x/acpi/pch.asl> - } - } -} diff --git a/src/mainboard/lenovo/l520/hda_verb.c b/src/mainboard/lenovo/l520/hda_verb.c deleted file mode 100644 index 30a4a61..0000000 --- a/src/mainboard/lenovo/l520/hda_verb.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/azalia_device.h> - -const u32 cim_verb_data[] = { - 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ - 0x17aa21de, /* Subsystem ID */ - - 0x0000000b, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ - AZALIA_SUBVENDOR(0x0, 0x17aa21de), - - /* NID 0x12. */ - AZALIA_PIN_CFG(0x0, 0x12, 0x99a30920), - - /* NID 0x14. */ - AZALIA_PIN_CFG(0x0, 0x14, 0x99130110), - - /* NID 0x17. */ - AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), - - /* NID 0x18. */ - AZALIA_PIN_CFG(0x0, 0x18, 0x03a11830), - - /* NID 0x19. */ - AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), - - /* NID 0x1a. */ - AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), - - /* NID 0x1b. */ - AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), - - /* NID 0x1d. */ - AZALIA_PIN_CFG(0x0, 0x1d, 0x40079a2d), - - /* NID 0x1e. */ - AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), - - /* NID 0x21. */ - AZALIA_PIN_CFG(0x0, 0x21, 0x0321101f), - 0x80862805, /* Codec Vendor / Device ID: Intel */ - 0x80860101, /* Subsystem ID */ - - 0x00000004, /* Number of 4 dword sets */ - /* NID 0x01: Subsystem ID. */ - AZALIA_SUBVENDOR(0x3, 0x80860101), - - /* NID 0x05. */ - AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), - - /* NID 0x06. */ - AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), - - /* NID 0x07. */ - AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), -}; - -const u32 pc_beep_verbs[0] = {}; - -AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/l520/mainboard.c b/src/mainboard/lenovo/l520/mainboard.c deleted file mode 100644 index db695b1..0000000 --- a/src/mainboard/lenovo/l520/mainboard.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <drivers/intel/gma/int15.h> -#include <ec/lenovo/h8/h8.h> - -static void mainboard_enable(struct device *dev) -{ - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, - GMA_INT15_PANEL_FIT_DEFAULT, - GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); -} - -void h8_mainboard_init_dock(void) -{ -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/lenovo/l520/smihandler.c b/src/mainboard/lenovo/l520/smihandler.c deleted file mode 100644 index fa038ed..0000000 --- a/src/mainboard/lenovo/l520/smihandler.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <cpu/x86/smm.h> -#include <ec/acpi/ec.h> -#include <ec/lenovo/h8/h8.h> -#include <southbridge/intel/common/pmutil.h> -#include <southbridge/intel/bd82x6x/pch.h> - -#define GPE_EC_SCI 6 -/* FIXME: check this */ -#define GPE_EC_WAKE 13 - -static void mainboard_smi_handle_ec_sci(void) -{ - u8 status = inb(EC_SC); - u8 event; - - if (!(status & EC_SCI_EVT)) - return; - - event = ec_query(); - printk(BIOS_DEBUG, "EC event %02x\n", event); -} - -void mainboard_smi_gpi(u32 gpi_sts) -{ - if (gpi_sts & (1 << GPE_EC_SCI)) - mainboard_smi_handle_ec_sci(); -} - -int mainboard_smi_apmc(u8 data) -{ - switch (data) { - case APM_CNT_ACPI_ENABLE: - /* use 0x1600/0x1604 to prevent races with userspace */ - ec_set_ports(0x1604, 0x1600); - /* route EC_SCI to SCI */ - gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); - /* discard all events, and enable attention */ - ec_write(0x80, 0x01); - break; - case APM_CNT_ACPI_DISABLE: - /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't - provide a EC query function */ - ec_set_ports(0x66, 0x62); - /* route EC_SCI to SMI */ - gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); - /* discard all events, and enable attention */ - ec_write(0x80, 0x01); - break; - default: - break; - } - return 0; -} - -void mainboard_smi_sleep(u8 slp_typ) -{ - h8_usb_always_on(); - - if (slp_typ == 3) { - u8 ec_wake = ec_read(0x32); - /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ - if (ec_wake & 0x14) { - /* Redirect EC WAKE GPE to SCI. */ - gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); - } - } -} diff --git a/src/mainboard/lenovo/l520/thermal.h b/src/mainboard/lenovo/l520/thermal.h deleted file mode 100644 index a2007ff..0000000 --- a/src/mainboard/lenovo/l520/thermal.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef L520_THERMAL_H -#define L520_THERMAL_H - - /* Temperature which OS will shutdown at */ - #define CRITICAL_TEMPERATURE 100 - - /* Temperature which OS will throttle CPU */ - #define PASSIVE_TEMPERATURE 90 - -#endif /* L520_THERMAL_H */ diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 79455e2..d435d3c 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -1,13 +1,14 @@ config BOARD_LENOVO_BASEBOARD_T520 def_bool n select SYSTEM_TYPE_LAPTOP - select CPU_INTEL_SOCKET_RPGA988B + select CPU_INTEL_SOCKET_RPGA988B if BOARD_LENOVO_T520 || BOARD_LENOVO_W520 + select CPU_INTEL_SOCKET_RPGA989 if BOARD_LENOVO_L520 select NORTHBRIDGE_INTEL_SANDYBRIDGE select USE_NATIVE_RAMINIT select SOUTHBRIDGE_INTEL_BD82X6X select EC_LENOVO_PMH7 select EC_LENOVO_H8 - select NO_UART_ON_SUPERIO + select NO_UART_ON_SUPERIO if BOARD_LENOVO_T520 || BOARD_LENOVO_W520 select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE @@ -15,10 +16,10 @@ select HAVE_ACPI_RESUME select INTEL_INT15 select SANDYBRIDGE_IVYBRIDGE_LVDS - select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_HAS_LPC_TPM - select MAINBOARD_HAS_TPM1 - select DRIVERS_LENOVO_HYBRID_GRAPHICS + select MAINBOARD_HAS_LIBGFXINIT if BOARD_LENOVO_T520 || BOARD_LENOVO_W520 + select MAINBOARD_HAS_LPC_TPM if BOARD_LENOVO_T520 || BOARD_LENOVO_W520 + select MAINBOARD_HAS_TPM1 if BOARD_LENOVO_T520 || BOARD_LENOVO_W520 + select DRIVERS_LENOVO_HYBRID_GRAPHICS if BOARD_LENOVO_T520 || BOARD_LENOVO_W520 select INTEL_GMA_HAVE_VBT if BOARD_LENOVO_T520 # Workaround for EC/KBC IRQ1. @@ -28,6 +29,7 @@ config VARIANT_DIR string + default "l520" if BOARD_LENOVO_L520 default "t520" if BOARD_LENOVO_T520 default "w520" if BOARD_LENOVO_W520 @@ -37,11 +39,13 @@ config DEVICETREE string + default "variants/l520/devicetree.cb" if BOARD_LENOVO_L520 default "variants/t520/devicetree.cb" if BOARD_LENOVO_T520 default "variants/w520/devicetree.cb" if BOARD_LENOVO_W520 config MAINBOARD_PART_NUMBER string + default "ThinkPad L520" if BOARD_LENOVO_L520 default "ThinkPad T520" if BOARD_LENOVO_T520 default "ThinkPad W520" if BOARD_LENOVO_W520 @@ -71,10 +75,33 @@ config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex - default 0x21cf + default 0x21dd if BOARD_LENOVO_L520 + default 0x21cf if BOARD_LENOVO_T520 || BOARD_LENOVO_W520 config ONBOARD_VGA_IS_PRIMARY bool default y +config EC_GPE_ID + int + default 22 if BOARD_LENOVO_L520 + default 17 if BOARD_LENOVO_T520 || BOARD_LENOVO_W520 + +config EC_GPE_SCI_ID + int + default 6 if BOARD_LENOVO_L520 + default 1 if BOARD_LENOVO_T520 || BOARD_LENOVO_W520 + +config DSDT_REVISION + hex + # ACPI v3.0 + default 0x03 if BOARD_LENOVO_L520 + # ACPI v2.0 + default 0x02 if BOARD_LENOVO_T520 || BOARD_LENOVO_W520 + +config OEM_REVISION + hex + default 0x20141018 if BOARD_LENOVO_L520 + default 0x20110725 if BOARD_LENOVO_T520 || BOARD_LENOVO_W520 + endif diff --git a/src/mainboard/lenovo/t520/Kconfig.name b/src/mainboard/lenovo/t520/Kconfig.name index cc622f0..41ef90f 100644 --- a/src/mainboard/lenovo/t520/Kconfig.name +++ b/src/mainboard/lenovo/t520/Kconfig.name @@ -1,3 +1,7 @@ +config BOARD_LENOVO_L520 + bool "ThinkPad L520" + select BOARD_LENOVO_BASEBOARD_T520 + config BOARD_LENOVO_T520 bool "ThinkPad T520" select BOARD_LENOVO_BASEBOARD_T520 diff --git a/src/mainboard/lenovo/t520/acpi/ec.asl b/src/mainboard/lenovo/t520/acpi/ec.asl index d631f12..f10f855 100644 --- a/src/mainboard/lenovo/t520/acpi/ec.asl +++ b/src/mainboard/lenovo/t520/acpi/ec.asl @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * Copyright (c) 2016 Patrick Rudolph <siro(a)das-labor.org> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/src/mainboard/lenovo/t520/acpi/platform.asl b/src/mainboard/lenovo/t520/acpi/platform.asl index e4c8a24..3a43f1c 100644 --- a/src/mainboard/lenovo/t520/acpi/platform.asl +++ b/src/mainboard/lenovo/t520/acpi/platform.asl @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. + * Copyright (c) 2016 Patrick Rudolph <siro(a)das-labor.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -32,8 +33,10 @@ Store (0, \_TZ.MEB1) Store (0, \_TZ.MEB2) +#if !IS_ENABLED(CONFIG_BOARD_LENOVO_L520) /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) +#endif /* Not implemented. */ Return(Package(){0,0}) diff --git a/src/mainboard/lenovo/t520/acpi/superio.asl b/src/mainboard/lenovo/t520/acpi/superio.asl index f2b35ba..7b69fda 100644 --- a/src/mainboard/lenovo/t520/acpi/superio.asl +++ b/src/mainboard/lenovo/t520/acpi/superio.asl @@ -1 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/t520/acpi_tables.c b/src/mainboard/lenovo/t520/acpi_tables.c index a3b0894..ffbd3c9 100644 --- a/src/mainboard/lenovo/t520/acpi_tables.c +++ b/src/mainboard/lenovo/t520/acpi_tables.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl index 7db8344..44ef7b9 100644 --- a/src/mainboard/lenovo/t520/dsdt.asl +++ b/src/mainboard/lenovo/t520/dsdt.asl @@ -15,7 +15,7 @@ * GNU General Public License for more details. */ -#define THINKPAD_EC_GPE 17 +#define THINKPAD_EC_GPE CONFIG_EC_GPE_ID #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 @@ -24,10 +24,10 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 + CONFIG_DSDT_REVISION, // DSDT revision: ACPI v2.0 "COREv4", // OEM id "COREBOOT", // OEM table id - 0x20110725 // OEM revision + CONFIG_OEM_REVISION, // OEM revision ) { #include <southbridge/intel/bd82x6x/acpi/platform.asl> diff --git a/src/mainboard/lenovo/t520/hda_verb.c b/src/mainboard/lenovo/t520/hda_verb.c index dae692d..0636ae9 100644 --- a/src/mainboard/lenovo/t520/hda_verb.c +++ b/src/mainboard/lenovo/t520/hda_verb.c @@ -1,8 +1,10 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -14,29 +16,92 @@ * GNU General Public License for more details. */ -/* Vendor Name : Conexant +/* L520 + * Vendor Name : Realtek + * Vendor ID : 0x10ec0269 + * Subsystem ID : 0x17aa21de + * Revision ID : ? + */ + +/* T520 / W520 + * Vendor Name : Conexant * Vendor ID : 0x14f1506e * Subsystem ID : 0x17aa21cf * Revision ID : 0x100000 */ +#ifdef CONFIG_BOARD_LENOVO_L520 +#define CODEC_VENDOR_DEVICE_ID 0x10ec0269 +#define CODEC_SUBSYSTEM_ID 0x17aa21de +#define CODEC_DATA_SETS_NUMBER 0x0000000b +#else +#define CODEC_VENDOR_DEVICE_ID 0x14f1506e // Conexant CX20590 - Schematic shows CX20672 +#define CODEC_SUBSYSTEM_ID 0x17aa21cf +#define CODEC_DATA_SETS_NUMBER 0x0000000d +#endif #include <device/azalia_device.h> const u32 cim_verb_data[] = { /* coreboot specific header */ - 0x14f1506e, // Codec Vendor / Device ID: Conexant CX20590 - Schematic shows CX20672 - 0x17aa21cf, // Subsystem ID - 0x0000000d, // Number of 4 dword sets + CODEC_VENDOR_DEVICE_ID, + CODEC_SUBSYSTEM_ID, // Subsystem ID + CODEC_DATA_SETS_NUMBER, // Number of 4 dword sets /* Bits 31:28 - Codec Address */ /* Bits 27:20 - NID */ /* Bits 19:8 - Verb ID */ /* Bits 7:0 - Payload */ -/* NID 0x01 - NodeInfo */ - AZALIA_SUBVENDOR(0x0, 0x17AA21CF), + /* NID 0x01 - Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, CODEC_SUBSYSTEM_ID), +#ifdef CONFIG_BOARD_LENOVO_L520 + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x99a30920), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x99130110), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x03a11830), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x40079a2d), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + + /* NID 0x21. */ + AZALIA_PIN_CFG(0x0, 0x21, 0x0321101f), + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), +#else AZALIA_PIN_CFG(0x0, 0x19, 0x04211040), AZALIA_PIN_CFG(0x0, 0x1A, 0x61A19050), AZALIA_PIN_CFG(0x0, 0x1B, 0x04A11060), @@ -60,10 +125,14 @@ 0x00170500, /* Set power state to D0 */ 0x00170500, /* Padding */ 0x00170500, /* Padding */ +#endif }; const u32 pc_beep_verbs[] = { +#ifdef CONFIG_BOARD_LENOVO_L520 +#else 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ +#endif }; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/t520/mainboard.c b/src/mainboard/lenovo/t520/mainboard.c index bd4292a..1ac7052 100644 --- a/src/mainboard/lenovo/t520/mainboard.c +++ b/src/mainboard/lenovo/t520/mainboard.c @@ -4,6 +4,7 @@ * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2011-2012 Google Inc. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/t520/smihandler.c b/src/mainboard/lenovo/t520/smihandler.c index 4e61a98..fe7e845 100644 --- a/src/mainboard/lenovo/t520/smihandler.c +++ b/src/mainboard/lenovo/t520/smihandler.c @@ -28,24 +28,28 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> -#define GPE_EC_SCI 1 +/* FIXME: check this for L520 */ #define GPE_EC_WAKE 13 static void mainboard_smi_brightness_up(void) { +#if CONFIG_BOARD_LENOVO_T520 || CONFIG_BOARD_LENOVO_W520 u8 value; if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0) pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf); +#endif } static void mainboard_smi_brightness_down(void) { +#if CONFIG_BOARD_LENOVO_T520 || CONFIG_BOARD_LENOVO_W520 u8 value; if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10) pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value - 0x10) & 0xf0); +#endif } static void mainboard_smi_handle_ec_sci(void) @@ -75,7 +79,7 @@ void mainboard_smi_gpi(u32 gpi_sts) { - if (gpi_sts & (1 << GPE_EC_SCI)) + if (gpi_sts & (1 << CONFIG_EC_GPE_SCI_ID)) mainboard_smi_handle_ec_sci(); } @@ -86,7 +90,7 @@ /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route EC_SCI to SCI */ - gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + gpi_route_interrupt(CONFIG_EC_GPE_SCI_ID, GPI_IS_SCI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; @@ -95,7 +99,7 @@ provide a EC query function */ ec_set_ports(0x66, 0x62); /* route EC_SCI to SMI */ - gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + gpi_route_interrupt(CONFIG_EC_GPE_SCI_ID, GPI_IS_SMI); /* discard all events, and enable attention */ ec_write(0x80, 0x01); break; diff --git a/src/mainboard/lenovo/t520/thermal.h b/src/mainboard/lenovo/t520/thermal.h index 60721bf..2e4a9e2 100644 --- a/src/mainboard/lenovo/t520/thermal.h +++ b/src/mainboard/lenovo/t520/thermal.h @@ -1,8 +1,10 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/src/mainboard/lenovo/l520/board_info.txt b/src/mainboard/lenovo/t520/variants/l520/board_info.txt similarity index 70% rename from src/mainboard/lenovo/l520/board_info.txt rename to src/mainboard/lenovo/t520/variants/l520/board_info.txt index f48c92b..16aba1f 100644 --- a/src/mainboard/lenovo/l520/board_info.txt +++ b/src/mainboard/lenovo/t520/variants/l520/board_info.txt @@ -1,3 +1,5 @@ +Vendor name: Lenovo +Board name: ThinkPad L520 Category: laptop ROM package: SOIC-8 ROM protocol: SPI diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/t520/variants/l520/devicetree.cb similarity index 100% rename from src/mainboard/lenovo/l520/devicetree.cb rename to src/mainboard/lenovo/t520/variants/l520/devicetree.cb diff --git a/src/mainboard/lenovo/l520/gpio.c b/src/mainboard/lenovo/t520/variants/l520/gpio.c similarity index 100% rename from src/mainboard/lenovo/l520/gpio.c rename to src/mainboard/lenovo/t520/variants/l520/gpio.c diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/t520/variants/l520/romstage.c similarity index 100% rename from src/mainboard/lenovo/l520/romstage.c rename to src/mainboard/lenovo/t520/variants/l520/romstage.c -- To view, visit https://review.coreboot.org/28936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I936ec6e51dc74637439d8562070443904071708c Gerrit-Change-Number: 28936 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com>

1 0

Change in coreboot[master]: nb/i945: Check if IGD is enabled before R/W to dev(0, 2)
by Elyes HAOUAS (Code Review) 05 Oct '18

05 Oct '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28935 Change subject: nb/i945: Check if IGD is enabled before R/W to dev(0, 2) ...................................................................... nb/i945: Check if IGD is enabled before R/W to dev(0, 2) Change-Id: I51ab94393710ce0222b353ab0cef28621fafaacf Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 12 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/28935/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index c259530..e95dda0 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2148,7 +2148,7 @@ u8 reg8; u16 reg16; u32 reg32; - int integrated_graphics = 1; + int integrated_graphics = 0; int i; reg32 = MCHBAR32(C0DRT2); @@ -2292,9 +2292,13 @@ reg8 |= (1 << 4); pci_write_config8(PCI_DEV(0, 0x0, 0), 0xfc, reg8); - reg8 = pci_read_config8(PCI_DEV(0, 0x2, 0), 0xc1); - reg8 |= (1 << 2); - pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8); + if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & + (DEVEN_D2F0 | DEVEN_D2F1)) { + integrated_graphics = 1; + reg8 = pci_read_config8(PCI_DEV(0, 0x2, 0), 0xc1); + reg8 |= (1 << 2); + pci_write_config8(PCI_DEV(0, 0x2, 0), 0xc1, reg8); + } #ifdef C2_SELF_REFRESH_DISABLE @@ -2755,10 +2759,12 @@ * Program Graphics Frequency * Set core display and render clock on 945GC to the max */ - if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { sdram_program_graphics_frequency(&sysinfo); - else + } else if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & + (DEVEN_D2F0 | DEVEN_D2F1)) { pci_write_config16(PCI_DEV(0, 2, 0), GCFC, 0x0534); + } /* Program System Memory Frequency */ sdram_program_memory_frequency(&sysinfo); -- To view, visit https://review.coreboot.org/28935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I51ab94393710ce0222b353ab0cef28621fafaacf Gerrit-Change-Number: 28935 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

1 0

Change in coreboot[master]: src: Use tabs for code indent
by build bot (Jenkins) (Code Review) 05 Oct '18

05 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28934 ) Change subject: src: Use tabs for code indent ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/#/c/28934/4/src/soc/qualcomm/ipq806x/gpio.c File src/soc/qualcomm/ipq806x/gpio.c: https://review.coreboot.org/#/c/28934/4/src/soc/qualcomm/ipq806x/gpio.c@66 PS4, Line 66: unsigned val = 0; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/28934/4/src/soc/qualcomm/ipq806x/gpio.c@96 PS4, Line 96: unsigned val; Prefer 'unsigned int' to bare use of 'unsigned' -- To view, visit https://review.coreboot.org/28934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba Gerrit-Change-Number: 28934 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 05 Oct 2018 09:39:32 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: src: Use tabs for code indent
by Elyes HAOUAS (Code Review) 05 Oct '18

05 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28934 to look at the new patch set (#4). Change subject: src: Use tabs for code indent ...................................................................... src: Use tabs for code indent Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/hypertransport.c M src/drivers/i2c/at24rf08c/at24rf08c.c M src/drivers/i2c/at24rf08c/lenovo_serials.c M src/drivers/intel/gma/int15.c M src/drivers/intel/gma/intel_bios.h M src/drivers/intel/wifi/wifi.c M src/drivers/vpd/lib_vpd.h M src/ec/roda/it8518/acpi/ec.asl M src/ec/smsc/mec1308/acpi/ec.asl M src/northbridge/amd/amdfam10/amdfam10_util.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/via/vx900/lpc.c M src/soc/imgtec/pistachio/bootblock.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/nhlt.c M src/soc/intel/baytrail/gpio.c M src/soc/intel/baytrail/pmutil.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/cannonlake/cbmem.c M src/soc/intel/cannonlake/nhlt.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/fsp_baytrail/gpio.c M src/soc/intel/skylake/acpi/dptf/thermal.asl M src/soc/intel/skylake/acpi/xhci.asl M src/soc/intel/skylake/nhlt/max98373.c M src/soc/mediatek/mt8173/dramc_pi_basic_api.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/mediatek/mt8173/mt6391.c M src/soc/nvidia/tegra/i2c.c M src/soc/nvidia/tegra124/chip.h M src/soc/nvidia/tegra124/display.c M src/soc/nvidia/tegra124/dp.c M src/soc/nvidia/tegra210/dc.c M src/soc/nvidia/tegra210/dsi.c M src/soc/nvidia/tegra210/romstage_asm.S M src/soc/nvidia/tegra210/stack.S M src/soc/qualcomm/ipq40xx/spi.c M src/soc/qualcomm/ipq806x/gpio.c M src/soc/samsung/exynos5420/clock_init.c M src/soc/samsung/exynos5420/fimd.c M src/southbridge/intel/bd82x6x/acpi/platform.asl M src/southbridge/intel/bd82x6x/acpi/usb.asl M src/southbridge/intel/lynxpoint/early_pch.c 44 files changed, 146 insertions(+), 146 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/28934/4 -- To view, visit https://review.coreboot.org/28934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba Gerrit-Change-Number: 28934 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: src: Use tabs for code indent
by build bot (Jenkins) (Code Review) 05 Oct '18

05 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28934 ) Change subject: src: Use tabs for code indent ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/28934/3/src/soc/qualcomm/ipq806x/gpio.c File src/soc/qualcomm/ipq806x/gpio.c: https://review.coreboot.org/#/c/28934/3/src/soc/qualcomm/ipq806x/gpio.c@66 PS3, Line 66: unsigned val = 0; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/28934/3/src/soc/qualcomm/ipq806x/gpio.c@96 PS3, Line 96: unsigned val; Prefer 'unsigned int' to bare use of 'unsigned' -- To view, visit https://review.coreboot.org/28934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba Gerrit-Change-Number: 28934 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 05 Oct 2018 09:35:19 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: src: Use tabs for code indent
by Elyes HAOUAS (Code Review) 05 Oct '18

05 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28934 to look at the new patch set (#3). Change subject: src: Use tabs for code indent ...................................................................... src: Use tabs for code indent Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/hypertransport.c M src/drivers/i2c/at24rf08c/at24rf08c.c M src/drivers/i2c/at24rf08c/lenovo_serials.c M src/drivers/intel/gma/int15.c M src/drivers/intel/gma/intel_bios.h M src/drivers/intel/wifi/wifi.c M src/drivers/vpd/lib_vpd.h M src/ec/roda/it8518/acpi/ec.asl M src/ec/smsc/mec1308/acpi/ec.asl M src/northbridge/amd/amdfam10/amdfam10_util.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/via/vx900/lpc.c M src/soc/imgtec/pistachio/bootblock.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/nhlt.c M src/soc/intel/baytrail/gpio.c M src/soc/intel/baytrail/pmutil.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/cannonlake/cbmem.c M src/soc/intel/cannonlake/nhlt.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/fsp_baytrail/gpio.c M src/soc/intel/skylake/acpi/dptf/thermal.asl M src/soc/intel/skylake/acpi/xhci.asl M src/soc/intel/skylake/nhlt/max98373.c M src/soc/mediatek/mt8173/dramc_pi_basic_api.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/mediatek/mt8173/mt6391.c M src/soc/nvidia/tegra/i2c.c M src/soc/nvidia/tegra124/chip.h M src/soc/nvidia/tegra124/display.c M src/soc/nvidia/tegra124/dp.c M src/soc/nvidia/tegra210/dc.c M src/soc/nvidia/tegra210/dsi.c M src/soc/nvidia/tegra210/romstage_asm.S M src/soc/nvidia/tegra210/stack.S M src/soc/qualcomm/ipq806x/gpio.c M src/soc/samsung/exynos5420/clock_init.c M src/soc/samsung/exynos5420/fimd.c M src/southbridge/intel/bd82x6x/acpi/platform.asl M src/southbridge/intel/bd82x6x/acpi/usb.asl M src/southbridge/intel/lynxpoint/early_pch.c 43 files changed, 145 insertions(+), 145 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/28934/3 -- To view, visit https://review.coreboot.org/28934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6b40aaf5af5d114bbb0cd227dfd50b0ee19eebba Gerrit-Change-Number: 28934 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit October 2018