coreboot-gerrit October 2018

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Change in coreboot[master]: soc/intel/skylake: Fix ‘dev’ pointer NULL before being dereferenced
by Subrata Banik (Code Review) 06 Oct '18

06 Oct '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/28948 Change subject: soc/intel/skylake: Fix ‘dev’ pointer NULL before being dereferenced ...................................................................... soc/intel/skylake: Fix ‘dev’ pointer NULL before being dereferenced This patch fixes KW issue due to pointer being NULL and will be dereferenced Change-Id: Iedb59daf5f448e31c0097873a086e4d08cd4a979 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/thermal.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/28948/1 diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 3733fe0..2adbc26 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -290,6 +290,8 @@ static void configure_misc(void) { struct device *dev = SA_DEV_ROOT; + if (!dev) + return; config_t *conf = dev->chip_info; msr_t msr; diff --git a/src/soc/intel/skylake/thermal.c b/src/soc/intel/skylake/thermal.c index 01a4f26..aeeebe1 100644 --- a/src/soc/intel/skylake/thermal.c +++ b/src/soc/intel/skylake/thermal.c @@ -83,6 +83,8 @@ { uint16_t reg16; struct device *dev = PCH_DEV_THERMAL; + if (!dev) + return; void *thermalbar = pch_thermal_get_bar(dev); /* Use default pre-ram bar */ -- To view, visit https://review.coreboot.org/28948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iedb59daf5f448e31c0097873a086e4d08cd4a979 Gerrit-Change-Number: 28948 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Disable Legacy PME for Root ports
by Subrata Banik (Code Review) 06 Oct '18

06 Oct '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/28947 Change subject: soc/intel/cannonlake: Disable Legacy PME for Root ports ...................................................................... soc/intel/cannonlake: Disable Legacy PME for Root ports Legacy PME are enabled by default in FSP-S UPD. This patch to override root port legacy pme upd policy from coreboot. BUG=b:113083354 BRANCH=none TEST=Able to make S3 resume using wake on wifi connect/disconnect usecase Change-Id: I779fac711eeeed65ea379fad1cc400052d8a00eb Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/28947/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index cbc97b2..d5233ed 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -129,6 +129,9 @@ /* S0ix */ params->PchPmSlpS0Enable = config->s0ix_enable; + /* disable Legacy PME */ + memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); + /* USB */ for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { params->PortUsb20Enable[i] = config->usb2_ports[i].enable; -- To view, visit https://review.coreboot.org/28947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I779fac711eeeed65ea379fad1cc400052d8a00eb Gerrit-Change-Number: 28947 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in em100[master]: em100: Increase maximum ROM size to 64MB
by Ryan O'Leary (Code Review) 06 Oct '18

06 Oct '18

Ryan O'Leary has uploaded this change for review. ( https://review.coreboot.org/28945 Change subject: em100: Increase maximum ROM size to 64MB ...................................................................... em100: Increase maximum ROM size to 64MB The previous maximum ROM size was 16MB. This is necessary to use em100 for emulating flash parts larger than 16MB, but I do not make any promise that all flash parts larger than 16MB will work. Change-Id: I94385eb9a46853e50550aa43aaa4822f24a0b095 Signed-off-by: Ryan O'Leary <ryanoleary(a)google.com> --- M em100.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/45/28945/1 diff --git a/em100.c b/em100.c index d4c215a..4673266 100644 --- a/em100.c +++ b/em100.c @@ -748,8 +748,8 @@ } if (read_filename) { - /* largest size - 16MB */ - int maxlen = desiredchip ? chip->size : 0x1000000; + /* largest size - 64MB */ + int maxlen = desiredchip ? chip->size : 0x4000000; void *data = malloc(maxlen); if (data == NULL) { printf("FATAL: couldn't allocate memory\n"); @@ -775,7 +775,7 @@ } if (filename) { - int maxlen = 0x1000000; /* largest size - 16MB */ + int maxlen = 0x4000000; /* largest size - 64MB */ void *data = malloc(maxlen); if (data == NULL) { printf("FATAL: couldn't allocate memory\n"); -- To view, visit https://review.coreboot.org/28945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I94385eb9a46853e50550aa43aaa4822f24a0b095 Gerrit-Change-Number: 28945 Gerrit-PatchSet: 1 Gerrit-Owner: Ryan O'Leary (1002134)

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Change in coreboot[master]: nb/i945: Check if IGD is enabled before R/W to dev(0, 2)
by Nico Huber (Code Review) 05 Oct '18

05 Oct '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/28935 ) Change subject: nb/i945: Check if IGD is enabled before R/W to dev(0, 2) ...................................................................... Patch Set 1: Code-Review-1 > so let give a sense to "integrated_graphics" and set it to 1 if IGD > is enabled. We can not just make the meaning up. If you have any other reference (e.g. serialice log, datasheet, ...) than your guessed meaning of `integrated_graphics` please tell so. If not, please don't touch this code. -- To view, visit https://review.coreboot.org/28935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I51ab94393710ce0222b353ab0cef28621fafaacf Gerrit-Change-Number: 28935 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 05 Oct 2018 20:36:29 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/common/block/gpio: check for NULL using if statement
by Bora Guvendik (Code Review) 05 Oct '18

05 Oct '18

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/28940 Change subject: soc/intel/common/block/gpio: check for NULL using if statement ...................................................................... soc/intel/common/block/gpio: check for NULL using if statement Remove assert() and instead use if statement to check if comm->groups is NULL. Found-by: klockwork BUG=None TEST=Boot to OS Change-Id: I85a6bc700b52d04c61ca8f2baac62000f40cf2cb Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/common/block/gpio/gpio.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/28940/1 diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 931fb7f..38d846c 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -73,7 +73,10 @@ { size_t i; - assert(comm->groups != NULL); + if (!comm->groups) { + printk(BIOS_ERR, "%s: Failed to get comm->groups\n", __func__); + return 0; + } /* find the base pad number for this pad's group */ for (i = 0; i < comm->num_groups; i++) { -- To view, visit https://review.coreboot.org/28940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I85a6bc700b52d04c61ca8f2baac62000f40cf2cb Gerrit-Change-Number: 28940 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Add back PM TIMER EMULATION
by Elyes HAOUAS (Code Review) 05 Oct '18

05 Oct '18

Elyes HAOUAS has posted comments on this change. ( https://review.coreboot.org/28937 ) Change subject: soc/intel/cannonlake: Add back PM TIMER EMULATION ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28937/2/src/soc/intel/cannonlake/cpu.c File src/soc/intel/cannonlake/cpu.c: https://review.coreboot.org/#/c/28937/2/src/soc/intel/cannonlake/cpu.c@187 PS2, Line 187: MSR_EMULATE_PM_TMR This is defined here soc/intel/common/block/include/intelblocks/msr.h, but also we have it here : src/soc/intel/skylake/include/soc/msr.h as "MSR_EMULATE_PM_TIMER" and we cab see also "EMULATE_DELAY_VALUE" ... Maybe we can fix the name and move this msr and linked registers bit to "soc/intel/common/block/include/intelblocks/msr.h" ? -- To view, visit https://review.coreboot.org/28937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie069e815e6244c3f85fabf51e186311621d316fd Gerrit-Change-Number: 28937 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Comment-Date: Fri, 05 Oct 2018 19:26:39 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/skylake: Set PCIEXPWAK_DIS if WAKE# pin is not enabled
by Furquan Shaikh (Code Review) 05 Oct '18

05 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28939 to look at the new patch set (#3). Change subject: soc/intel/skylake: Set PCIEXPWAK_DIS if WAKE# pin is not enabled ...................................................................... soc/intel/skylake: Set PCIEXPWAK_DIS if WAKE# pin is not enabled This change sets PCIEXPWAK_DIS in PM1_EN register if WAKE# pin is not enabled on the platform. This is required to prevent unnecessary wakes if the WAKE# pin remains not connected on the platform. BUG=b:117284700 TEST=Verified that no spurious wakes are observed on nocturne. Change-Id: Iea93baffc9bb703c0ffedacafc6a9a9410c7ebfe Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/skylake/cpu.c 1 file changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/28939/3 -- To view, visit https://review.coreboot.org/28939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iea93baffc9bb703c0ffedacafc6a9a9410c7ebfe Gerrit-Change-Number: 28939 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/cannonlake: Add back PM TIMER EMULATION
by Lijian Zhao (Code Review) 05 Oct '18

05 Oct '18

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/28937 ) Change subject: soc/intel/cannonlake: Add back PM TIMER EMULATION ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28937/2/src/soc/intel/cannonlake/include/so… File src/soc/intel/cannonlake/include/soc/msr.h: https://review.coreboot.org/#/c/28937/2/src/soc/intel/cannonlake/include/so… PS2, Line 24: > is this extra space? Usually people have an extra space to differentiate a whole register and register bit under, I can take that out to avoid confusion. -- To view, visit https://review.coreboot.org/28937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie069e815e6244c3f85fabf51e186311621d316fd Gerrit-Change-Number: 28937 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Comment-Date: Fri, 05 Oct 2018 18:59:58 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/skylake: Set PCIEXPWAK_DIS if WAKE# pin is not enabled
by Furquan Shaikh (Code Review) 05 Oct '18

05 Oct '18

Furquan Shaikh has uploaded a new patch set (#2). ( https://review.coreboot.org/28939 ) Change subject: soc/intel/skylake: Set PCIEXPWAK_DIS if WAKE# pin is not enabled ...................................................................... soc/intel/skylake: Set PCIEXPWAK_DIS if WAKE# pin is not enabled This change sets PCIEXPWAK_DIS in PM1_EN register if WAKE# pin is not enabled on the platform. This is required to prevent unnecessary wakes if the WAKE# pin remains not connected on the platform. BUG=b:117284700 TEST=Verified that no spurious wakes are observed on nocturne. Change-Id: Iea93baffc9bb703c0ffedacafc6a9a9410c7ebfe Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/skylake/cpu.c 1 file changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/28939/2 -- To view, visit https://review.coreboot.org/28939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iea93baffc9bb703c0ffedacafc6a9a9410c7ebfe Gerrit-Change-Number: 28939 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/skylake: Set PCIEXPWAK_DIS if WAKE# pin is not enabled
by Furquan Shaikh (Code Review) 05 Oct '18

05 Oct '18

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/28939 Change subject: soc/intel/skylake: Set PCIEXPWAK_DIS if WAKE# pin is not enabled ...................................................................... soc/intel/skylake: Set PCIEXPWAK_DIS if WAKE# pin is not enabled This change sets PCIEXPWAK_DIS in PM1_EN register if WAKE# pin is not enabled on the platform. This is required to prevent unnecessary wakes if the WAKE# pin remains not connected on the platform. BUG=b:117284700 TEST=Verified that no spurious wakes are observed on nocturne. Change-Id: Iea93baffc9bb703c0ffedacafc6a9a9410c7ebfe Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/skylake/cpu.c 1 file changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/28939/1 diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 417c4bc..925b694 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -466,14 +466,26 @@ static void post_mp_init(void) { + struct device *dev = SA_DEV_ROOT; + config_t *conf; + uint16_t pm1_en = GBL_EN; + /* Set Max Ratio */ cpu_set_max_ratio(); + if (dev && dev->chip_info) { + conf = dev->chip_info; + if (!(conf->deep_sx_config & DSX_EN_WAKE_PIN)) { + printk(BIOS_INFO, "Setting PCI Express Wake Disable.\n"); + pm1_en |= PCIEXPWAK_DIS; + } + } + /* * Now that all APs have been relocated as well as the BSP let SMIs * start flowing. */ - smm_southbridge_enable(GBL_EN); + smm_southbridge_enable(pm1_en); /* Lock down the SMRAM space. */ #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) -- To view, visit https://review.coreboot.org/28939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iea93baffc9bb703c0ffedacafc6a9a9410c7ebfe Gerrit-Change-Number: 28939 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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coreboot-gerrit October 2018