coreboot-gerrit October 2018

coreboot-gerrit@coreboot.org

1 participants
1285 discussions

Change in coreboot[master]: mb/google/poppy/variant/nocturne: correct wifi wake register
by Furquan Shaikh (Code Review) 05 Oct '18

05 Oct '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/28938 ) Change subject: mb/google/poppy/variant/nocturne: correct wifi wake register ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iafa865ca79d33541d7f47b69d2fb209e7f9c98af Gerrit-Change-Number: 28938 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 05 Oct 2018 18:49:48 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mb/google/poppy/variant/nocturne: correct wifi wake register
by Nick Vaccaro (Code Review) 05 Oct '18

05 Oct '18

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/28938 Change subject: mb/google/poppy/variant/nocturne: correct wifi wake register ...................................................................... mb/google/poppy/variant/nocturne: correct wifi wake register Wifi wake register is incorrectly set in devicetree. Set wifi wake to its correct wake source, GPE0_DW2_01. BUG=b:117330593 TEST='emerge-nocturne coreboot chromeos-bootimage', flash nocture, connect wifi to a hotspot, suspend device, echo freeze > /sys/power/state, and then shutdown the hotspot and verify device wakes. Change-Id: Iafa865ca79d33541d7f47b69d2fb209e7f9c98af Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/28938/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 9c67795..8313770 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -393,7 +393,7 @@ end # I2C #4 - Audio device pci 1c.0 on chip drivers/intel/wifi - register "wake" = "GPE0_PCI_EXP" + register "wake" = "GPE0_DW2_01" device pci 00.0 on end end end # PCI Express Port 1 -- To view, visit https://review.coreboot.org/28938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iafa865ca79d33541d7f47b69d2fb209e7f9c98af Gerrit-Change-Number: 28938 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com>

1 0

Change in coreboot[master]: soc/intel/cannonlake: Add back PM TIMER EMULATION
by Pratikkumar V Prajapati (Code Review) 05 Oct '18

05 Oct '18

Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/28937 ) Change subject: soc/intel/cannonlake: Add back PM TIMER EMULATION ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28937/2/src/soc/intel/cannonlake/include/so… File src/soc/intel/cannonlake/include/soc/msr.h: https://review.coreboot.org/#/c/28937/2/src/soc/intel/cannonlake/include/so… PS2, Line 24: is this extra space? -- To view, visit https://review.coreboot.org/28937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie069e815e6244c3f85fabf51e186311621d316fd Gerrit-Change-Number: 28937 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Comment-Date: Fri, 05 Oct 2018 17:47:06 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: soc/intel/cannonlake: Add back PM TIMER EMULATION
by Lijian Zhao (Code Review) 05 Oct '18

05 Oct '18

Hello Pratikkumar V Prajapati, Subrata Banik, Wonkyu Kim, Hannah Williams, I'd like you to reexamine a change. Please visit https://review.coreboot.org/28937 to look at the new patch set (#2). Change subject: soc/intel/cannonlake: Add back PM TIMER EMULATION ...................................................................... soc/intel/cannonlake: Add back PM TIMER EMULATION ACPI PM timer emulation will be added back as default FSP stops TCO count for power saving, which will also stop ACPI PM timer within PCH. CPU PM TIMER EMULATION will help UEFI payload pass, instead of endless loop wait for ACPI PM timer counter to increase. BUG=N/A TEST=Build and boot up fine with whiskey lake rvp board into UEFI shell. Change-Id: Ie069e815e6244c3f85fabf51e186311621d316fd Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/include/soc/cpu.h M src/soc/intel/cannonlake/include/soc/msr.h 3 files changed, 30 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/28937/2 -- To view, visit https://review.coreboot.org/28937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ie069e815e6244c3f85fabf51e186311621d316fd Gerrit-Change-Number: 28937 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com>

1 0

Change in coreboot[master]: soc/intel/cannonlake: Add back PM TIMER EMULATION
by Lijian Zhao (Code Review) 05 Oct '18

05 Oct '18

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/28937 Change subject: soc/intel/cannonlake: Add back PM TIMER EMULATION ...................................................................... soc/intel/cannonlake: Add back PM TIMER EMULATION ACPI PM timer emulation will be added back as default FSP stops TCO count for power saving, which will also stop ACPI PM timer within PCH. CPU PM TIMER EMULATION will help UEFI payload pass, instead of endless loop wait for ACPI PM timer counter to increase. BUG=N/A TEST=Build and boot up fine with whiskey lake rvp board into UEFI shell. Change-Id: Ie069e815e6244c3f85fabf51e186311621d316fd Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/cpu.c M src/soc/intel/cannonlake/include/soc/cpu.h M src/soc/intel/cannonlake/include/soc/msr.h 3 files changed, 30 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/28937/1 diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index ba87045..0e5b4bf 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -165,6 +165,27 @@ wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); } +/* + * The emulated ACPI timer allows disabling of the ACPI timer + * (PM1_TMR) to have no impart on the system. + */ +static void enable_pm_timer_emulation(void) +{ + /* ACPI PM timer emulation */ + msr_t msr; + /* + * The derived frequency is calculated as follows: + * (CTC_FREQ * msr[63:32]) >> 32 = target frequency. + * Back solve the multiplier so the 3.579545MHz ACPI timer + * frequency is used. + */ + msr.hi = (3579545ULL << 32) / CTC_FREQ; + /* Set PM1 timer IO port and enable*/ + msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | + EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); + wrmsr(MSR_EMULATE_PM_TMR, msr); +} + /* All CPUs including BSP will run the following function. */ void soc_core_init(struct device *cpu) { @@ -187,6 +208,9 @@ /* Configure Intel Speed Shift */ configure_isst(); + /* Enable ACPI Timer Emulation via MSR 0x121 */ + enable_pm_timer_emulation(); + /* Enable Direct Cache Access */ configure_dca_cap(); diff --git a/src/soc/intel/cannonlake/include/soc/cpu.h b/src/soc/intel/cannonlake/include/soc/cpu.h index dfc7183..1e3e2b4 100644 --- a/src/soc/intel/cannonlake/include/soc/cpu.h +++ b/src/soc/intel/cannonlake/include/soc/cpu.h @@ -37,6 +37,9 @@ #define C9_POWER 0xc8 #define C10_POWER 0xc8 +/* Common Timer Copy (CTC) frequency - 24MHz. */ +#define CTC_FREQ 24000000 + #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \ (((1 << ((base)*5)) * (limit)) / 1000) #define C_STATE_LATENCY_FROM_LAT_REG(reg) \ diff --git a/src/soc/intel/cannonlake/include/soc/msr.h b/src/soc/intel/cannonlake/include/soc/msr.h index c63c921..48db610 100644 --- a/src/soc/intel/cannonlake/include/soc/msr.h +++ b/src/soc/intel/cannonlake/include/soc/msr.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2018 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,6 +20,7 @@ #include <intelblocks/msr.h> #define MSR_PIC_MSG_CONTROL 0x2e +#define EMULATE_DELAY_VALUE 0x13 #define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 -- To view, visit https://review.coreboot.org/28937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie069e815e6244c3f85fabf51e186311621d316fd Gerrit-Change-Number: 28937 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

1 0

Change in coreboot[master]: nb/i945: Check if IGD is enabled before R/W to dev(0, 2)
by Elyes HAOUAS (Code Review) 05 Oct '18

05 Oct '18

Elyes HAOUAS has posted comments on this change. ( https://review.coreboot.org/28935 ) Change subject: nb/i945: Check if IGD is enabled before R/W to dev(0, 2) ...................................................................... Patch Set 1: > >> I don't see a way IGD could be disabled at this stage. But what > about > >> SKUs that don't have it at all? are there any (on supported > boards)? > > > > 1 - In case we use an external GPU, the IGD is disabled at > > arly_init.c (line #686). > > Which is run after raminit. > > > (BTW: line +949 should be commented) > > It doesn't work without that line. You probably mean 950 should > be implemented for the desktop version. Please, go ahead. > The board I have works without that line. seems that nvidia external GPU didn't work properly (I don't have it for test), But ATI works just fine without that line. More, it works better without that line. please see https://review.coreboot.org/#/c/coreboot/+/27985/ (Arthur's comment on Patch Set 3 ) > > 2 - there some desktop's version that do not have IGD at all. > > That's why I was asking. Are the DEVEN bits hard-wired to 0 for > them? > I don't think so, but as you know, intel's datasheet are not helpful :( maybe some one from intel can help ... > > 3 - at function "sdram_power_management", we set > integrated_graphics > > = 1 and use it for test in raminit.c line #2305 .... this do not > > make sense. > > It documents for the human reader that it should only be executed > when integrated graphics are present (or maybe only when enabled; > that's not clear). This can be useful, for instance, when somebody > wants to implement it for system without IGD. here I mean why we define "integrated_graphics" = 1 ? the test do not make sense : if (1) { .... }else { ..... <<=== this will never happen } so let give a sense to "integrated_graphics" and set it to 1 if IGD is enabled. -- To view, visit https://review.coreboot.org/28935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I51ab94393710ce0222b353ab0cef28621fafaacf Gerrit-Change-Number: 28935 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 05 Oct 2018 17:14:19 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: nb/i945: Check if IGD is enabled before R/W to dev(0, 2)
by Nico Huber (Code Review) 05 Oct '18

05 Oct '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/28935 ) Change subject: nb/i945: Check if IGD is enabled before R/W to dev(0, 2) ...................................................................... Patch Set 1: >> I don't see a way IGD could be disabled at this stage. But what about >> SKUs that don't have it at all? are there any (on supported boards)? > > 1 - In case we use an external GPU, the IGD is disabled at > arly_init.c (line #686). Which is run after raminit. > (BTW: line +949 should be commented) It doesn't work without that line. You probably mean 950 should be implemented for the desktop version. Please, go ahead. > 2 - there some desktop's version that do not have IGD at all. That's why I was asking. Are the DEVEN bits hard-wired to 0 for them? > 3 - at function "sdram_power_management", we set integrated_graphics > = 1 and use it for test in raminit.c line #2305 .... this do not > make sense. It documents for the human reader that it should only be executed when integrated graphics are present (or maybe only when enabled; that's not clear). This can be useful, for instance, when somebody wants to implement it for system without IGD. -- To view, visit https://review.coreboot.org/28935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I51ab94393710ce0222b353ab0cef28621fafaacf Gerrit-Change-Number: 28935 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 05 Oct 2018 16:22:40 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: nb/i945: Check if IGD is enabled before R/W to dev(0, 2)
by Angel Pons (Code Review) 05 Oct '18

05 Oct '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/28935 ) Change subject: nb/i945: Check if IGD is enabled before R/W to dev(0, 2) ...................................................................... Patch Set 1: > 2 - there some desktop's version that do not have IGD at all. There are some mobile versions which do not have an IGD either. -- To view, visit https://review.coreboot.org/28935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I51ab94393710ce0222b353ab0cef28621fafaacf Gerrit-Change-Number: 28935 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 05 Oct 2018 16:04:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: nb/i945: Check if IGD is enabled before R/W to dev(0, 2)
by Elyes HAOUAS (Code Review) 05 Oct '18

05 Oct '18

1 0

Change in coreboot[master]: Unify all Lenovo t520 variants
by Patrick Rudolph (Code Review) 05 Oct '18

05 Oct '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28936 ) Change subject: Unify all Lenovo t520 variants ...................................................................... Patch Set 2: (1 comment) did you test it on L520 ? https://review.coreboot.org/#/c/28936/2/src/mainboard/lenovo/t520/hda_verb.c File src/mainboard/lenovo/t520/hda_verb.c: https://review.coreboot.org/#/c/28936/2/src/mainboard/lenovo/t520/hda_verb.… PS2, Line 33: #ifdef CONFIG_BOARD_LENOVO_L520 no #ifdefs or #if -- To view, visit https://review.coreboot.org/28936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I936ec6e51dc74637439d8562070443904071708c Gerrit-Change-Number: 28936 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 05 Oct 2018 14:49:02 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2018