coreboot-gerrit September 2017

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Change in coreboot[master]: amd/stoneyridge: Add UMA settings to chip.h
by Marshall Dawson (Code Review) 02 Sep '17

02 Sep '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21334 Change subject: amd/stoneyridge: Add UMA settings to chip.h ...................................................................... amd/stoneyridge: Add UMA settings to chip.h Add three settings for the UMA configuration to correspond with definitions in AGESA.h. * UMA off, Auto, or size specified * Size (if specified above) * Legacy vs. non-legacy BUG=b:64927639 Change-Id: I38b6603f365fdc1f1f615794365476f749e58be7 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/chip.h 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/21334/1 diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index cd3bc74..c0c864a 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -19,6 +19,14 @@ #include <stdint.h> struct soc_amd_stoneyridge_config { + u32 uma_mode; + #define UMAMODE_NONE 0 + #define UMAMODE_SPECIFIED 1 + #define UMAMODE_AUTO 2 + u32 uma_type; + #define UMATYPE_LEGACY 0 + #define UMATYPE_NONLEGACY 1 + u32 uma_size; /* size in units of 64KB, N/A for none and auto */ u8 spdAddrLookup[1][1][2]; u32 ide0_enable : 1; u32 sata0_enable : 1; -- To view, visit https://review.coreboot.org/21334 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I38b6603f365fdc1f1f615794365476f749e58be7 Gerrit-Change-Number: 21334 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/stoneyridge: Remove duplicate PCI definitions
by Marshall Dawson (Code Review) 02 Sep '17

02 Sep '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/21333 Change subject: amd/stoneyridge: Remove duplicate PCI definitions ...................................................................... amd/stoneyridge: Remove duplicate PCI definitions Change-Id: Iafb10476f32505f6b4ad7b5ba6fa5de2c4648836 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/include/soc/pci_devs.h 1 file changed, 0 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/21333/1 diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h index 5c7f86a..caa4765 100644 --- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h +++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h @@ -19,48 +19,6 @@ #include <device/pci_def.h> #include <rules.h> -/* HT Configuration */ -#define HT_DEV 0x18 -#define HT_FUNC 0 -#define HT_DEVID 0x15b0 -#define HT_DEVFN PCI_DEVFN(HT_DEV, HT_FUNC) - -/* Address Maps */ -#define ADDR_DEV 0x18 -#define ADDR_FUNC 1 -#define ADDR_DEVID 0x15b1 -#define ADDR_DEVFN PCI_DEVFN(ADDR_DEV, ADDR_FUNC) - -/* DRAM Configuration */ -#define DCT_DEV 0x18 -#define DCT_FUNC 2 -#define DCT_DEVID 0x15b2 -#define DCT_DEVFN PCI_DEVFN(DCT_DEV, DCT_FUNC) - -/* Misc. Configuration */ -#define MISC_DEV 0x18 -#define MISC_FUNC 3 -#define MISC_DEVID 0x15b3 -#define MISC_DEVFN PCI_DEVFN(MISC_DEV, MISC_FUNC) - -/* PM Configuration */ -#define PM_DEV 0x18 -#define PM_FUNC 4 -#define PM_DEVID 0x15b4 -#define PM_DEVFN PCI_DEVFN(PM_DEV, PM_FUNC) -#if !defined(__SIMPLE_DEVICE__) - #include <device/device.h> - #define DEV_D18F4 dev_find_slot(0, PM_DEVFN) -#else - #define DEV_D18F4 PCI_DEV(0, PM_DEV, PM_FUNC) -#endif - -/* Northbridge Configuration */ -#define NB_DEV 0x18 -#define NB_FUNC 5 -#define NB_DEVID 0x15b5 -#define NB_DEVFN PCI_DEVFN(NB_DEV, NB_FUNC) - /* GNB Root Complex */ #define GNB_DEV 0x0 #define GNB_FUNC 0 -- To view, visit https://review.coreboot.org/21333 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iafb10476f32505f6b4ad7b5ba6fa5de2c4648836 Gerrit-Change-Number: 21333 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: winbond/w83697hf: Drop early_serial.c
by Keith Hui (Code Review) 02 Sep '17

02 Sep '17

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/21332 Change subject: winbond/w83697hf: Drop early_serial.c ...................................................................... winbond/w83697hf: Drop early_serial.c It is already using winbond_enable_serial(). Once w83697hf_set_clksel_48() is unified into winbond/common/early_init.c, this file is no longer needed and can be dropped. Change-Id: I7424233b5d70e143721038493f194760f07346a1 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/superio/winbond/w83697hf/Makefile.inc D src/superio/winbond/w83697hf/early_serial.c M src/superio/winbond/w83697hf/w83697hf.h 3 files changed, 0 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/21332/1 diff --git a/src/superio/winbond/w83697hf/Makefile.inc b/src/superio/winbond/w83697hf/Makefile.inc index 3b521ed..d1ef2b0 100644 --- a/src/superio/winbond/w83697hf/Makefile.inc +++ b/src/superio/winbond/w83697hf/Makefile.inc @@ -14,5 +14,4 @@ ## GNU General Public License for more details. ## -romstage-$(CONFIG_SUPERIO_WINBOND_W83697HF) += early_serial.c ramstage-$(CONFIG_SUPERIO_WINBOND_W83697HF) += superio.c diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c deleted file mode 100644 index 48d76e0..0000000 --- a/src/superio/winbond/w83697hf/early_serial.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Sean Nelson <snelson(a)nmt.edu> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pnp_def.h> -#include "w83697hf.h" - -static void pnp_enter_ext_func_mode(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_ext_func_mode(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -void w83697hf_set_clksel_48(pnp_devfn_t dev) -{ - u8 reg8; - - pnp_enter_ext_func_mode(dev); - reg8 = pnp_read_config(dev, 0x24); - reg8 |= (1 << 6); /* Set the clock input to 48MHz. */ - pnp_write_config(dev, 0x24, reg8); - pnp_exit_ext_func_mode(dev); -} - -/* Depreciated, use winbond_enable_serial() */ -void w83697hf_enable_serial(pnp_devfn_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} diff --git a/src/superio/winbond/w83697hf/w83697hf.h b/src/superio/winbond/w83697hf/w83697hf.h index 756fa98..52466a8 100644 --- a/src/superio/winbond/w83697hf/w83697hf.h +++ b/src/superio/winbond/w83697hf/w83697hf.h @@ -17,8 +17,6 @@ #ifndef SUPERIO_WINBOND_W83697HF_H #define SUPERIO_WINBOND_W83697HF_H -#include <arch/io.h> - #define W83697HF_FDC 0 /* Floppy */ #define W83697HF_PP 1 /* Parallel port */ #define W83697HF_SP1 2 /* Com1 */ @@ -29,10 +27,5 @@ #define W83697HF_GPIO234 9 /* GPIO 2, 3, 4 */ #define W83697HF_ACPI 10 /* ACPI */ #define W83697HF_HWM 11 /* Hardware monitor */ - -void w83697hf_set_clksel_48(pnp_devfn_t); - -/* Depreciated, use winbond_enable_serial() */ -void w83697hf_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_WINBOND_W83697HF_H */ -- To view, visit https://review.coreboot.org/21332 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7424233b5d70e143721038493f194760f07346a1 Gerrit-Change-Number: 21332 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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Change in coreboot[master]: superio/winbond/*: Unify w*_set_clksel_48()
by Keith Hui (Code Review) 02 Sep '17

02 Sep '17

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/21331 Change subject: superio/winbond/*: Unify w*_set_clksel_48() ...................................................................... superio/winbond/*: Unify w*_set_clksel_48() This function is identical throughout all Winbond superios in the tree, so move it into superio/winbond/common/early_init.c, renamed from early_serial.c because it now does more than just early serial. Change all affected mainboards to use the unified function. Change-Id: If05e0db93375641917e538d83aacd1b50fbd033b Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/bcom/winnetp680/romstage.c M src/mainboard/msi/ms6178/romstage.c M src/mainboard/supermicro/h8dme/romstage.c M src/mainboard/supermicro/h8dmr/romstage.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/tyan/s8226/romstage.c M src/mainboard/via/epia-m700/romstage.c M src/mainboard/winent/pl6064/romstage.c M src/mainboard/winnet/g170/romstage.c M src/superio/winbond/Makefile.inc R src/superio/winbond/common/early_init.c M src/superio/winbond/common/winbond.h 15 files changed, 26 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/21331/1 diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index d143724..7714f72 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -100,7 +100,7 @@ enable_rs780_dev8(); sb800_clk_output_48Mhz(); - w83627hf_set_clksel_48(PNP_DEV(0x2e, 0)); + winbond_set_clksel_48(PNP_DEV(0x2e, 0)); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index d32e7b2..e574ecd 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -100,7 +100,7 @@ enable_rs780_dev8(); sb800_clk_output_48Mhz(); - w83627hf_set_clksel_48(CLK_DEV); + winbond_set_clksel_48(CLK_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index 4ba528c..0703ba6 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -78,7 +78,7 @@ /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); - w83697hf_set_clksel_48(SERIAL_DEV); + winbond_set_clksel_48(SERIAL_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c index d7cbc32..2f1180e 100644 --- a/src/mainboard/msi/ms6178/romstage.c +++ b/src/mainboard/msi/ms6178/romstage.c @@ -33,7 +33,7 @@ void mainboard_romstage_entry(unsigned long bist) { - w83627hf_set_clksel_48(DUMMY_DEV); + winbond_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index cacdd41..9deb940 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -140,7 +140,7 @@ if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - w83627hf_set_clksel_48(DUMMY_DEV); + winbond_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 550bb89..9da1ab5 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -120,7 +120,7 @@ if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - w83627hf_set_clksel_48(DUMMY_DEV); + winbond_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index eb6edff..7ba4f60 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -130,7 +130,7 @@ post_code(0x32); - w83627hf_set_clksel_48(DUMMY_DEV); + winbond_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index edede81..3c255c5 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -195,7 +195,7 @@ post_code(0x32); - w83627hf_set_clksel_48(DUMMY_DEV); + winbond_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index 220098d..3731e88 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -53,7 +53,7 @@ report_bist_failure(bist); sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ - w83627dhg_set_clksel_48(DUMMY_DEV); + winbond_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); post_code(0x34); diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index 2f8ecce..faf87c7 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -378,7 +378,7 @@ */ pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01); /* EmbedComInit(); */ - w83697hf_set_clksel_48(DUMMY_DEV); + winbond_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* enable_vx800_serial(); */ diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index 624163b..a8f64cf 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -59,7 +59,7 @@ /* Note: must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - w83627hf_set_clksel_48(SERIAL_DEV); + winbond_set_clksel_48(SERIAL_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/winnet/g170/romstage.c b/src/mainboard/winnet/g170/romstage.c index 9ac02d0..4b549bb 100644 --- a/src/mainboard/winnet/g170/romstage.c +++ b/src/mainboard/winnet/g170/romstage.c @@ -79,7 +79,7 @@ /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); - w83697hf_set_clksel_48(SERIAL_DEV); + winbond_set_clksel_48(SERIAL_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/superio/winbond/Makefile.inc b/src/superio/winbond/Makefile.inc index ae4b283..b0b7b8c 100644 --- a/src/superio/winbond/Makefile.inc +++ b/src/superio/winbond/Makefile.inc @@ -14,7 +14,7 @@ ## ## include generic winbond pre-ram stage driver -romstage-$(CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE) += common/early_serial.c +romstage-$(CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE) += common/early_init.c subdirs-y += w83627dhg subdirs-y += w83627ehg diff --git a/src/superio/winbond/common/early_serial.c b/src/superio/winbond/common/early_init.c similarity index 88% rename from src/superio/winbond/common/early_serial.c rename to src/superio/winbond/common/early_init.c index aebbd38..7c3ce2b 100644 --- a/src/superio/winbond/common/early_serial.c +++ b/src/superio/winbond/common/early_init.c @@ -15,7 +15,7 @@ */ /* - * A generic romstage (pre-ram) driver for Winbond variant Super I/O chips. + * A generic romstage (pre-ram) driver for various Winbond Super I/O chips. * * The following is derived directly from the vendor Winbond's data-sheets: * @@ -79,3 +79,14 @@ pnp_write_config(dev, offset, byte); pnp_exit_conf_state(dev); } + +void winbond_set_clksel_48(pnp_devfn_t dev) +{ + u8 reg8; + + pnp_enter_conf_state(dev); + reg8 = pnp_read_config(dev, 0x24); + reg8 |= (1 << 6); /* Set the clock input to 48MHz. */ + pnp_write_config(dev, 0x24, reg8); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/winbond/common/winbond.h b/src/superio/winbond/common/winbond.h index 6e67eeb..e472018 100644 --- a/src/superio/winbond/common/winbond.h +++ b/src/superio/winbond/common/winbond.h @@ -22,6 +22,7 @@ void winbond_enable_serial(pnp_devfn_t dev, uint16_t iobase); void winbond_set_pinmux(pnp_devfn_t dev, uint8_t offset, uint8_t mask, uint8_t state); +void winbond_set_clksel_48(pnp_devfn_t dev); void pnp_enter_conf_state(pnp_devfn_t dev); void pnp_exit_conf_state(pnp_devfn_t dev); -- To view, visit https://review.coreboot.org/21331 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If05e0db93375641917e538d83aacd1b50fbd033b Gerrit-Change-Number: 21331 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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Change in coreboot[master]: soc/intel/common/block/gpio: Fix PAD_DW1_MASK
by build bot (Jenkins) (Code Review) 02 Sep '17

02 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21282 ) Change subject: soc/intel/common/block/gpio: Fix PAD_DW1_MASK ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14986/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59714/ : SUCCESS -- To view, visit https://review.coreboot.org/21282 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2b0b9c07ebc99f4b4d7e8c5a72483bedd33e2e07 Gerrit-Change-Number: 21282 Gerrit-PatchSet: 2 Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Sep 2017 23:24:50 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/lulu, gandof: set kb backlight on boot
by build bot (Jenkins) (Code Review) 02 Sep '17

02 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21330 ) Change subject: google/lulu,gandof: set kb backlight on boot ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14985/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59713/ : SUCCESS -- To view, visit https://review.coreboot.org/21330 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7ed59289419af21764b1b5bd0a534d3b630c6c6b Gerrit-Change-Number: 21330 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Sep 2017 23:00:44 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/lulu, gandof: set kb backlight on boot
by Matt DeVillier (Code Review) 02 Sep '17

02 Sep '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21330 Change subject: google/lulu,gandof: set kb backlight on boot ...................................................................... google/lulu,gandof: set kb backlight on boot Set keyboard backlight to 75% on boot, except when resuming from S3. This enables the backlight at a reasonable level prior to the OS driver taking over, providing early proof-of-life and enhanced usability in grub etc. Uses same method as other google boards with a keyboard backlight (chell, link, samus). 75% value determined based on user feedback. TEST: boot google/lulu,gandof boards, observe keyboard backlight enabled in pre-OS environment. Change-Id: I7ed59289419af21764b1b5bd0a534d3b630c6c6b Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/auron/variants/gandof/variant.c M src/mainboard/google/auron/variants/lulu/variant.c 2 files changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/21330/1 diff --git a/src/mainboard/google/auron/variants/gandof/variant.c b/src/mainboard/google/auron/variants/gandof/variant.c index f1af14d..ad88f0d 100644 --- a/src/mainboard/google/auron/variants/gandof/variant.c +++ b/src/mainboard/google/auron/variants/gandof/variant.c @@ -11,6 +11,8 @@ * GNU General Public License for more details. */ +#include <ec/google/chromeec/ec.h> +#include <soc/pm.h> #include <smbios.h> #include <soc/romstage.h> #include <variant/onboard.h> @@ -35,5 +37,6 @@ void variant_romstage_entry(struct romstage_params *rp) { - /* N/A for boards other than SAMUS */ + if (rp->power_state->prev_sleep_state != ACPI_S3) + google_chromeec_kbbacklight(75); } diff --git a/src/mainboard/google/auron/variants/lulu/variant.c b/src/mainboard/google/auron/variants/lulu/variant.c index 740decf..9d77c27 100644 --- a/src/mainboard/google/auron/variants/lulu/variant.c +++ b/src/mainboard/google/auron/variants/lulu/variant.c @@ -11,6 +11,8 @@ * GNU General Public License for more details. */ +#include <ec/google/chromeec/ec.h> +#include <soc/pm.h> #include <smbios.h> #include <soc/romstage.h> #include <variant/onboard.h> @@ -44,5 +46,6 @@ void variant_romstage_entry(struct romstage_params *rp) { - /* N/A for boards other than SAMUS */ + if (rp->power_state->prev_sleep_state != ACPI_S3) + google_chromeec_kbbacklight(75); } -- To view, visit https://review.coreboot.org/21330 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7ed59289419af21764b1b5bd0a534d3b630c6c6b Gerrit-Change-Number: 21330 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: cpu/intel/car/cache_as_ram.inc: Simplify code path
by build bot (Jenkins) (Code Review) 02 Sep '17

02 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21329 ) Change subject: cpu/intel/car/cache_as_ram.inc: Simplify code path ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14984/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59712/ : SUCCESS -- To view, visit https://review.coreboot.org/21329 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9ab996e46e4f96320143022938477a5fd2046ed7 Gerrit-Change-Number: 21329 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Sep 2017 22:47:54 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: cpu/intel/car/cache_as_ram.inc: Simplify code path
by Keith Hui (Code Review) 02 Sep '17

02 Sep '17

Keith Hui has posted comments on this change. ( https://review.coreboot.org/21329 ) Change subject: cpu/intel/car/cache_as_ram.inc: Simplify code path ...................................................................... Patch Set 2: Please review based on patch set 2. -- To view, visit https://review.coreboot.org/21329 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9ab996e46e4f96320143022938477a5fd2046ed7 Gerrit-Change-Number: 21329 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Sep 2017 22:42:53 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: cpu/intel/car/cache_as_ram.inc: Simplify code path
by Keith Hui (Code Review) 02 Sep '17

02 Sep '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/21329 to look at the new patch set (#2). Change subject: cpu/intel/car/cache_as_ram.inc: Simplify code path ...................................................................... cpu/intel/car/cache_as_ram.inc: Simplify code path Make all CAR-related calculations refer to CONFIG_DCACHE_RAM_BASE and CONFIG_DCACHE_RAM_SIZE for consistency. This fixes a bug that prevents migrating cpu/intel/slot_1 & nb/intel/i440bx to EARLY_CBMEM_INIT. Exclude a Hyperthreading-specific code path when building for slot_1 or pga370, which predates HT. Do not clear MTRRs that will be programmed immediately afterwards. Remove a block of CAR testing code currently blocked out by #if. Newer CAR code don't even do it anymore. Do not set %ebp before calling romstage_main(). We know it's not needed. Clarify the purpose of various code in the file. Boot tested on ASUS P2B-LS mainboard. Brought to you by https://review.coreboot.org/c/20977/. Change-Id: I9ab996e46e4f96320143022938477a5fd2046ed7 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/cpu/intel/car/cache_as_ram.inc 1 file changed, 31 insertions(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/21329/2 -- To view, visit https://review.coreboot.org/21329 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I9ab996e46e4f96320143022938477a5fd2046ed7 Gerrit-Change-Number: 21329 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit September 2017