coreboot-gerrit September 2017

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Change in coreboot[master]: cpu/intel/car/cache_as_ram.inc: Simplify code path
by Keith Hui (Code Review) 01 Sep '17

01 Sep '17

Keith Hui has posted comments on this change. ( https://review.coreboot.org/21329 ) Change subject: cpu/intel/car/cache_as_ram.inc: Simplify code path ...................................................................... Patch Set 1: Please hold. One of the items isn't valid. Will submit an update. -- To view, visit https://review.coreboot.org/21329 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9ab996e46e4f96320143022938477a5fd2046ed7 Gerrit-Change-Number: 21329 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Sep 2017 22:14:04 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: cpu/intel/car/cache_as_ram.inc: Simplify code path
by build bot (Jenkins) (Code Review) 01 Sep '17

01 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21329 ) Change subject: cpu/intel/car/cache_as_ram.inc: Simplify code path ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14983/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59711/ : SUCCESS -- To view, visit https://review.coreboot.org/21329 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9ab996e46e4f96320143022938477a5fd2046ed7 Gerrit-Change-Number: 21329 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Sep 2017 22:07:54 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP] arch/x86/acpigen: Add function to write a CPU package
by build bot (Jenkins) (Code Review) 01 Sep '17

01 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21324 ) Change subject: [WIP] arch/x86/acpigen: Add function to write a CPU package ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14982/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59710/ : SUCCESS -- To view, visit https://review.coreboot.org/21324 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I10e9ebad84343d1fb282b3fbb28f5f014f664f14 Gerrit-Change-Number: 21324 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Sep 2017 22:03:13 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: cpu/intel/car/cache_as_ram.inc: Simplify code path
by Keith Hui (Code Review) 01 Sep '17

01 Sep '17

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/21329 Change subject: cpu/intel/car/cache_as_ram.inc: Simplify code path ...................................................................... cpu/intel/car/cache_as_ram.inc: Simplify code path Make all CAR-related calculations refer to CONFIG_DCACHE_RAM_BASE and CONFIG_DCACHE_RAM_SIZE for consistency. This fixes a bug that prevents migrating cpu/intel/slot_1 & nb/intel/i440bx to EARLY_CBMEM_INIT. Exclude a Hyperthreading-specific code path when building for slot_1 or pga370, which predates HT. Do not clear MTRRs that will be programmed immediately afterwards. Remove a block of CAR testing code currently blocked out by #if. Newer CAR code don't even do it anymore. Do not set %ebp before calling romstage_main(). We know it's not needed. The check for CONFIG_DCACHE_RAM_SIZE < 0x1000 is not needed; checking that it is multiples of 4k will catch it. Clarify the purpose of various code in the file. Boot tested on ASUS P2B-LS mainboard. Brought to you by https://review.coreboot.org/c/20977/. Change-Id: I9ab996e46e4f96320143022938477a5fd2046ed7 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/cpu/intel/car/cache_as_ram.inc 1 file changed, 31 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/21329/1 diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index ac17571..ee1d577 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -22,13 +22,15 @@ #include <cpu/x86/lapic_def.h> #include <cpu/x86/post_code.h> -#define CacheSize CONFIG_DCACHE_RAM_SIZE -#define CacheBase (0xd0000 - CacheSize) - /* Save the BIST result. */ movl %eax, %ebp CacheAsRam: +/* + * Only SLOT_1, SOCKET_(FC_)PGA370 and SOCKET_MPGA479M use this code and HT + * was only introduced for 479. Include this HT-specific code only on 479. + */ +#if IS_ENABLED(CONFIG_CPU_INTEL_SOCKET_MPGA479M) /* Check whether the processor has HT capability. */ movl $01, %eax cpuid @@ -104,6 +106,7 @@ jz LogicalAP_SIPINotdone NotHtProcessor: +#endif /* Set the default memory type and enable fixed and variable MTRRs. */ movl $MTRR_DEF_TYPE_MSR, %ecx xorl %edx, %edx @@ -130,8 +133,13 @@ .long MTRR_FIX_64K_00000 .long MTRR_FIX_16K_80000 .long MTRR_FIX_16K_A0000 + /* C0000 will be set later if DCACHE_RAM_BASE is set below 0xc8000. + * Don't try to set it twice. + */ +#if CONFIG_DCACHE_RAM_BASE >= 0xc8000 .long MTRR_FIX_4K_C0000 - .long MTRR_FIX_4K_C8000 +#endif + /* C8000 will be set later. */ .long MTRR_FIX_4K_D0000 .long MTRR_FIX_4K_D8000 .long MTRR_FIX_4K_E0000 @@ -142,8 +150,7 @@ /* var MTRR MSRs */ .long MTRR_PHYS_BASE(0) .long MTRR_PHYS_MASK(0) - .long MTRR_PHYS_BASE(1) - .long MTRR_PHYS_MASK(1) + /* var MTRR #1 will be set next for XIP ROM. Don't try to set it twice. */ .long MTRR_PHYS_BASE(2) .long MTRR_PHYS_MASK(2) .long MTRR_PHYS_BASE(3) @@ -203,32 +210,27 @@ */ .endm -#if CacheSize > 0x10000 +#if CONFIG_DCACHE_RAM_SIZE > 0x10000 #error Invalid CAR size, must be at most 64k. #endif -#if CacheSize < 0x1000 -#error Invalid CAR size, must be at least 4k. This is a processor limitation. -#endif -#if (CacheSize & (0x1000 - 1)) +/* This check will also catch DCACHE_RAM_SIZE < 0x1000 */ +#if (CONFIG_DCACHE_RAM_SIZE & (0x1000 - 1)) #error Invalid CAR size, is not a multiple of 4k. This is a processor limitation. #endif -#if CacheSize > 0x8000 +#if CONFIG_DCACHE_RAM_SIZE > 0x8000 /* Enable caching for 32K-64K using fixed MTRR. */ movl $MTRR_FIX_4K_C0000, %ecx - simplemask CacheSize, 0x8000 + simplemask CONFIG_DCACHE_RAM_SIZE, 0x8000 wrmsr #endif /* Enable caching for 0-32K using fixed MTRR. */ movl $MTRR_FIX_4K_C8000, %ecx - simplemask CacheSize, 0 + simplemask CONFIG_DCACHE_RAM_SIZE, 0 wrmsr - /* - * Enable write base caching so we can do execute in place (XIP) - * on the flash ROM. - */ + /* Enable cache for our code in Flash because we do XIP here. */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx /* @@ -237,7 +239,7 @@ */ movl $copy_and_run, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax - orl $MTRR_TYPE_WRBACK, %eax + orl $MTRR_TYPE_WRPROT, %eax wrmsr movl $MTRR_PHYS_MASK(1), %ecx @@ -250,70 +252,26 @@ andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 - /* Read the range with lodsl. */ - movl $CacheBase, %esi + /* Read the CAR region. This will also fill up the cache. + * IMPORTANT: This step is mandatory. + */ + movl $CONFIG_DCACHE_RAM_BASE, %esi cld - movl $(CacheSize >> 2), %ecx + movl $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx rep lodsl - /* Clear the range. */ - movl $CacheBase, %edi - movl $(CacheSize >> 2), %ecx + /* Clear the CAR region. */ + movl $CONFIG_DCACHE_RAM_BASE, %edi + movl $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx xorl %eax, %eax rep stosl -#if 0 - /* Check the cache as ram. */ - movl $CacheBase, %esi - movl $(CacheSize >> 2), %ecx -.xin1: - movl %esi, %eax - movl %eax, (%esi) - decl %ecx - je .xout1 - add $4, %esi - jmp .xin1 -.xout1: - - movl $CacheBase, %esi - // movl $(CacheSize >> 2), %ecx - movl $4, %ecx -.xin1x: - movl %esi, %eax - - movl $0x4000, %edx - movb %ah, %al -.testx1: - outb %al, $0x80 - decl %edx - jnz .testx1 - - movl (%esi), %eax - cmpb 0xff, %al - je .xin2 /* Don't show. */ - - movl $0x4000, %edx -.testx2: - outb %al, $0x80 - decl %edx - jnz .testx2 - -.xin2: - decl %ecx - je .xout1x - add $4, %esi - jmp .xin1x -.xout1x: -#endif - - movl $(CacheBase + CacheSize - 4), %eax + movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax movl %eax, %esp lout: /* Restore the BIST result. */ movl %ebp, %eax - /* We need to set EBP? No need. */ - movl %esp, %ebp pushl %eax /* BIST */ call romstage_main @@ -329,7 +287,7 @@ orl $CR0_CacheDisable, %eax movl %eax, %cr0 - /* Clear sth. */ + /* Clear the fixed MTRR we used. */ movl $MTRR_FIX_4K_C8000, %ecx xorl %edx, %edx xorl %eax, %eax -- To view, visit https://review.coreboot.org/21329 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9ab996e46e4f96320143022938477a5fd2046ed7 Gerrit-Change-Number: 21329 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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Change in coreboot[master]: [WIP] arch/x86/acpigen: Add function to write a CPU package
by Nico Huber (Code Review) 01 Sep '17

01 Sep '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/21324 to look at the new patch set (#2). Change subject: [WIP] arch/x86/acpigen: Add function to write a CPU package ...................................................................... [WIP] arch/x86/acpigen: Add function to write a CPU package Emits a list of CPU cores, e.g. Name (PPKG, Package (2) { \_PR.CP00, \_PR.CP01 }) Change-Id: I10e9ebad84343d1fb282b3fbb28f5f014f664f14 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/arch/x86/acpigen.c M src/arch/x86/include/arch/acpigen.h 2 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/21324/2 -- To view, visit https://review.coreboot.org/21324 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I10e9ebad84343d1fb282b3fbb28f5f014f664f14 Gerrit-Change-Number: 21324 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/bd82x6x: Revise flash ROM lockdown options
by build bot (Jenkins) (Code Review) 01 Sep '17

01 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21327 ) Change subject: sb/intel/bd82x6x: Revise flash ROM lockdown options ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14981/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59709/ : SUCCESS -- To view, visit https://review.coreboot.org/21327 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I435a3b63dd294aa766b1eccf1aa80a7c47e55c95 Gerrit-Change-Number: 21327 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Sep 2017 21:50:11 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/gru: Re-enable 3V rail GPIO on Scarlet
by build bot (Jenkins) (Code Review) 01 Sep '17

01 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21328 ) Change subject: google/gru: Re-enable 3V rail GPIO on Scarlet ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14978/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59705/ : SUCCESS -- To view, visit https://review.coreboot.org/21328 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6037aa486b50119f2c7b859b966cadc3686e3459 Gerrit-Change-Number: 21328 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: David Schneider <dnschneid(a)chromium.org> Gerrit-Reviewer: Lin Huang <hl(a)rock-chips.com> Gerrit-Reviewer: Philip Chen <philipchen(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Sep 2017 21:44:37 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/common: Write MRC cache at exit of BS_DEV_INIT
by build bot (Jenkins) (Code Review) 01 Sep '17

01 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21326 ) Change subject: nb/intel/common: Write MRC cache at exit of BS_DEV_INIT ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14976/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59704/ : SUCCESS -- To view, visit https://review.coreboot.org/21326 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifda826ae2bb28adcce8dda8e2bb16dc38fe0fe9e Gerrit-Change-Number: 21326 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Sep 2017 21:44:31 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add PMC pci drivers
by build bot (Jenkins) (Code Review) 01 Sep '17

01 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21251 ) Change subject: soc/intel/cannonlake: Add PMC pci drivers ...................................................................... Patch Set 8: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/59706/ : SUCCESS -- To view, visit https://review.coreboot.org/21251 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I95895a3e26cdebd98a4e54720bd4730542707d7e Gerrit-Change-Number: 21251 Gerrit-PatchSet: 8 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrex Andraos <andrex.andraos(a)intel.corp-partner.google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Sep 2017 21:43:10 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add PMC pci drivers
by build bot (Jenkins) (Code Review) 01 Sep '17

01 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21251 ) Change subject: soc/intel/cannonlake: Add PMC pci drivers ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14979/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59707/ : SUCCESS -- To view, visit https://review.coreboot.org/21251 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I95895a3e26cdebd98a4e54720bd4730542707d7e Gerrit-Change-Number: 21251 Gerrit-PatchSet: 8 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrex Andraos <andrex.andraos(a)intel.corp-partner.google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Sep 2017 21:41:09 +0000 Gerrit-HasComments: No

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coreboot-gerrit September 2017