coreboot-gerrit September 2017

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Change in coreboot[master]: sb/intel/bd82x6x: Revise flash ROM lockdown options
by Nico Huber (Code Review) 01 Sep '17

01 Sep '17

Nico Huber has posted comments on this change. ( https://review.coreboot.org/21327 ) Change subject: sb/intel/bd82x6x: Revise flash ROM lockdown options ...................................................................... Patch Set 3: to be tested -- To view, visit https://review.coreboot.org/21327 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I435a3b63dd294aa766b1eccf1aa80a7c47e55c95 Gerrit-Change-Number: 21327 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Sep 2017 21:39:02 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/bd82x6x: Revise flash ROM lockdown options
by build bot (Jenkins) (Code Review) 01 Sep '17

01 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21327 ) Change subject: sb/intel/bd82x6x: Revise flash ROM lockdown options ...................................................................... Patch Set 2: Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/14980/ : ABORTED https://qa.coreboot.org/job/coreboot-gerrit/59708/ : ABORTED -- To view, visit https://review.coreboot.org/21327 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I435a3b63dd294aa766b1eccf1aa80a7c47e55c95 Gerrit-Change-Number: 21327 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Sep 2017 21:38:10 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/bd82x6x: Revise flash ROM lockdown options
by Nico Huber (Code Review) 01 Sep '17

01 Sep '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/21327 to look at the new patch set (#3). Change subject: sb/intel/bd82x6x: Revise flash ROM lockdown options ...................................................................... sb/intel/bd82x6x: Revise flash ROM lockdown options The original options were named and described under the false assumption that the chipset lockdown would only be executed during S3 resume. Fix that. Change-Id: I435a3b63dd294aa766b1eccf1aa80a7c47e55c95 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/finalize.c 2 files changed, 29 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/21327/3 -- To view, visit https://review.coreboot.org/21327 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I435a3b63dd294aa766b1eccf1aa80a7c47e55c95 Gerrit-Change-Number: 21327 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/bd82x6x: Revise flash ROM lockdown options
by Nico Huber (Code Review) 01 Sep '17

01 Sep '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/21327 to look at the new patch set (#2). Change subject: sb/intel/bd82x6x: Revise flash ROM lockdown options ...................................................................... sb/intel/bd82x6x: Revise flash ROM lockdown options The original options were named and described under the false assumption that the chipset lockdown would only be executed during S3 resume. Fix that. Change-Id: I435a3b63dd294aa766b1eccf1aa80a7c47e55c95 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/finalize.c 2 files changed, 33 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/21327/2 -- To view, visit https://review.coreboot.org/21327 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I435a3b63dd294aa766b1eccf1aa80a7c47e55c95 Gerrit-Change-Number: 21327 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/cannonlake: Add PMC pci drivers
by Lijian Zhao (Code Review) 01 Sep '17

01 Sep '17

Lijian Zhao has uploaded a new patch set (#8). ( https://review.coreboot.org/21251 ) Change subject: soc/intel/cannonlake: Add PMC pci drivers ...................................................................... soc/intel/cannonlake: Add PMC pci drivers Add PMC pci driver on top of PMC common code, also include pmc init code reference from skylake. Change-Id: I95895a3e26cdebd98a4e54720bd4730542707d7e Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/gpio.c M src/soc/intel/cannonlake/include/soc/pmc.h A src/soc/intel/cannonlake/pmc.c 5 files changed, 210 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/21251/8 -- To view, visit https://review.coreboot.org/21251 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I95895a3e26cdebd98a4e54720bd4730542707d7e Gerrit-Change-Number: 21251 Gerrit-PatchSet: 8 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrex Andraos <andrex.andraos(a)intel.corp-partner.google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/gru: Re-enable 3V rail GPIO on Scarlet
by Julius Werner (Code Review) 01 Sep '17

01 Sep '17

Hello Lin Huang, David Schneider, Philip Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/21328 to review the following change. Change subject: google/gru: Re-enable 3V rail GPIO on Scarlet ...................................................................... google/gru: Re-enable 3V rail GPIO on Scarlet We've decided to move control for the 3.0V rail (technically 3.3V on Scarlet, but who cares about millivolts) back to a GPIO on the AP for Scarlet rev2. This patch adds the necessary code to enable it and make ARM TF aware of its existence. Since the pin had previously not been connected to anything, we shouldn't really need to guard this by board ID... older Scarlets will just be twiddling an empty pin. Change-Id: I6037aa486b50119f2c7b859b966cadc3686e3459 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/mainboard/google/gru/board.h M src/mainboard/google/gru/bootblock.c M src/mainboard/google/gru/mainboard.c 3 files changed, 23 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/21328/1 diff --git a/src/mainboard/google/gru/board.h b/src/mainboard/google/gru/board.h index cc7581d..7237d46 100644 --- a/src/mainboard/google/gru/board.h +++ b/src/mainboard/google/gru/board.h @@ -30,7 +30,7 @@ #define GPIO_EC_IRQ GPIO(1, C, 2) #define GPIO_P15V_EN dead_code_t(gpio_t, "PP1500 doesn't exist on Scarlet") #define GPIO_P18V_AUDIO_PWREN dead_code_t(gpio_t, "doesn't exist on Scarlet") -#define GPIO_P30V_EN dead_code_t(gpio_t, "PP3000 doesn't exist on Scarlet") +#define GPIO_P30V_EN GPIO(0, B, 1) #define GPIO_TP_RST_L dead_code_t(gpio_t, "don't need TP_RST_L on Scarlet") #define GPIO_TPM_IRQ GPIO(1, C, 1) #define GPIO_WP GPIO(0, B, 5) diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c index 01aa4bf..a3d3121 100644 --- a/src/mainboard/google/gru/bootblock.c +++ b/src/mainboard/google/gru/bootblock.c @@ -48,12 +48,10 @@ if (IS_ENABLED(CONFIG_BOARD_GOOGLE_SCARLET)) write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 3)); - if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_SCARLET)) { - /* Enable rails powering GPIO blocks, among other things. - These are EC-controlled on Scarlet and already on. */ - gpio_output(GPIO_P15V_EN, 1); - gpio_output(GPIO_P30V_EN, 1); - } + /* Enable rails powering GPIO blocks, among other things. */ + gpio_output(GPIO_P30V_EN, 1); + if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_SCARLET)) + gpio_output(GPIO_P15V_EN, 1); /* Scarlet: EC-controlled */ #if IS_ENABLED(CONFIG_DRIVERS_UART) _Static_assert(CONFIG_CONSOLE_SERIAL_UART_ADDRESS == UART2_BASE, diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index df3df4f..38c2646 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -90,36 +90,27 @@ * with highest voltage first. * Since register_bl31() appends to the front of the list, we need to * register them backwards, with 1.5V coming first. + * 1.5V and 1.8V are EC-controlled on Scarlet, so we skip them. */ - static struct bl31_gpio_param param_p15_en = { - .h = { - .type = PARAM_SUSPEND_GPIO, - }, - .gpio = { - .polarity = BL31_GPIO_LEVEL_LOW, - }, - }; - param_p15_en.gpio.index = GPIO_P15V_EN.raw; - register_bl31_param(&param_p15_en.h); + if (!CONFIG_BOARD_GOOGLE_SCARLET) { + static struct bl31_gpio_param param_p15_en = { + .h = { .type = PARAM_SUSPEND_GPIO }, + .gpio = { .polarity = BL31_GPIO_LEVEL_LOW }, + }; + param_p15_en.gpio.index = GPIO_P15V_EN.raw; + register_bl31_param(&param_p15_en.h); - static struct bl31_gpio_param param_p18_audio_en = { - .h = { - .type = PARAM_SUSPEND_GPIO, - }, - .gpio = { - .polarity = BL31_GPIO_LEVEL_LOW, - }, - }; - param_p18_audio_en.gpio.index = GPIO_P18V_AUDIO_PWREN.raw; - register_bl31_param(&param_p18_audio_en.h); + static struct bl31_gpio_param param_p18_audio_en = { + .h = { .type = PARAM_SUSPEND_GPIO }, + .gpio = { .polarity = BL31_GPIO_LEVEL_LOW }, + }; + param_p18_audio_en.gpio.index = GPIO_P18V_AUDIO_PWREN.raw; + register_bl31_param(&param_p18_audio_en.h); + } static struct bl31_gpio_param param_p30_en = { - .h = { - .type = PARAM_SUSPEND_GPIO, - }, - .gpio = { - .polarity = BL31_GPIO_LEVEL_LOW, - }, + .h = { .type = PARAM_SUSPEND_GPIO }, + .gpio = { .polarity = BL31_GPIO_LEVEL_LOW }, }; param_p30_en.gpio.index = GPIO_P30V_EN.raw; register_bl31_param(&param_p30_en.h); @@ -354,8 +345,8 @@ if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_SCARLET)) { configure_touchpad(); /* Scarlet: works differently */ setup_usb(1); /* Scarlet: only one USB port */ - register_gpio_suspend(); /* Scarlet: all EC-controlled */ } + register_gpio_suspend(); register_reset_to_bl31(); register_poweroff_to_bl31(); register_apio_suspend(); -- To view, visit https://review.coreboot.org/21328 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6037aa486b50119f2c7b859b966cadc3686e3459 Gerrit-Change-Number: 21328 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: David Schneider <dnschneid(a)chromium.org> Gerrit-Reviewer: Lin Huang <hl(a)rock-chips.com> Gerrit-Reviewer: Philip Chen <philipchen(a)chromium.org>

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Change in coreboot[master]: sb/intel/bd82x6x: Revise flash ROM lockdown options
by build bot (Jenkins) (Code Review) 01 Sep '17

01 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21327 ) Change subject: sb/intel/bd82x6x: Revise flash ROM lockdown options ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/59703/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/14977/ : SUCCESS -- To view, visit https://review.coreboot.org/21327 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I435a3b63dd294aa766b1eccf1aa80a7c47e55c95 Gerrit-Change-Number: 21327 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Sep 2017 21:32:46 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/bd82x6x: Revise flash ROM lockdown options
by Nico Huber (Code Review) 01 Sep '17

01 Sep '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21327 Change subject: sb/intel/bd82x6x: Revise flash ROM lockdown options ...................................................................... sb/intel/bd82x6x: Revise flash ROM lockdown options The original options were named and described under the false assumption that the chipset lockdown would only be executed during S3 resume. Fix that. Change-Id: I435a3b63dd294aa766b1eccf1aa80a7c47e55c95 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/finalize.c 2 files changed, 33 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/21327/1 diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 9eb3111..fcaa139 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -75,29 +75,41 @@ if SOUTHBRIDGE_INTEL_BD82X6X || SOUTHBRIDGE_INTEL_C216 || SOUTHBRIDGE_INTEL_IBEXPEAK choice - prompt "Flash ROM locking on S3 resume" - default LOCK_SPI_ON_RESUME_NONE + prompt "Flash ROM locking during chipset lockdown" + default LOCK_SPI_FLASH_NONE -config LOCK_SPI_ON_RESUME_NONE - bool "Don't lock ROM sections on S3 resume" +config LOCK_SPI_FLASH_NONE + bool "Don't lock ROM sections" -config LOCK_SPI_ON_RESUME_RO - bool "Lock all flash ROM sections on S3 resume" +config LOCK_SPI_FLASH_RO + bool "Lock all flash ROM sections" help - If the flash ROM shall be protected against write accesses from the - operating system (OS), the locking procedure has to be repeated after - each resume from S3. Select this if you never want to update the flash - ROM from within your OS. Notice: Even with this option, the write lock - has still to be enabled on the normal boot path (e.g. by the payload). + Select this if you want to write-protect the whole firmware flash + chip. The locking will take place during the chipset lockdown, which + is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) + or has to be triggered later (e.g. by the payload or the OS). -config LOCK_SPI_ON_RESUME_NO_ACCESS - bool "Lock and disable reads all flash ROM sections on S3 resume" + NOTE: If you trigger the chipset lockdown unconditionally, + you won't be able to write to the flash chip using the + internal programmer any more. + +#' fix syntax highlighting + +config LOCK_SPI_FLASH_NO_ACCESS + bool "Lock and disable reads for all flash ROM sections" help - If the flash ROM shall be protected against all accesses from the - operating system (OS), the locking procedure has to be repeated after - each resume from S3. Select this if you never want to update the flash - ROM from within your OS. Notice: Even with this option, the lock - has still to be enabled on the normal boot path (e.g. by the payload). + Select this if you want to protect the firmware flash against all + further accesses (with the exception of the memory mapped BIOS re- + gion which is always readable). The locking will take place during + the chipset lockdown, which is either triggered by coreboot (when + INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g. + by the payload or the OS). + + NOTE: If you trigger the chipset lockdown unconditionally, + you won't be able to write to the flash chip using the + internal programmer any more. + +#' fix syntax highlighting endchoice diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index a9cfa38..fe28af0 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -25,12 +25,13 @@ u16 tco1_cnt; u16 pmbase; - if (CONFIG_LOCK_SPI_ON_RESUME_RO || CONFIG_LOCK_SPI_ON_RESUME_NO_ACCESS) { + if (IS_ENABLED(CONFIG_LOCK_SPI_FLASH_RO) || + IS_ENABLED(CONFIG_LOCK_SPI_FLASH_NO_ACCESS)) { /* Copy flash regions from FREG0-4 to PR0-4 and enable write protection bit31 */ int i; u32 lockmask = (1 << 31); - if (CONFIG_LOCK_SPI_ON_RESUME_NO_ACCESS) + if (IS_ENABLED(CONFIG_LOCK_SPI_FLASH_NO_ACCESS)) lockmask |= (1 << 15); for (i = 0; i < 20; i += 4) RCBA32(0x3874 + i) = RCBA32(0x3854 + i) | lockmask; -- To view, visit https://review.coreboot.org/21327 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I435a3b63dd294aa766b1eccf1aa80a7c47e55c95 Gerrit-Change-Number: 21327 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: nb/intel/common: Write MRC cache at exit of BS_DEV_INIT
by Nico Huber (Code Review) 01 Sep '17

01 Sep '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21326 Change subject: nb/intel/common: Write MRC cache at exit of BS_DEV_INIT ...................................................................... nb/intel/common: Write MRC cache at exit of BS_DEV_INIT We set the SPI lockdown in BS_POST_DEVICE (dev_finalize()) on many plat- forms now. The SPI controller is initialized at start of BS_DEV_INIT (dev_initialize()). The SPI lockdown usually shouldn't be a problem but the SPI driver imple- mentation lacks full support for the locked interface. Also, some options exist to lock all flash regions read-only until the next reboot. Change-Id: Ifda826ae2bb28adcce8dda8e2bb16dc38fe0fe9e Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/northbridge/intel/common/mrc_cache.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/21326/1 diff --git a/src/northbridge/intel/common/mrc_cache.c b/src/northbridge/intel/common/mrc_cache.c index 2fc8d96..f692282 100644 --- a/src/northbridge/intel/common/mrc_cache.c +++ b/src/northbridge/intel/common/mrc_cache.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <cbfs.h> #include <fmap.h> +#include <arch/acpi.h> #include <ip_checksum.h> #include <device/device.h> #include <cbmem.h> @@ -162,6 +163,9 @@ int ret; struct spi_flash flash; + if (acpi_is_wakeup_s3()) + return; + if (!current) { printk(BIOS_ERR, "No MRC cache in cbmem. Can't update flash.\n"); return; @@ -231,7 +235,8 @@ printk(BIOS_DEBUG, "Successfully wrote MRC cache\n"); } -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL); +/* Do it before chipset is locked during BS_POST_DEVICE. */ +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, update_mrc_cache, NULL); struct mrc_data_container *find_current_mrc_cache(void) { -- To view, visit https://review.coreboot.org/21326 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifda826ae2bb28adcce8dda8e2bb16dc38fe0fe9e Gerrit-Change-Number: 21326 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: [WIP] cpu/intel/speedstep: Emit PPKG object for first package
by build bot (Jenkins) (Code Review) 01 Sep '17

01 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21325 ) Change subject: [WIP] cpu/intel/speedstep: Emit PPKG object for first package ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14975/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59701/ : SUCCESS -- To view, visit https://review.coreboot.org/21325 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I89f1ab4be338841463fb95ac75d794103380d16f Gerrit-Change-Number: 21325 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Sep 2017 20:01:23 +0000 Gerrit-HasComments: No

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coreboot-gerrit September 2017