coreboot-gerrit September 2017

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Change in coreboot[master]: [WIP] arch/x86/acpigen: Add function to write a CPU package
by build bot (Jenkins) (Code Review) 01 Sep '17

01 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21324 ) Change subject: [WIP] arch/x86/acpigen: Add function to write a CPU package ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14974/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59702/ : SUCCESS -- To view, visit https://review.coreboot.org/21324 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I10e9ebad84343d1fb282b3fbb28f5f014f664f14 Gerrit-Change-Number: 21324 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Sep 2017 19:42:52 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP] cpu/intel/speedstep: Emit PPKG object for first package
by Nico Huber (Code Review) 01 Sep '17

01 Sep '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21325 Change subject: [WIP] cpu/intel/speedstep: Emit PPKG object for first package ...................................................................... [WIP] cpu/intel/speedstep: Emit PPKG object for first package Change-Id: I89f1ab4be338841463fb95ac75d794103380d16f Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/cpu/intel/speedstep/acpi.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/21325/1 diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index b4aaa87..c154da0 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -161,4 +161,7 @@ acpigen_pop_len(); } } + /* PPKG is usually used for thermal management + of the first and only package. */ + acpigen_write_processor_package("PPKG", 0, cores_per_package); } -- To view, visit https://review.coreboot.org/21325 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I89f1ab4be338841463fb95ac75d794103380d16f Gerrit-Change-Number: 21325 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: [WIP] arch/x86/acpigen: Add function to write a CPU package
by Nico Huber (Code Review) 01 Sep '17

01 Sep '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21324 Change subject: [WIP] arch/x86/acpigen: Add function to write a CPU package ...................................................................... [WIP] arch/x86/acpigen: Add function to write a CPU package Emits a list of CPU cores, e.g. Name (PPKG, Package (2) { \_PR.CP00, \_PR.CP01 }) Change-Id: I10e9ebad84343d1fb282b3fbb28f5f014f664f14 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/arch/x86/acpigen.c M src/arch/x86/include/arch/acpigen.h 2 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/21324/1 diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 758386d..d97723c 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -353,6 +353,23 @@ acpigen_emit_byte(pblock_len); } +void acpigen_write_processor_package(const char *const name, + const size_t first_core, + const size_t core_count) +{ + size_t i; + char pscope[16]; + + acpigen_write_name(name); + acpigen_write_package(core_count); + for (i = first_core; i < core_count; ++i) { + snprintf(pscope, sizeof(pscope), + CONFIG_ACPI_CPU_STRING, (unsigned int)i); + acpigen_emit_namestring(pscope); + } + acpigen_pop_len(); +} + /* * Generate ACPI AML code for OperationRegion * Arg0: Pointer to struct opregion opreg = OPREGION(rname, space, offset, len) diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 37d0d55..68d7957 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -219,6 +219,8 @@ void acpigen_write_CSD_package(u32 domain, u32 numprocs, CSD_coord coordtype, u32 index); void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len); +void acpigen_write_processor_package(const char *name, + size_t first_core, size_t core_count); void acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list); void acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); void acpigen_write_mem32fixed(int readwrite, u32 base, u32 size); -- To view, visit https://review.coreboot.org/21324 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I10e9ebad84343d1fb282b3fbb28f5f014f664f14 Gerrit-Change-Number: 21324 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: soc/intel/cannonlake: Define Max PCIE Root Ports
by build bot (Jenkins) (Code Review) 01 Sep '17

01 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21272 ) Change subject: soc/intel/cannonlake: Define Max PCIE Root Ports ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14973/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59700/ : SUCCESS -- To view, visit https://review.coreboot.org/21272 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id45ff6e96043ed71117018a4e73d08920ae9667e Gerrit-Change-Number: 21272 Gerrit-PatchSet: 2 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Sep 2017 18:24:35 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add Vboot/ChromOS support
by build bot (Jenkins) (Code Review) 01 Sep '17

01 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21280 ) Change subject: soc/intel/cannonlake: Add Vboot/ChromOS support ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14972/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59699/ : SUCCESS -- To view, visit https://review.coreboot.org/21280 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I114a9d6e92b69199ccacc1e7e1535eccc0e2cb99 Gerrit-Change-Number: 21280 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Sep 2017 18:23:15 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add dummy ACPI DSDT table
by build bot (Jenkins) (Code Review) 01 Sep '17

01 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21279 ) Change subject: soc/intel/cannonlake: Add dummy ACPI DSDT table ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14971/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59698/ : SUCCESS -- To view, visit https://review.coreboot.org/21279 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia435f2a03982313c6b0c63ac25668a3300d08793 Gerrit-Change-Number: 21279 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrex Andraos <andrex.andraos(a)intel.corp-partner.google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Sep 2017 17:57:17 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add dummy ACPI DSDT table
by Lijian Zhao (Code Review) 01 Sep '17

01 Sep '17

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/21279 Change subject: soc/intel/cannonlake: Add dummy ACPI DSDT table ...................................................................... soc/intel/cannonlake: Add dummy ACPI DSDT table A dummy DSDT table will be created for cannonlake. Change-Id: Ia435f2a03982313c6b0c63ac25668a3300d08793 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/intel/cannonlake_rvp/Kconfig A src/mainboard/intel/cannonlake_rvp/acpi_tables.c A src/mainboard/intel/cannonlake_rvp/dsdt.asl 3 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/21279/2 diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig index 35afb07..9d2a5f2 100644 --- a/src/mainboard/intel/cannonlake_rvp/Kconfig +++ b/src/mainboard/intel/cannonlake_rvp/Kconfig @@ -4,6 +4,7 @@ def_bool y select BOARD_ROMSIZE_KB_16384 select SOC_INTEL_CANNONLAKE + select HAVE_ACPI_TABLES select GENERIC_SPD_BIN config MAINBOARD_DIR diff --git a/src/mainboard/intel/cannonlake_rvp/acpi_tables.c b/src/mainboard/intel/cannonlake_rvp/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/acpi_tables.c diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl new file mode 100644 index 0000000..410e1ac --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2017 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // global NVS and variables + #include <soc/intel/cannonlake/acpi/globalnvs.asl> + + Scope (\_SB) { + } + +#if IS_ENABLED(CONFIG_CHROMEOS) + // Chrome OS specific + #include <vendorcode/google/chromeos/acpi/chromeos.asl> +#endif +} -- To view, visit https://review.coreboot.org/21279 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia435f2a03982313c6b0c63ac25668a3300d08793 Gerrit-Change-Number: 21279 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrex Andraos <andrex.andraos(a)intel.corp-partner.google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/x4x: Select LAPIC_MONOTONIC_TIMER
by Nico Huber (Code Review) 01 Sep '17

01 Sep '17

Nico Huber has posted comments on this change. ( https://review.coreboot.org/21320 ) Change subject: nb/intel/x4x: Select LAPIC_MONOTONIC_TIMER ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/21320 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I01059c8cbdc6a002dfd75b6da3a629811b137702 Gerrit-Change-Number: 21320 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Sep 2017 17:15:23 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: Kconfig: Move and rename ADD_VBT_DATA_FILE
by build bot (Jenkins) (Code Review) 01 Sep '17

01 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20619 ) Change subject: Kconfig: Move and rename ADD_VBT_DATA_FILE ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/14970/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/59697/ : SUCCESS -- To view, visit https://review.coreboot.org/20619 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I688bac339c32e9c856642a0f4bd5929beef06409 Gerrit-Change-Number: 20619 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 01 Sep 2017 16:16:20 +0000 Gerrit-HasComments: No

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Change in libgfxinit[master]: gma: Add procedure to power up legacy VGA block
by Nico Huber (Code Review) 01 Sep '17

01 Sep '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21323 Change subject: gma: Add procedure to power up legacy VGA block ...................................................................... gma: Add procedure to power up legacy VGA block Calling this is necessary for VGA text mode on at least Skylake, where the legacy VGA registers are inaccessible otherwise. Change-Id: I48ba1738bcc7babd4e666e5266f775dcd06b2a3f Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M common/hw-gfx-gma.adb M common/hw-gfx-gma.ads 2 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/23/21323/1 diff --git a/common/hw-gfx-gma.adb b/common/hw-gfx-gma.adb index 99a1276..6bc6fea 100644 --- a/common/hw-gfx-gma.adb +++ b/common/hw-gfx-gma.adb @@ -438,6 +438,23 @@ ---------------------------------------------------------------------------- + procedure Power_Up_VGA + is + Fake_Config : constant Pipe_Configs := + (Primary => + (Port => Analog, + Framebuffer => HW.GFX.Default_FB, + Mode => HW.GFX.Invalid_Mode), + others => + (Port => Disabled, + Framebuffer => HW.GFX.Default_FB, + Mode => HW.GFX.Invalid_Mode)); + begin + Power_And_Clocks.Power_Up (Cur_Configs, Fake_Config); + end Power_Up_VGA; + + ---------------------------------------------------------------------------- + function FB_First_Page (FB : Framebuffer_Type) return Natural is (Natural (FB.Offset / GTT_Page_Size)); function FB_Pages (FB : Framebuffer_Type) return Natural is diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 3771804..cd992b8 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -80,6 +80,12 @@ Global => (Input => Init_State); pragma Warnings (GNATprove, On, "unused variable ""Write_Delay"""); + pragma Warnings (GNATprove, Off, "subprogram ""Power_Up_VGA"" has no effect", + Reason => "Effect depends on the platform compiled for"); + procedure Power_Up_VGA + with + Pre => Is_Initialized; + procedure Update_Outputs (Configs : Pipe_Configs); pragma Warnings (GNATprove, Off, "subprogram ""Dump_Configs"" has no effect", -- To view, visit https://review.coreboot.org/21323 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I48ba1738bcc7babd4e666e5266f775dcd06b2a3f Gerrit-Change-Number: 21323 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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coreboot-gerrit September 2017