Subrata Banik has posted comments on this change. ( https://review.coreboot.org/21459 )
Change subject: mainboard/intel/cannonlake_rvp: Set LPSS UART2 to hidden
......................................................................
Patch Set 1:
> (1 comment)
Why we are not setting UPD as PCI mode and take advantage of below code as coreboot already initialize LPSS UART 2 device in PCI mode in bootblock
case PchSerialIoPci:
//
// Check If device is already initialized
//
if (PciSegmentRead32 (PciCfgBase + PCI_BASE_ADDRESSREG_OFFSET) & 0xFFFFF000) {
return;
}
Then it has to return rather doing further legacy programming if i use your CL that mean since BB till FSP-S entry we are in 32 bit mode and at exist we are in 8 bit mode again. Because if policy is
if (DeviceMode == PchSerialIoHidden) {
Data32Or = (B_SERIAL_IO_PCR_GPPRVRW7_UART0_BYTE_ADDR_EN << (Controller - PchSerialIoIndexUart0));
}
then only FSP will set into leagcy 16550 - 8bit mode.
If you still have confusion then raise HSD, i will try to clarify but i don't think this CL make sense
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/21459 )
Change subject: mainboard/intel/cannonlake_rvp: Set LPSS UART2 to hidden
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/21459/1//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/21459/1//COMMIT_MSG@9
PS1, Line 9: If LPSS UART port had been set up to hidden mode, FSP will not force
: 8 bit transition mode (AKA 16550 compatible UART mode).
FSP should not force UART in 8 bit mode unless its Legacy UART configuration.If you see that after you set UART as PCI and still FSP is doing legacy 8 bit mode program then please raise a FSP bug and give me. I don't see such case and in my FSP code, i could see PChSerialIoSkip option which allow FSP to skip UART programming.
The problem with this CL is that, your kernel will unable to bind serial driver hence serial log or login console will be at risk.
I don't understand the point of digressing so much from SKL/KBL coreboot implementation for CNL when its same IP and no change in serial debug from SOC or BIOS.
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