coreboot-gerrit September 2017

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Change in coreboot[master]: nb/intel/i945/raminit.c: Clean sdram_program_dram_width()
by build bot (Jenkins) (Code Review) 09 Sep '17

09 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21472 ) Change subject: nb/intel/i945/raminit.c: Clean sdram_program_dram_width() ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15403/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60172/ : SUCCESS -- To view, visit https://review.coreboot.org/21472 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ife1aff0a5cf311881b3a11533b71a74c518a633f Gerrit-Change-Number: 21472 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Sep 2017 18:25:41 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/i945/raminit.c: Clean sdram_program_dram_width()
by HAOUAS Elyes (Code Review) 09 Sep '17

09 Sep '17

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/21472 Change subject: nb/intel/i945/raminit.c: Clean sdram_program_dram_width() ...................................................................... nb/intel/i945/raminit.c: Clean sdram_program_dram_width() Use macro instead of numbers Change-Id: Ife1aff0a5cf311881b3a11533b71a74c518a633f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 20 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/21472/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 8fe589b..f10f108 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -880,29 +880,29 @@ idx = 1; switch (sysinfo->dimm[0]) { - case 0: - c0dramw = 0x0000; break; /* x16DS */ - case 1: - c0dramw = 0x0001; break; /* x8DS */ - case 2: - c0dramw = 0x0000; break; /* x16SS */ - case 3: - c0dramw = 0x0005; break; /* x8DDS */ - case 4: - c0dramw = 0x0000; break; /* NC */ + case SYSINFO_DIMM_X16DS: + c0dramw = 0x0000; break; + case SYSINFO_DIMM_X8DS: + c0dramw = 0x0001; break; + case SYSINFO_DIMM_X16SS: + c0dramw = 0x0000; break; + case SYSINFO_DIMM_X8DDS: + c0dramw = 0x0005; break; + case SYSINFO_DIMM_NOT_POPULATED: + c0dramw = 0x0000; break; } switch (sysinfo->dimm[idx]) { - case 0: - c1dramw = 0x0000; break; /* x16DS */ - case 1: - c1dramw = 0x0010; break; /* x8DS */ - case 2: - c1dramw = 0x0000; break; /* x16SS */ - case 3: - c1dramw = 0x0050; break; /* x8DDS */ - case 4: - c1dramw = 0x0000; break; /* NC */ + case SYSINFO_DIMM_X16DS: + c1dramw = 0x0000; break; + case SYSINFO_DIMM_X8DS: + c1dramw = 0x0010; break; + case SYSINFO_DIMM_X16SS: + c1dramw = 0x0000; break; + case SYSINFO_DIMM_X8DDS: + c1dramw = 0x0050; break; + case SYSINFO_DIMM_NOT_POPULATED: + c1dramw = 0x0000; break; } if (!sdram_capabilities_dual_channel()) { -- To view, visit https://review.coreboot.org/21472 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ife1aff0a5cf311881b3a11533b71a74c518a633f Gerrit-Change-Number: 21472 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr>

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Change in coreboot[master]: nb/intel/i945: Clear timeout bits after disabling watchdog
by build bot (Jenkins) (Code Review) 09 Sep '17

09 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21471 ) Change subject: nb/intel/i945: Clear timeout bits after disabling watchdog ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15402/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60171/ : SUCCESS -- To view, visit https://review.coreboot.org/21471 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If9f93fcc96827bb192148a80b4476796c9358a7a Gerrit-Change-Number: 21471 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Sep 2017 18:19:22 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/i945: Clear timeout bits after disabling watchdog
by Nico Huber (Code Review) 09 Sep '17

09 Sep '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/21471 Change subject: nb/intel/i945: Clear timeout bits after disabling watchdog ...................................................................... nb/intel/i945: Clear timeout bits after disabling watchdog Even with the watchdog disabled, these bits influence other hardware blocks (e.g. SECOND_TO_STS stops SMBus block transfers, possibly yet before they started). Change-Id: If9f93fcc96827bb192148a80b4476796c9358a7a Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/northbridge/intel/i945/early_init.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/21471/1 diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 1d473d3..f25d13b 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -170,6 +170,8 @@ printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ + outw((1 << 3), DEFAULT_PMBASE | 0x60 | 0x04); /* clear timeout */ + outw((1 << 1), DEFAULT_PMBASE | 0x60 | 0x06); /* clear second timeout */ printk(BIOS_DEBUG, " done.\n"); /* Enable upper 128bytes of CMOS */ -- To view, visit https://review.coreboot.org/21471 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If9f93fcc96827bb192148a80b4476796c9358a7a Gerrit-Change-Number: 21471 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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Change in coreboot[master]: sb/intel/i82371eb: Consolidate bootblock.c logic
by build bot (Jenkins) (Code Review) 09 Sep '17

09 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21468 ) Change subject: sb/intel/i82371eb: Consolidate bootblock.c logic ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15399/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60168/ : SUCCESS -- To view, visit https://review.coreboot.org/21468 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I07a5a28c91da9586e3bdaaf4521cba3f53a5cc01 Gerrit-Change-Number: 21468 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Sep 2017 15:58:13 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/i82371eb: Consolidate bootblock.c logic
by Keith Hui (Code Review) 09 Sep '17

09 Sep '17

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/21468 Change subject: sb/intel/i82371eb: Consolidate bootblock.c logic ...................................................................... sb/intel/i82371eb: Consolidate bootblock.c logic The southbridge bootblock entry point bootblock_southbridge_init() just calls i82371eb_enable_rom() which does all the work. Move all that code into bootblock_southbridge_init() and drop the second function. Plus combine the 3 lines that set 3 bits in XBCS into one. Change-Id: I07a5a28c91da9586e3bdaaf4521cba3f53a5cc01 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/i82371eb/bootblock.c 1 file changed, 2 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/21468/1 diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index 07f94f3..6f52aa7 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -19,7 +19,7 @@ #include <device/pci_ids.h> #include "i82371eb.h" -static void i82371eb_enable_rom(void) +static void bootblock_southbridge_init(void) { u16 reg16; pci_devfn_t dev; @@ -36,14 +36,7 @@ /* Enable access to the whole ROM, disable ROM write access. */ reg16 = pci_read_config16(dev, XBCS); - reg16 |= LOWER_BIOS_ENABLE; - reg16 |= EXT_BIOS_ENABLE; - reg16 |= EXT_BIOS_ENABLE_1MB; + reg16 |= (LOWER_BIOS_ENABLE | EXT_BIOS_ENABLE | EXT_BIOS_ENABLE_1MB); reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */ pci_write_config16(dev, XBCS, reg16); -} - -static void bootblock_southbridge_init(void) -{ - i82371eb_enable_rom(); } -- To view, visit https://review.coreboot.org/21468 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I07a5a28c91da9586e3bdaaf4521cba3f53a5cc01 Gerrit-Change-Number: 21468 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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Change in coreboot[master]: nb/i945/raminit: Use common ddr2 decode functions
by build bot (Jenkins) (Code Review) 09 Sep '17

09 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18305 ) Change subject: nb/i945/raminit: Use common ddr2 decode functions ...................................................................... Patch Set 54: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15398/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60167/ : SUCCESS -- To view, visit https://review.coreboot.org/18305 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I97c93939d11807752797785dd88c70b43a236ee3 Gerrit-Change-Number: 18305 Gerrit-PatchSet: 54 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Comment-Date: Sat, 09 Sep 2017 14:18:13 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/i945/raminit: Use common ddr2 decode functions
by build bot (Jenkins) (Code Review) 09 Sep '17

09 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18305 ) Change subject: nb/i945/raminit: Use common ddr2 decode functions ...................................................................... Patch Set 53: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/60165/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/15396/ : SUCCESS -- To view, visit https://review.coreboot.org/18305 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I97c93939d11807752797785dd88c70b43a236ee3 Gerrit-Change-Number: 18305 Gerrit-PatchSet: 53 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Comment-Date: Sat, 09 Sep 2017 13:36:36 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/asrock/g41c-gs: Add IO decode range for SIO HWMON
by build bot (Jenkins) (Code Review) 09 Sep '17

09 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21464 ) Change subject: mb/asrock/g41c-gs: Add IO decode range for SIO HWMON ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15395/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60164/ : SUCCESS -- To view, visit https://review.coreboot.org/21464 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic02c3a6265f11c1571369bc04371d28b6f989736 Gerrit-Change-Number: 21464 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Sep 2017 12:48:45 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/soraka: Update DPTF parameters
by Sumeet R Pawnikar (Code Review) 09 Sep '17

09 Sep '17

Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/21453 ) Change subject: mb/google/soraka: Update DPTF parameters ...................................................................... Patch Set 3: Code-Review-1 Measured performance regression with this CL, details updated on Bug. -- To view, visit https://review.coreboot.org/21453 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6af93fa358a037df2088213ee4df5e2cfd047590 Gerrit-Change-Number: 21453 Gerrit-PatchSet: 3 Gerrit-Owner: Wisley Chen <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Sep 2017 12:36:06 +0000 Gerrit-HasComments: No

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coreboot-gerrit September 2017