coreboot-gerrit September 2017

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Change in coreboot[master]: device/dram/ddr2.c: Improve error returning and debug output
by Nico Huber (Code Review) 10 Sep '17

10 Sep '17

Nico Huber has posted comments on this change. ( https://review.coreboot.org/21480 ) Change subject: device/dram/ddr2.c: Improve error returning and debug output ...................................................................... Patch Set 2: (7 comments) Thanks for taking this up. https://review.coreboot.org/#/c/21480/2/src/device/dram/ddr2.c File src/device/dram/ddr2.c: https://review.coreboot.org/#/c/21480/2/src/device/dram/ddr2.c@116 PS2, Line 116: static int spd_decode_tck_time(u8 c, u32 *tck) I'd prefer the pointer to be the first argument (old writel vs write32 debate). https://review.coreboot.org/#/c/21480/2/src/device/dram/ddr2.c@119 PS2, Line 119: int ret = CB_SUCCESS; We could just bail out directly and drop the variable. Not writing `*tck` isn't bad, IMO. Just a matter of personal preference, I guess. https://review.coreboot.org/#/c/21480/2/src/device/dram/ddr2.c@155 PS2, Line 155: * Returns cycle time in 1/256th ns. (I hate comments) https://review.coreboot.org/#/c/21480/2/src/device/dram/ddr2.c@157 PS2, Line 157: u32 nit, er, int ;) https://review.coreboot.org/#/c/21480/2/src/device/dram/ddr2.c@350 PS2, Line 350: printk(BIOS_WARNING, " Invalid number of memory rows\n"); I don't think, we should keep the indent. With low loglevel, the message would be freestanding. Also we might want to give some context for that case, e.g. "... in SPD" or "SPD decode: ..."? https://review.coreboot.org/#/c/21480/2/src/device/dram/ddr2.c@440 PS2, Line 440: if (spd_decode_bcd_time(spd[10], &dimm->access_time[cl]) != CB_SUCCESS) { line is too long https://review.coreboot.org/#/c/21480/2/src/device/dram/ddr2.c@480 PS2, Line 480: printk(BIOS_WARNING," Invalid rank density.\n"); space after comma, no space before the output? -- To view, visit https://review.coreboot.org/21480 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iee434d1fa1a9d911cc3683b88b260881ed6434ea Gerrit-Change-Number: 21480 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 10 Sep 2017 19:35:01 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: nb/i945/raminit: Use common ddr2 decode functions
by build bot (Jenkins) (Code Review) 10 Sep '17

10 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18305 ) Change subject: nb/i945/raminit: Use common ddr2 decode functions ...................................................................... Patch Set 55: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/60208/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/15435/ : SUCCESS -- To view, visit https://review.coreboot.org/18305 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I97c93939d11807752797785dd88c70b43a236ee3 Gerrit-Change-Number: 18305 Gerrit-PatchSet: 55 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Comment-Date: Sun, 10 Sep 2017 19:18:31 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: device/dram/ddr2.c: Improve error returning and debug output
by build bot (Jenkins) (Code Review) 10 Sep '17

10 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21480 ) Change subject: device/dram/ddr2.c: Improve error returning and debug output ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/60209/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/15436/ : SUCCESS -- To view, visit https://review.coreboot.org/21480 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iee434d1fa1a9d911cc3683b88b260881ed6434ea Gerrit-Change-Number: 21480 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 10 Sep 2017 19:18:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: device/dram/ddr2.c: Improve error returning and debug output
by Arthur Heymans (Code Review) 10 Sep '17

10 Sep '17

Hello Patrick Rudolph, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/21480 to look at the new patch set (#3). Change subject: device/dram/ddr2.c: Improve error returning and debug output ...................................................................... device/dram/ddr2.c: Improve error returning and debug output This patch outputs decoding errors with BIOS_WARNING instead of depending on CONFIG_DEBUG_RAM_SETUP. Returns SPD_STATUS_INVALID on invalid settings for tRR, bcd and tCK. Change-Id: Iee434d1fa1a9d911cc3683b88b260881ed6434ea Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/device/dram/ddr2.c 1 file changed, 87 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/21480/3 -- To view, visit https://review.coreboot.org/21480 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iee434d1fa1a9d911cc3683b88b260881ed6434ea Gerrit-Change-Number: 21480 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: device/dram/ddr2.c: Improve error returning and debug output
by Arthur Heymans (Code Review) 10 Sep '17

10 Sep '17

Hello Patrick Rudolph, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/21480 to look at the new patch set (#2). Change subject: device/dram/ddr2.c: Improve error returning and debug output ...................................................................... device/dram/ddr2.c: Improve error returning and debug output This patch outputs decoding errors with BIOS_WARNING instead of depending on CONFIG_DEBUG_RAM_SETUP. Returns SPD_STATUS_INVALID on invalid settings for tRR, bcd and tCK. Change-Id: Iee434d1fa1a9d911cc3683b88b260881ed6434ea Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/device/dram/ddr2.c 1 file changed, 88 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/21480/2 -- To view, visit https://review.coreboot.org/21480 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iee434d1fa1a9d911cc3683b88b260881ed6434ea Gerrit-Change-Number: 21480 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: device/dram/ddr2.c: Improve error returning and debug output
by build bot (Jenkins) (Code Review) 10 Sep '17

10 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21480 ) Change subject: device/dram/ddr2.c: Improve error returning and debug output ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/60207/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/15434/ : SUCCESS -- To view, visit https://review.coreboot.org/21480 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iee434d1fa1a9d911cc3683b88b260881ed6434ea Gerrit-Change-Number: 21480 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 10 Sep 2017 19:05:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: device/dram/ddr2.c: Improve error returning and debug output
by Arthur Heymans (Code Review) 10 Sep '17

10 Sep '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/21480 Change subject: device/dram/ddr2.c: Improve error returning and debug output ...................................................................... device/dram/ddr2.c: Improve error returning and debug output This patch outputs decoding errors with BIOS_WARNING instead of depending on CONFIG_DEBUG_RAM_SETUP. Returns SPD_STATUS_INVALID on invalid settings for tRR, bcd and tCK. Change-Id: Iee434d1fa1a9d911cc3683b88b260881ed6434ea Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/device/dram/ddr2.c 1 file changed, 88 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/21480/1 diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index 62c1079..aa6027f 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -113,9 +113,10 @@ * Decodes a raw SPD data from a DDR2 DIMM. * Returns cycle time in 1/256th ns. */ -static u32 spd_decode_tck_time(u8 c) +static int spd_decode_tck_time(u8 c, u32 *tck) { u8 high, low; + int ret = CB_SUCCESS; high = c >> 4; @@ -132,11 +133,19 @@ case 0xd: low = 75; break; + case 0xe: + case 0xf: + printk(BIOS_WARNING, "Invalid tck setting. " + "Using 0 for lower nibble\n"); + low = 0; + ret = CB_ERR; + break; default: low = (c & 0xf) * 10; } - return ((high * 100 + low) << 8) / 100; + *tck = ((high * 100 + low) << 8) / 100; + return ret; } /** @@ -145,14 +154,18 @@ * Decodes a raw SPD data from a DDR2 DIMM. * Returns cycle time in 1/256th ns. */ -static u32 spd_decode_bcd_time(u8 c) +static u32 spd_decode_bcd_time(u8 c, u32 *bcd) { u8 high, low; + int ret = CB_SUCCESS; high = c >> 4; low = c & 0xf; + if (high > 10 || low > 10) + ret = CB_ERR; - return ((high * 10 + low) << 8) / 100; + *bcd = ((high * 10 + low) << 8) / 100; + return ret; } /** @@ -177,26 +190,29 @@ * Decodes a raw SPD data from a DDR2 DIMM. * Returns cycle time in 1/256th us. */ -static u32 spd_decode_tRR_time(u8 c) +static int spd_decode_tRR_time(u8 c, u32 *tRR) { + int ret = CB_SUCCESS; switch (c) { default: - printk(BIOS_DEBUG, + printk(BIOS_WARNING, "Unknown tRR value, using default of 15.6us."); + ret = CB_ERR; /* Fallthrough */ case 0x80: - return 15625 << 8; + *tRR = 15625 << 8; case 0x81: - return 15625 << 6; + *tRR = 15625 << 6; case 0x82: - return 15625 << 7; + *tRR = 15625 << 7; case 0x83: - return 15625 << 9; + *tRR = 15625 << 9; case 0x84: - return 15625 << 10; + *tRR = 15625 << 10; case 0x85: - return 15625 << 11; + *tRR = 15625 << 11; } + return ret; } /** @@ -297,20 +313,20 @@ printram("SPD contains 0x%02x bytes\n", spd_size); if (spd_size < 64 || eeprom_size < 64) { - printram("ERROR: SPD to small\n"); + printk(BIOS_WARNING, "ERROR: SPD to small\n"); dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; return SPD_STATUS_INVALID; } if (spd_ddr2_calc_checksum(spd, spd_size) != spd[63]) { - printram("ERROR: SPD checksum error\n"); + printk(BIOS_WARNING, "ERROR: SPD checksum error\n"); dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; return SPD_STATUS_CRC_ERROR; } reg8 = spd[62]; if ((reg8 & 0xf0) != 0x10) { - printram("ERROR: Unsupported SPD revision %01x.%01x\n", + printk(BIOS_WARNING, "ERROR: Unsupported SPD revision %01x.%01x\n", reg8 >> 4, reg8 & 0xf); dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; return SPD_STATUS_INVALID; @@ -321,7 +337,7 @@ reg8 = spd[2]; printram(" Type : 0x%02x\n", reg8); if (reg8 != 0x08) { - printram("ERROR: Unsupported SPD type %x\n", reg8); + printk(BIOS_WARNING, "ERROR: Unsupported SPD type %x\n", reg8); dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; return SPD_STATUS_INVALID; } @@ -331,14 +347,14 @@ printram(" Rows : %u\n", dimm->row_bits); if ((dimm->row_bits > 31) || ((dimm->row_bits > 15) && (dimm->rev < 0x13))) { - printram(" Invalid number of memory rows\n"); + printk(BIOS_WARNING, " Invalid number of memory rows\n"); ret = SPD_STATUS_INVALID_FIELD; } dimm->col_bits = spd[4]; printram(" Columns : %u\n", dimm->col_bits); if (dimm->col_bits > 15) { - printram(" Invalid number of memory columns\n"); + printk(BIOS_WARNING, " Invalid number of memory columns\n"); ret = SPD_STATUS_INVALID_FIELD; } @@ -348,21 +364,21 @@ dimm->mod_width = spd[6]; printram(" Module data width : x%u\n", dimm->mod_width); if (!dimm->mod_width) { - printram(" Invalid module data width\n"); + printk(BIOS_WARNING, " Invalid module data width\n"); ret = SPD_STATUS_INVALID_FIELD; } dimm->width = spd[13]; printram(" SDRAM width : x%u\n", dimm->width); if (!dimm->width) { - printram(" Invalid SDRAM width\n"); + printk(BIOS_WARNING, " Invalid SDRAM width\n"); ret = SPD_STATUS_INVALID_FIELD; } dimm->banks = spd[17]; printram(" Banks : %u\n", dimm->banks); if (!dimm->banks) { - printram(" Invalid module banks count\n"); + printk(BIOS_WARNING, " Invalid module banks count\n"); ret = SPD_STATUS_INVALID_FIELD; } @@ -392,23 +408,23 @@ printram(" Voltage : 1.8V\n"); break; default: - printram(" Unknown voltage level.\n"); + printk(BIOS_WARNING, " Unknown voltage level.\n"); ret = SPD_STATUS_INVALID_FIELD; } dimm->cas_supported = spd[18]; if ((dimm->cas_supported & 0x3) || !dimm->cas_supported) { - printram(" Invalid CAS support advertised.\n"); + printk(BIOS_WARNING, " Invalid CAS support advertised.\n"); ret = SPD_STATUS_INVALID_FIELD; } printram(" Supported CAS mask : 0x%x\n", dimm->cas_supported); if ((dimm->rev < 0x13) && (dimm->cas_supported & 0x80)) { - printram(" Invalid CAS support advertised.\n"); + printk(BIOS_WARNING, " Invalid CAS support advertised.\n"); ret = SPD_STATUS_INVALID_FIELD; } if ((dimm->rev < 0x12) && (dimm->cas_supported & 0x40)) { - printram(" Invalid CAS support advertised.\n"); + printk(BIOS_WARNING, " Invalid CAS support advertised.\n"); ret = SPD_STATUS_INVALID_FIELD; } @@ -416,26 +432,52 @@ cl = spd_get_msbs(dimm->cas_supported); /* SDRAM Cycle time at Maximum Supported CAS Latency (CL), CL=X */ - dimm->cycle_time[cl] = spd_decode_tck_time(spd[9]); + if (spd_decode_tck_time(spd[9], &dimm->cycle_time[cl]) != CB_SUCCESS) { + printk(BIOS_WARNING, "Invalid min tCL for CAS%d\n", cl); + ret = SPD_STATUS_INVALID_FIELD; + } /* SDRAM Access from Clock */ - dimm->access_time[cl] = spd_decode_bcd_time(spd[10]); + if (spd_decode_bcd_time(spd[10], &dimm->access_time[cl]) != CB_SUCCESS) { + printk(BIOS_WARNING, "Invalid min tAC for CAS%d\n", cl); + ret = SPD_STATUS_INVALID_FIELD; + } if (dimm->cas_supported & (1 << (cl - 1))) { /* Minimum Clock Cycle at CLX-1 */ - dimm->cycle_time[cl - 1] = spd_decode_tck_time(spd[23]); + if (spd_decode_tck_time(spd[23], &dimm->cycle_time[cl - 1]) + != CB_SUCCESS) { + printk(BIOS_WARNING, "Invalid min tCL for CAS%d\n", + cl - 1); + ret = SPD_STATUS_INVALID_FIELD; + } /* Maximum Data Access Time (tAC) from Clock at CLX-1 */ - dimm->access_time[cl - 1] = spd_decode_bcd_time(spd[24]); + if (spd_decode_bcd_time(spd[24], &dimm->access_time[cl - 1]) + != CB_SUCCESS) { + printk(BIOS_WARNING, "Invalid min tAC for CAS%d\n", + cl - 1); + ret = SPD_STATUS_INVALID_FIELD; + } } if (dimm->cas_supported & (1 << (cl - 2))) { /* Minimum Clock Cycle at CLX-2 */ - dimm->cycle_time[cl - 2] = spd_decode_tck_time(spd[25]); + if (spd_decode_tck_time(spd[25], &dimm->cycle_time[cl - 2]) + != CB_SUCCESS) { + printk(BIOS_WARNING, "Invalid min tCL for CAS%d\n", + cl - 2); + ret = SPD_STATUS_INVALID_FIELD; + } /* Maximum Data Access Time (tAC) from Clock at CLX-2 */ - dimm->access_time[cl - 2] = spd_decode_bcd_time(spd[26]); + if (spd_decode_bcd_time(spd[26], &dimm->access_time[cl - 2]) + != CB_SUCCESS) { + printk(BIOS_WARNING, "Invalid min tAC for CAS%d\n", cl - 2); + ret = SPD_STATUS_INVALID_FIELD; + } + } reg8 = (spd[31] >> 5) | (spd[31] << 3); if (!reg8) { - printram(" Invalid rank density.\n"); + printk(BIOS_WARNING," Invalid rank density.\n"); ret = SPD_STATUS_INVALID_FIELD; } @@ -449,7 +491,10 @@ printram(" Capacity : %u GB\n", dimm->size_mb >> 10); /* SDRAM Maximum Cycle Time (tCKmax) */ - dimm->tCK = spd_decode_tck_time(spd[43]); + if (spd_decode_bcd_time(spd[43], &dimm->tCK) != CB_SUCCESS) { + printk(BIOS_WARNING, "Invalid Max tCK\n"); + ret = SPD_STATUS_INVALID_FIELD; + } /* Minimum Write Recovery Time (tWRmin) */ dimm->tWR = spd_decode_quarter_time(spd[36]); /* Minimum RAS# to CAS# Delay Time (tRCDmin) */ @@ -468,9 +513,15 @@ /* Minimum Internal Read to Precharge Command Delay Time (tRTPmin) */ dimm->tRTP = spd_decode_quarter_time(spd[38]); /* Data Input Setup Time Before Strobe */ - dimm->tDS = spd_decode_bcd_time(spd[34]); + if (spd_decode_bcd_time(spd[34], &dimm->tDS) != CB_SUCCESS) { + printk(BIOS_WARNING, "Invalid tDS\n"); + ret = SPD_STATUS_INVALID_FIELD; + } /* Data Input Hold Time After Strobe */ - dimm->tDH = spd_decode_bcd_time(spd[35]); + if (spd_decode_bcd_time(spd[35], &dimm->tDH) != CB_SUCCESS) { + printk(BIOS_WARNING, "Invalid tDH\n"); + ret = SPD_STATUS_INVALID_FIELD; + } /* SDRAM Device DQS-DQ Skew for DQS and associated DQ signals */ dimm->tDQSQ = (spd[44] << 8) / 100; /* SDRAM Device Maximum Read Data Hold Skew Factor */ @@ -478,7 +529,8 @@ /* PLL Relock Time in us */ dimm->tPLL = spd[46] << 8; /* Refresh rate in us */ - dimm->tRR = spd_decode_tRR_time(spd[12]); + if (spd_decode_tRR_time(spd[12], &dimm->tRR) != CB_SUCCESS) + ret = SPD_STATUS_INVALID_FIELD; /* Number of PLLs on DIMM */ if (dimm->rev >= 0x11) -- To view, visit https://review.coreboot.org/21480 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iee434d1fa1a9d911cc3683b88b260881ed6434ea Gerrit-Change-Number: 21480 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: [WIP] soc/intel/skylake: Hook up libgfxinit
by build bot (Jenkins) (Code Review) 10 Sep '17

10 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20113 ) Change subject: [WIP] soc/intel/skylake: Hook up libgfxinit ...................................................................... Patch Set 4: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/60206/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/15433/ : SUCCESS -- To view, visit https://review.coreboot.org/20113 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I79fbfed7732cf02d054530ea7ec0d34de32836ba Gerrit-Change-Number: 20113 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 10 Sep 2017 18:23:59 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: ifdtool: port the feature to set AltMeDisable/HAP bit here
by build bot (Jenkins) (Code Review) 10 Sep '17

10 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21437 ) Change subject: ifdtool: port the feature to set AltMeDisable/HAP bit here ...................................................................... Patch Set 9: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15424/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60197/ : SUCCESS -- To view, visit https://review.coreboot.org/21437 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9a2ecc60cfbb9ee9d96f15be3d53226cb428729a Gerrit-Change-Number: 21437 Gerrit-PatchSet: 9 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 10 Sep 2017 08:30:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: ifdtool: refactor region_name(s) and new_layout
by build bot (Jenkins) (Code Review) 10 Sep '17

10 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21315 ) Change subject: ifdtool: refactor region_name(s) and new_layout ...................................................................... Patch Set 24: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15422/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60196/ : SUCCESS -- To view, visit https://review.coreboot.org/21315 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia2b92c3f835f9849a243a48c37588c2dbe7449bf Gerrit-Change-Number: 21315 Gerrit-PatchSet: 24 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 10 Sep 2017 08:27:14 +0000 Gerrit-HasComments: No

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coreboot-gerrit September 2017