coreboot-gerrit September 2017

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Change in coreboot[master]: mb/asrock/g41c-gs: Add IO decode range for SIO HWMON
by Arthur Heymans (Code Review) 09 Sep '17

09 Sep '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/21464 to look at the new patch set (#3). Change subject: mb/asrock/g41c-gs: Add IO decode range for SIO HWMON ...................................................................... mb/asrock/g41c-gs: Add IO decode range for SIO HWMON Change-Id: Ic02c3a6265f11c1571369bc04371d28b6f989736 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asrock/g41c-gs/romstage.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/21464/3 -- To view, visit https://review.coreboot.org/21464 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic02c3a6265f11c1571369bc04371d28b6f989736 Gerrit-Change-Number: 21464 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/bd82x6x: Add Timestamp around ME DRAM update
by build bot (Jenkins) (Code Review) 09 Sep '17

09 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21465 ) Change subject: sb/intel/bd82x6x: Add Timestamp around ME DRAM update ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15386/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60155/ : SUCCESS -- To view, visit https://review.coreboot.org/21465 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie228e12a75d373b4f406b3595e1fb1aab41aa5df Gerrit-Change-Number: 21465 Gerrit-PatchSet: 2 Gerrit-Owner: Nathaniel Roach <nroach44(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Sep 2017 12:25:05 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/bd82x6x: Add Timestamp around ME DRAM update
by Nathaniel Roach (Code Review) 09 Sep '17

09 Sep '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/21465 to look at the new patch set (#2). Change subject: sb/intel/bd82x6x: Add Timestamp around ME DRAM update ...................................................................... sb/intel/bd82x6x: Add Timestamp around ME DRAM update Add a timestamp before and after waiting for the ME to acknowledge the DRAM being ready. This allows easier debugging during use of me_cleaner and/or alternate ME images. Change-Id: Ie228e12a75d373b4f406b3595e1fb1aab41aa5df Signed-off-by: Nathaniel Roach <nroach44(a)gmail.com> --- M src/commonlib/include/commonlib/timestamp_serialized.h M src/southbridge/intel/bd82x6x/early_me.c 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/21465/2 -- To view, visit https://review.coreboot.org/21465 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ie228e12a75d373b4f406b3595e1fb1aab41aa5df Gerrit-Change-Number: 21465 Gerrit-PatchSet: 2 Gerrit-Owner: Nathaniel Roach <nroach44(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/bd82x6x: Add Timestamp around ME DRAM update
by build bot (Jenkins) (Code Review) 09 Sep '17

09 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21465 ) Change subject: sb/intel/bd82x6x: Add Timestamp around ME DRAM update ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/60147/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/15378/ : SUCCESS -- To view, visit https://review.coreboot.org/21465 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie228e12a75d373b4f406b3595e1fb1aab41aa5df Gerrit-Change-Number: 21465 Gerrit-PatchSet: 1 Gerrit-Owner: Nathaniel Roach <nroach44(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Sep 2017 12:04:38 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/bd82x6x: Add Awareness of ME's AltDisable
by build bot (Jenkins) (Code Review) 09 Sep '17

09 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21466 ) Change subject: sb/intel/bd82x6x: Add Awareness of ME's AltDisable ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/60148/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/15379/ : SUCCESS -- To view, visit https://review.coreboot.org/21466 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifdda6b2dbb8ae3a650be6d5df6c60475a3fa74aa Gerrit-Change-Number: 21466 Gerrit-PatchSet: 1 Gerrit-Owner: Nathaniel Roach <nroach44(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Sep 2017 12:01:29 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/bd82x6x: Add Awareness of ME's AltDisable
by Nathaniel Roach (Code Review) 09 Sep '17

09 Sep '17

Nathaniel Roach has uploaded this change for review. ( https://review.coreboot.org/21466 Change subject: sb/intel/bd82x6x: Add Awareness of ME's AltDisable ...................................................................... sb/intel/bd82x6x: Add Awareness of ME's AltDisable me_cleaner now allows setting a bit in the PCH straps - AltDisableBit tells the ME to stop execution after BUP - disabling the 30 minute watchdog - but also "breaking" the ME. The ME reports OpMode = 2. This means the ME will not respond when we wait for an acknowledgement about the DRAM being ready. Change the label for OpMode = 2 from DEBUG to DISABLE, and when DISABLEd, don't wait for a response to the DRAM notification. Change-Id: Ifdda6b2dbb8ae3a650be6d5df6c60475a3fa74aa Signed-off-by: Nathaniel Roach <nroach44(a)gmail.com> --- M src/southbridge/intel/bd82x6x/early_me.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/me_8.x.c 4 files changed, 16 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/21466/1 diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index b2e9200..48595ee 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -191,18 +191,22 @@ meDID = did.uma_base | (1 << 28);// | (1 << 23); pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_ME_H_GS, meDID); - timestamp_add_now(TS_ME_INFORM_DRAM_WAIT); - udelay(1100); - /* Must wait for ME acknowledgement */ - millisec = 0; - hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24; - while ((((hfs & 0xf0) >> 4) != ME_HFS_BIOS_DRAM_ACK) && (millisec < 5000)) { - udelay(1000); + if (opmode == ME_HFS_MODE_DISABLED) { + printk(BIOS_NOTICE, "ME: ME is reporting as disabled, so not waiting for a response.\n"); + } else { + timestamp_add_now(TS_ME_INFORM_DRAM_WAIT); + udelay(1100); + millisec = 0; hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24; - millisec++; + while ((((hfs & 0xf0) >> 4) != ME_HFS_BIOS_DRAM_ACK) && (millisec < 5000)) { + udelay(1000); + hfs = (pci_read_config32(PCI_DEV(0, b617e32bb99af608b7609583815e876d348025ac0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24; + millisec++; + } + timestamp_add_now(TS_ME_INFORM_DRAM_DONE); } - timestamp_add_now(TS_ME_INFORM_DRAM_DONE); + me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48); printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2); diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 70ba301..433f864 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -576,7 +576,7 @@ switch (hfs.operation_mode) { case ME_HFS_MODE_NORMAL: break; - case ME_HFS_MODE_DEBUG: + case ME_HFS_MODE_DISABLED: case ME_HFS_MODE_DIS: case ME_HFS_MODE_OVER_JMPR: case ME_HFS_MODE_OVER_MEI: diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index f95a0b4..39bfabb 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -49,7 +49,7 @@ #define ME_HFS_ERROR_IMAGE 3 #define ME_HFS_ERROR_DEBUG 4 #define ME_HFS_MODE_NORMAL 0 -#define ME_HFS_MODE_DEBUG 2 +#define ME_HFS_MODE_DISABLED 2 #define ME_HFS_MODE_DIS 3 #define ME_HFS_MODE_OVER_JMPR 4 #define ME_HFS_MODE_OVER_MEI 5 diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 2e29233..5a9b60a 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -556,7 +556,7 @@ switch (hfs.operation_mode) { case ME_HFS_MODE_NORMAL: break; - case ME_HFS_MODE_DEBUG: + case ME_HFS_MODE_DISABLED: case ME_HFS_MODE_DIS: case ME_HFS_MODE_OVER_JMPR: case ME_HFS_MODE_OVER_MEI: -- To view, visit https://review.coreboot.org/21466 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifdda6b2dbb8ae3a650be6d5df6c60475a3fa74aa Gerrit-Change-Number: 21466 Gerrit-PatchSet: 1 Gerrit-Owner: Nathaniel Roach <nroach44(a)gmail.com>

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Change in coreboot[master]: sb/intel/bd82x6x: Add Timestamp around ME DRAM update
by Nathaniel Roach (Code Review) 09 Sep '17

09 Sep '17

Nathaniel Roach has uploaded this change for review. ( https://review.coreboot.org/21465 Change subject: sb/intel/bd82x6x: Add Timestamp around ME DRAM update ...................................................................... sb/intel/bd82x6x: Add Timestamp around ME DRAM update Add a timestamp before and after waiting for the ME to acknowledge the DRAM being ready. This allows easier debugging during use of me_cleaner and/or alternate ME images. Change-Id: Ie228e12a75d373b4f406b3595e1fb1aab41aa5df Signed-off-by: Nathaniel Roach <nroach44(a)gmail.com> --- M src/commonlib/include/commonlib/timestamp_serialized.h M src/southbridge/intel/bd82x6x/early_me.c 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/21465/1 diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index 60feffe..d9784d1 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -77,6 +77,10 @@ TS_END_COPYVPD_RO = 551, TS_END_COPYVPD_RW = 552, + /* 940-950 reserved for vendorcode extensions (940-950: intel/ME) */ + TS_ME_INFORM_DRAM_WAIT = 940, + TS_ME_INFORM_DRAM_DONE = 941, + /* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */ TS_FSP_MEMORY_INIT_START = 950, TS_FSP_MEMORY_INIT_END = 951, @@ -177,6 +181,10 @@ { TS_KERNEL_DECOMPRESSION, "starting kernel decompression/relocation" }, { TS_START_KERNEL, "jumping to kernel" }, + /* Intel ME related timestamps */ + { TS_ME_INFORM_DRAM_WAIT, "waiting for ME acknowledgement of raminit"}, + { TS_ME_INFORM_DRAM_DONE, "finished waiting for ME response"}, + /* FSP related timestamps */ { TS_FSP_MEMORY_INIT_START, "calling FspMemoryInit" }, { TS_FSP_MEMORY_INIT_END, "returning from FspMemoryInit" }, diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index 607cd14..b2e9200 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -20,6 +20,7 @@ #include <device/pci_ids.h> #include <halt.h> #include <string.h> +#include <timestamp.h> #include "me.h" #include "pch.h" @@ -190,6 +191,7 @@ meDID = did.uma_base | (1 << 28);// | (1 << 23); pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_ME_H_GS, meDID); + timestamp_add_now(TS_ME_INFORM_DRAM_WAIT); udelay(1100); /* Must wait for ME acknowledgement */ @@ -200,6 +202,7 @@ hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24; millisec++; } + timestamp_add_now(TS_ME_INFORM_DRAM_DONE); me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48); printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2); -- To view, visit https://review.coreboot.org/21465 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie228e12a75d373b4f406b3595e1fb1aab41aa5df Gerrit-Change-Number: 21465 Gerrit-PatchSet: 1 Gerrit-Owner: Nathaniel Roach <nroach44(a)gmail.com>

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Change in coreboot[master]: mb/asrock/g41c-gs: Add IO decode range for SIO HWMON
by build bot (Jenkins) (Code Review) 09 Sep '17

09 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21464 ) Change subject: mb/asrock/g41c-gs: Add IO decode range for SIO HWMON ...................................................................... Patch Set 2: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/60146/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/15377/ : SUCCESS -- To view, visit https://review.coreboot.org/21464 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic02c3a6265f11c1571369bc04371d28b6f989736 Gerrit-Change-Number: 21464 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Sep 2017 11:11:23 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: cpu/amdk8: Depreciate LATE_CBMEM_INIT
by build bot (Jenkins) (Code Review) 09 Sep '17

09 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21151 ) Change subject: cpu/amdk8: Depreciate LATE_CBMEM_INIT ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15376/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60145/ : SUCCESS -- To view, visit https://review.coreboot.org/21151 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ief7dd6d6f450fb8ed9dd4d36b099f3c0072b6b2e Gerrit-Change-Number: 21151 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Sep 2017 10:43:00 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/asrock/g41c-gs: Add IO decode range for SIO HWMON
by Arthur Heymans (Code Review) 09 Sep '17

09 Sep '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/21464 to look at the new patch set (#2). Change subject: mb/asrock/g41c-gs: Add IO decode range for SIO HWMON ...................................................................... mb/asrock/g41c-gs: Add IO decode range for SIO HWMON Change-Id: Ic02c3a6265f11c1571369bc04371d28b6f989736 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asrock/g41c-gs/romstage.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/21464/2 -- To view, visit https://review.coreboot.org/21464 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic02c3a6265f11c1571369bc04371d28b6f989736 Gerrit-Change-Number: 21464 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit September 2017