coreboot-gerrit September 2017

coreboot-gerrit@coreboot.org

1 participants
1960 discussions

Change in coreboot[master]: soc/intel/common/block: Update common rtc code
by build bot (Jenkins) (Code Review) 09 Sep '17

09 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21433 ) Change subject: soc/intel/common/block: Update common rtc code ...................................................................... Patch Set 8: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15354/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60122/ : SUCCESS -- To view, visit https://review.coreboot.org/21433 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I702ce0efba25cb6fde33cc15698ae44312742367 Gerrit-Change-Number: 21433 Gerrit-PatchSet: 8 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrex Andraos <andrex.andraos(a)intel.corp-partner.google.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Sep 2017 01:28:29 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/cannonlake: Add ramstage uart debug support
by build bot (Jenkins) (Code Review) 09 Sep '17

09 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21412 ) Change subject: soc/intel/cannonlake: Add ramstage uart debug support ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15356/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60125/ : SUCCESS -- To view, visit https://review.coreboot.org/21412 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib773e01d5f5358f13297400075d6920793200b88 Gerrit-Change-Number: 21412 Gerrit-PatchSet: 7 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrex Andraos <andrex.andraos(a)intel.corp-partner.google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Sep 2017 01:24:26 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/cannonlake: Add serialio device config
by build bot (Jenkins) (Code Review) 09 Sep '17

09 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21411 ) Change subject: soc/intel/cannonlake: Add serialio device config ...................................................................... Patch Set 8: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/60126/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/15357/ : SUCCESS -- To view, visit https://review.coreboot.org/21411 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7009120d69646cf60cb5a622e438ae1eeb6498cf Gerrit-Change-Number: 21411 Gerrit-PatchSet: 8 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Sep 2017 01:21:45 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: mainboard/intel/cannonlake_rvp: Set LPSS UART2 to hidden
by Lijian Zhao (Code Review) 09 Sep '17

09 Sep '17

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/21459 Change subject: mainboard/intel/cannonlake_rvp: Set LPSS UART2 to hidden ...................................................................... mainboard/intel/cannonlake_rvp: Set LPSS UART2 to hidden If LPSS UART port had been set up to hidden mode, FSP will not force 8 bit transition mode (AKA 16550 compatible UART mode). BRANCH=none TEST=Boot up coreboot and check LPSS UART debug printing after silicon init. If mismatch, the print will became much slower. Change-Id: I80619394d8f462a799c57bf0e7589dc34fe67716 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/21459/1 diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index a3c4c80..31a762a 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -8,6 +8,9 @@ register "SaGv" = "3" register "FspSkipMpInit" = "1" register "SmbusEnable" = "1" + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexUART2] = PchSerialIoHidden, \ + }" device domain 0 on device pci 00.0 on end # Host Bridge diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index a3c4c80..31a762a 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -8,6 +8,9 @@ register "SaGv" = "3" register "FspSkipMpInit" = "1" register "SmbusEnable" = "1" + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexUART2] = PchSerialIoHidden, \ + }" device domain 0 on device pci 00.0 on end # Host Bridge -- To view, visit https://review.coreboot.org/21459 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I80619394d8f462a799c57bf0e7589dc34fe67716 Gerrit-Change-Number: 21459 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

1 0

Change in coreboot[master]: soc/intel/cannonlake: Add serialio device config
by Lijian Zhao (Code Review) 09 Sep '17

09 Sep '17

Lijian Zhao has uploaded a new patch set (#8). ( https://review.coreboot.org/21411 ) Change subject: soc/intel/cannonlake: Add serialio device config ...................................................................... soc/intel/cannonlake: Add serialio device config Add SerialIO device mode configuration, device mode definition mirrored from FSP. Change-Id: I7009120d69646cf60cb5a622e438ae1eeb6498cf Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/chip.c M src/soc/intel/cannonlake/chip.h A src/soc/intel/cannonlake/include/soc/serialio.h 3 files changed, 109 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/21411/8 -- To view, visit https://review.coreboot.org/21411 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7009120d69646cf60cb5a622e438ae1eeb6498cf Gerrit-Change-Number: 21411 Gerrit-PatchSet: 8 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: soc/intel/cannonlake: Add ramstage uart debug support
by build bot (Jenkins) (Code Review) 09 Sep '17

09 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21412 ) Change subject: soc/intel/cannonlake: Add ramstage uart debug support ...................................................................... Patch Set 6: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/60124/ : ABORTED -- To view, visit https://review.coreboot.org/21412 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib773e01d5f5358f13297400075d6920793200b88 Gerrit-Change-Number: 21412 Gerrit-PatchSet: 6 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrex Andraos <andrex.andraos(a)intel.corp-partner.google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Sep 2017 01:15:03 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/cannonlake: Add PMC pci drivers
by build bot (Jenkins) (Code Review) 09 Sep '17

09 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21251 ) Change subject: soc/intel/cannonlake: Add PMC pci drivers ...................................................................... Patch Set 13: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15355/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60123/ : SUCCESS -- To view, visit https://review.coreboot.org/21251 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I95895a3e26cdebd98a4e54720bd4730542707d7e Gerrit-Change-Number: 21251 Gerrit-PatchSet: 13 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrex Andraos <andrex.andraos(a)intel.corp-partner.google.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Sep 2017 01:14:02 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/common/block: Update common rtc code
by build bot (Jenkins) (Code Review) 09 Sep '17

09 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21433 ) Change subject: soc/intel/common/block: Update common rtc code ...................................................................... Patch Set 8: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/60121/ : SUCCESS -- To view, visit https://review.coreboot.org/21433 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I702ce0efba25cb6fde33cc15698ae44312742367 Gerrit-Change-Number: 21433 Gerrit-PatchSet: 8 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrex Andraos <andrex.andraos(a)intel.corp-partner.google.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Sep 2017 01:12:36 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/common/block: Update common rtc code
by Lijian Zhao (Code Review) 09 Sep '17

09 Sep '17

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/21433 Change subject: soc/intel/common/block: Update common rtc code ...................................................................... soc/intel/common/block: Update common rtc code Move rtc init code into common area and update the implementation for apollolake to avoid build break. Change-Id: I702ce0efba25cb6fde33cc15698ae44312742367 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/apollolake/lpc.c M src/soc/intel/common/block/include/intelblocks/rtc.h M src/soc/intel/common/block/rtc/Makefile.inc M src/soc/intel/common/block/rtc/rtc.c 4 files changed, 32 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/21433/8 diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 6c7ffff..0cd58de 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -83,23 +83,16 @@ gpio_configure_pads(lpc_gpios, ARRAY_SIZE(lpc_gpios)); } -static void rtc_init(void) +int soc_get_rtc_failed(void) { - int rtc_fail; const struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); if (!ps) { printk(BIOS_ERR, "Could not find power state in cbmem, RTC init aborted\n"); - return; + return 1; } - rtc_fail = !!(ps->gen_pmcon1 & RPS); - /* Ensure the date is set including century byte. */ - cmos_check_update_date(); - if (IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS)) - init_vbnv_cmos(rtc_fail); - else - cmos_init(rtc_fail); + return !!(ps->gen_pmcon1 & RPS); } void lpc_init(struct device *dev) diff --git a/src/soc/intel/common/block/include/intelblocks/rtc.h b/src/soc/intel/common/block/include/intelblocks/rtc.h index 1556026..c6507c8 100644 --- a/src/soc/intel/common/block/include/intelblocks/rtc.h +++ b/src/soc/intel/common/block/include/intelblocks/rtc.h @@ -18,4 +18,9 @@ void enable_rtc_upper_bank(void); +/* Expect return rtc failed bootlean in case of coin removal */ +int soc_get_rtc_failed(void); + +void rtc_init(void); + #endif /* SOC_INTEL_COMMON_BLOCK_RTC_H */ diff --git a/src/soc/intel/common/block/rtc/Makefile.inc b/src/soc/intel/common/block/rtc/Makefile.inc index 2d2d4e3..95f6659 100644 --- a/src/soc/intel/common/block/rtc/Makefile.inc +++ b/src/soc/intel/common/block/rtc/Makefile.inc @@ -1 +1,3 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_RTC) += rtc.c + +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_RTC) += rtc.c diff --git a/src/soc/intel/common/block/rtc/rtc.c b/src/soc/intel/common/block/rtc/rtc.c index ea99870..04c0768 100644 --- a/src/soc/intel/common/block/rtc/rtc.c +++ b/src/soc/intel/common/block/rtc/rtc.c @@ -13,9 +13,11 @@ * GNU General Public License for more details. */ -#include <soc/pcr_ids.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> +#include <soc/pcr_ids.h> +#include <pc80/mc146818rtc.h> +#include <vboot/vbnv.h> /* RTC PCR configuration */ #define PCR_RTC_CONF 0x3400 @@ -29,3 +31,22 @@ /* Enable upper 128 bytes of CMOS */ pcr_or32(PID_RTC, PCR_RTC_CONF, PCR_RTC_CONF_UCMOS_EN); } + +__attribute__((weak)) int soc_get_rtc_failed(void) +{ + return 0; +} + +void rtc_init(void) +{ + int rtc_failed; + + rtc_failed = soc_get_rtc_failed(); + /* Ensure the date is set including century byte. */ + cmos_check_update_date(); + + if (IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS)) + init_vbnv_cmos(rtc_failed); + else + cmos_init(rtc_failed); +} -- To view, visit https://review.coreboot.org/21433 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I702ce0efba25cb6fde33cc15698ae44312742367 Gerrit-Change-Number: 21433 Gerrit-PatchSet: 8 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrex Andraos <andrex.andraos(a)intel.corp-partner.google.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: google/snappy: Update EC keyboard backlight flag by SKU ID
by build bot (Jenkins) (Code Review) 09 Sep '17

09 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21400 ) Change subject: google/snappy: Update EC keyboard backlight flag by SKU ID ...................................................................... Patch Set 12: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/15353/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/60120/ : SUCCESS -- To view, visit https://review.coreboot.org/21400 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1153aa0b89250c55f311dd93a01fcef47afd7292 Gerrit-Change-Number: 21400 Gerrit-PatchSet: 12 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Keith Tzeng <keith.tzeng(a)quantatw.com> Gerrit-Reviewer: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 09 Sep 2017 00:30:06 +0000 Gerrit-HasComments: No

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2017