coreboot-gerrit August 2017

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Change in coreboot[master]: Boards w/ Winbond superios: Use common config entry code
by Keith Hui (Code Review) 13 Aug '17

13 Aug '17

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/20989 Change subject: Boards w/ Winbond superios: Use common config entry code ...................................................................... Boards w/ Winbond superios: Use common config entry code Six mainboards with Winbond superios directly configure them in romstage.c. All use the common Winbond romstage code. Change them to use the common config entry code to allow for code refactoring such as [1]. Build tested. [1] https://review.coreboot.org/20988 Change-Id: Icecd52ec622b9da86edb07c52893f4db001e5562 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/a8v-e_deluxe/romstage.c M src/mainboard/asus/a8v-e_se/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/msi/ms7260/romstage.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/nvidia/l1_2pvv/romstage.c 6 files changed, 20 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/20989/1 diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 87fec55..2ead963 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -94,7 +94,7 @@ { u8 reg; - pnp_enter_ext_func_mode(SERIAL_DEV); + pnp_enter_conf_state(SERIAL_DEV); /* We have 24MHz input. */ reg = pnp_read_config(SERIAL_DEV, 0x24); pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); @@ -104,9 +104,9 @@ /* We have all RESTOUT and even some reserved bits, too. */ reg = pnp_read_config(SERIAL_DEV, 0x2c); pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); - pnp_exit_ext_func_mode(SERIAL_DEV); + pnp_exit_conf_state(SERIAL_DEV); - pnp_enter_ext_func_mode(ACPI_DEV); + pnp_enter_conf_state(ACPI_DEV); pnp_set_logical_device(ACPI_DEV); /* * Set the delay rising time from PWROK_LP to PWROK_ST to @@ -117,9 +117,9 @@ /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ reg = pnp_read_config(ACPI_DEV, 0xe4); pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); - pnp_exit_ext_func_mode(ACPI_DEV); + pnp_exit_conf_state(ACPI_DEV); - pnp_enter_ext_func_mode(GPIO_DEV); + pnp_enter_conf_state(GPIO_DEV); pnp_set_logical_device(GPIO_DEV); /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ @@ -129,7 +129,7 @@ pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0 = output 1 = input */ pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ - pnp_exit_ext_func_mode(GPIO_DEV); + pnp_exit_conf_state(GPIO_DEV); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index adcf381..d893cf5 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -94,7 +94,7 @@ { u8 reg; - pnp_enter_ext_func_mode(SERIAL_DEV); + pnp_enter_conf_state(SERIAL_DEV); /* We have 24MHz input. */ reg = pnp_read_config(SERIAL_DEV, 0x24); pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); @@ -104,9 +104,9 @@ /* We have all RESTOUT and even some reserved bits, too. */ reg = pnp_read_config(SERIAL_DEV, 0x2c); pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); - pnp_exit_ext_func_mode(SERIAL_DEV); + pnp_exit_conf_state(SERIAL_DEV); - pnp_enter_ext_func_mode(ACPI_DEV); + pnp_enter_conf_state(ACPI_DEV); pnp_set_logical_device(ACPI_DEV); /* * Set the delay rising time from PWROK_LP to PWROK_ST to @@ -117,9 +117,9 @@ /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ reg = pnp_read_config(ACPI_DEV, 0xe4); pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); - pnp_exit_ext_func_mode(ACPI_DEV); + pnp_exit_conf_state(ACPI_DEV); - pnp_enter_ext_func_mode(GPIO_DEV); + pnp_enter_conf_state(GPIO_DEV); pnp_set_logical_device(GPIO_DEV); /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ @@ -129,7 +129,7 @@ pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0 = output 1 = input */ pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ - pnp_exit_ext_func_mode(GPIO_DEV); + pnp_exit_conf_state(GPIO_DEV); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 7088f1d..43c5677 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -62,7 +62,7 @@ pnp_devfn_t dev; dev = DUMMY_DEV; - pnp_enter_ext_func_mode(dev); + pnp_enter_conf_state(dev); pnp_write_config(dev, 0x24, 0xc4); // PNPCSV @@ -121,7 +121,7 @@ pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); + pnp_exit_conf_state(dev); } static void rcba_config(void) diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 878a79e..8ddfdd6 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -126,11 +126,11 @@ bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* FIXME: This should be part of the Super I/O code/config. */ - pnp_enter_ext_func_mode(SERIAL_DEV); + pnp_enter_conf_state(SERIAL_DEV); /* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */ pnp_write_config(SERIAL_DEV, 0x24, 0); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); + pnp_exit_conf_state(SERIAL_DEV); setup_mb_resource_map(); console_init(); diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 11e9bc0..ec11dd6 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -129,11 +129,11 @@ post_code(0x32); - pnp_enter_ext_func_mode(SERIAL_DEV); + pnp_enter_conf_state(SERIAL_DEV); /* We have 24MHz input. */ reg = pnp_read_config(SERIAL_DEV, 0x24); pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf)); - pnp_exit_ext_func_mode(SERIAL_DEV); + pnp_exit_conf_state(SERIAL_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index d8076f0..c2fd798 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -124,9 +124,9 @@ if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - pnp_enter_ext_func_mode(SERIAL_DEV); + pnp_enter_conf_state(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x24, 0); - pnp_exit_ext_func_mode(SERIAL_DEV); + pnp_exit_conf_state(SERIAL_DEV); setup_mb_resource_map(); -- To view, visit https://review.coreboot.org/20989 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icecd52ec622b9da86edb07c52893f4db001e5562 Gerrit-Change-Number: 20989 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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Change in coreboot[master]: superio/winbond/w83627*: Remove deprecated code
by build bot (Jenkins) (Code Review) 13 Aug '17

13 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20988 ) Change subject: superio/winbond/w83627*: Remove deprecated code ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/58508/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/13909/ : SUCCESS -- To view, visit https://review.coreboot.org/20988 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idad6e0281f7a272e184feff686ce1407825429c7 Gerrit-Change-Number: 20988 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 13 Aug 2017 19:42:07 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: superio/winbond/w83627*: Remove deprecated code
by Keith Hui (Code Review) 13 Aug '17

13 Aug '17

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/20988 Change subject: superio/winbond/w83627*: Remove deprecated code ...................................................................... superio/winbond/w83627*: Remove deprecated code Early serial for W83627[HF|EHG] superios are handled by superio/winbond/common/early_serial.c. Remove code thus deprecated. Build tested on select affected mainboards. Change-Id: Idad6e0281f7a272e184feff686ce1407825429c7 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/superio/winbond/w83627ehg/Makefile.inc D src/superio/winbond/w83627ehg/early_serial.c D src/superio/winbond/w83627hf/early_serial.c M src/superio/winbond/w83627hf/w83627hf.h 4 files changed, 0 insertions(+), 102 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/20988/1 diff --git a/src/superio/winbond/w83627ehg/Makefile.inc b/src/superio/winbond/w83627ehg/Makefile.inc index b9719b5..88fb0f2 100644 --- a/src/superio/winbond/w83627ehg/Makefile.inc +++ b/src/superio/winbond/w83627ehg/Makefile.inc @@ -15,5 +15,4 @@ ## GNU General Public License for more details. ## -romstage-$(CONFIG_SUPERIO_WINBOND_W83627EHG) += early_serial.c ramstage-$(CONFIG_SUPERIO_WINBOND_W83627EHG) += superio.c diff --git a/src/superio/winbond/w83627ehg/early_serial.c b/src/superio/winbond/w83627ehg/early_serial.c deleted file mode 100644 index b690cac..0000000 --- a/src/superio/winbond/w83627ehg/early_serial.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "w83627ehg.h" - -void pnp_enter_ext_func_mode(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -void pnp_exit_ext_func_mode(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} diff --git a/src/superio/winbond/w83627hf/early_serial.c b/src/superio/winbond/w83627hf/early_serial.c deleted file mode 100644 index a87c7e9..0000000 --- a/src/superio/winbond/w83627hf/early_serial.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * Copyright (C) 2010 Win Enterprises (anishp(a)win-ent.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include "w83627hf.h" - -static void pnp_enter_ext_func_mode(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0x87, port); - outb(0x87, port); -} - -static void pnp_exit_ext_func_mode(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(0xaa, port); -} - -/* - * FIXME: The following ROMCC boards are blocking the removal this superio's - * model specific w83627hf_enable_serial() symbol. - * - * mainboard/supermicro/x6dai_g - * mainboard/supermicro/x6dhe_g - * mainboard/supermicro/x6dhr_ig - * mainboard/supermicro/x6dhr_ig2 - * - * XXX: ROMCC - everything is inlined, no forwarding function prototypes - * declarations are accepted. - */ -void w83627hf_enable_serial(pnp_devfn_t dev, u16 iobase) -{ - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); -} - -void w83627hf_set_clksel_48(pnp_devfn_t dev) -{ - u8 reg8; - - pnp_enter_ext_func_mode(dev); - reg8 = pnp_read_config(dev, 0x24); - reg8 |= (1 << 6); /* Set CLKSEL (clock input on pin 1) to 48MHz. */ - pnp_write_config(dev, 0x24, reg8); - pnp_exit_ext_func_mode(dev); -} diff --git a/src/superio/winbond/w83627hf/w83627hf.h b/src/superio/winbond/w83627hf/w83627hf.h index e4f3784..4b55e0f 100644 --- a/src/superio/winbond/w83627hf/w83627hf.h +++ b/src/superio/winbond/w83627hf/w83627hf.h @@ -112,6 +112,5 @@ #include <arch/io.h> void w83627hf_set_clksel_48(pnp_devfn_t dev); -void w83627hf_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_WINBOND_W83627HF_H */ -- To view, visit https://review.coreboot.org/20988 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idad6e0281f7a272e184feff686ce1407825429c7 Gerrit-Change-Number: 20988 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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Change in coreboot[master]: tint: Use the current time as random seed
by build bot (Jenkins) (Code Review) 13 Aug '17

13 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20980 ) Change subject: tint: Use the current time as random seed ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58507/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13908/ : SUCCESS -- To view, visit https://review.coreboot.org/20980 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2e482bbb9d33cdbbf3c15916458329f99fbc4450 Gerrit-Change-Number: 20980 Gerrit-PatchSet: 2 Gerrit-Owner: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 13 Aug 2017 18:31:28 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: ec/lenovo/h8/acpi/ec: Add registers
by build bot (Jenkins) (Code Review) 13 Aug '17

13 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20987 ) Change subject: ec/lenovo/h8/acpi/ec: Add registers ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58506/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13907/ : SUCCESS -- To view, visit https://review.coreboot.org/20987 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5a125047fad0e08cd9256bc53c3f5a7db7e56e7d Gerrit-Change-Number: 20987 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 13 Aug 2017 16:32:57 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: ec/lenovo/h8/acpi/ec: Add registers
by Patrick Rudolph (Code Review) 13 Aug '17

13 Aug '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/20987 Change subject: ec/lenovo/h8/acpi/ec: Add registers ...................................................................... ec/lenovo/h8/acpi/ec: Add registers Add register HPPI and WLSW. WLSW is used by thinkpad_acpi kernel module. Change-Id: I5a125047fad0e08cd9256bc53c3f5a7db7e56e7d Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/ec/lenovo/h8/acpi/ec.asl 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/20987/1 diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index eed0e16..fdbb931 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -53,6 +53,9 @@ KBLT, 1, /* Keyboard Light */ , 2, USPW, 1, /* USB Power enable */ + Offset (0x48), + HPPI, 1, /* Headphone plugged in */ + WLSW, 1, /* Master wireless switch */ Offset (0x4e), WAKE, 16, Offset (0x78), -- To view, visit https://review.coreboot.org/20987 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5a125047fad0e08cd9256bc53c3f5a7db7e56e7d Gerrit-Change-Number: 20987 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: mb/lenovo/*/devicetree: Add support for WWAN detection
by build bot (Jenkins) (Code Review) 13 Aug '17

13 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20984 ) Change subject: mb/lenovo/*/devicetree: Add support for WWAN detection ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58501/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13902/ : SUCCESS -- To view, visit https://review.coreboot.org/20984 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie96b2593971d49703eb747ab19f512be890d9c12 Gerrit-Change-Number: 20984 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 13 Aug 2017 16:01:32 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: ec/lenovo/h8: Add WWAN detection support
by build bot (Jenkins) (Code Review) 13 Aug '17

13 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20983 ) Change subject: ec/lenovo/h8: Add WWAN detection support ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58503/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13904/ : SUCCESS -- To view, visit https://review.coreboot.org/20983 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie53275b384c85df8adf71fe79b3d54211c868756 Gerrit-Change-Number: 20983 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 13 Aug 2017 15:56:08 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenovo/*/devicetree: Add BDC detection support
by build bot (Jenkins) (Code Review) 13 Aug '17

13 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19810 ) Change subject: mb/lenovo/*/devicetree: Add BDC detection support ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58502/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13903/ : SUCCESS -- To view, visit https://review.coreboot.org/19810 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If33ef88fb808f36b050393fa83eb1b541ce936b9 Gerrit-Change-Number: 19810 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 13 Aug 2017 15:55:07 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: ec/lenovo/h8/ssdt: Add WWAN ACPI methods
by build bot (Jenkins) (Code Review) 13 Aug '17

13 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20986 ) Change subject: ec/lenovo/h8/ssdt: Add WWAN ACPI methods ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58505/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13906/ : SUCCESS -- To view, visit https://review.coreboot.org/20986 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5550c78e0d36884eca7a8d8ece19b64aaee44045 Gerrit-Change-Number: 20986 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 13 Aug 2017 15:55:03 +0000 Gerrit-HasComments: No

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