coreboot-gerrit August 2017

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Change in coreboot[master]: 440BX boards: Use combined RAM init routine
by build bot (Jenkins) (Code Review) 13 Aug '17

13 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20868 ) Change subject: 440BX boards: Use combined RAM init routine ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58491/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13893/ : SUCCESS -- To view, visit https://review.coreboot.org/20868 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I699db882189f99018d4a6fdcb00f9438b2a7a1bc Gerrit-Change-Number: 20868 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 13 Aug 2017 02:54:34 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/i440bx: [WIP] Implement CBMEM in romstage
by build bot (Jenkins) (Code Review) 13 Aug '17

13 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20977 ) Change subject: nb/intel/i440bx: [WIP] Implement CBMEM in romstage ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58493/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/13895/ : SUCCESS -- To view, visit https://review.coreboot.org/20977 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I432f145a5343c1bb5f2b0de3b6b88f57124d1bd9 Gerrit-Change-Number: 20977 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 13 Aug 2017 02:51:55 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/i440bx: [WIP] Implement CBMEM in romstage
by Keith Hui (Code Review) 13 Aug '17

13 Aug '17

Keith Hui has uploaded a new patch set (#2). ( https://review.coreboot.org/20977 ) Change subject: nb/intel/i440bx: [WIP] Implement CBMEM in romstage ...................................................................... nb/intel/i440bx: [WIP] Implement CBMEM in romstage An attempt to implement CBMEM in romstage. Should benefit all 440BX boards but currently only being tested on ASUS P2B-LS. NOT FOR MERGING. Currently does not boot and I need your help on the mailing list. Change-Id: I432f145a5343c1bb5f2b0de3b6b88f57124d1bd9 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/i440bx/Makefile.inc M src/northbridge/intel/i440bx/northbridge.c A src/northbridge/intel/i440bx/ram_calc.c 4 files changed, 127 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/20977/2 -- To view, visit https://review.coreboot.org/20977 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I432f145a5343c1bb5f2b0de3b6b88f57124d1bd9 Gerrit-Change-Number: 20977 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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Change in coreboot[master]: nb/intel/i440bx: [WIP] Implement CBMEM in romstage
by Keith Hui (Code Review) 13 Aug '17

13 Aug '17

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/20977 Change subject: nb/intel/i440bx: [WIP] Implement CBMEM in romstage ...................................................................... nb/intel/i440bx: [WIP] Implement CBMEM in romstage An attempt to implement CBMEM in romstage. Should benefit all 440BX boards but currently only being tested on ASUS P2B-LS. Currently does not boot and I need your help on the mailing list. Change-Id: I432f145a5343c1bb5f2b0de3b6b88f57124d1bd9 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/northbridge/intel/i440bx/Kconfig M src/northbridge/intel/i440bx/Makefile.inc M src/northbridge/intel/i440bx/northbridge.c A src/northbridge/intel/i440bx/ram_calc.c 4 files changed, 127 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/20977/1 diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 36d4754..45cdd9c 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -17,7 +17,6 @@ bool select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP - select LATE_CBMEM_INIT select UDELAY_IO config SDRAMPWR_4DIMM diff --git a/src/northbridge/intel/i440bx/Makefile.inc b/src/northbridge/intel/i440bx/Makefile.inc index ecefe6a..f900c50 100644 --- a/src/northbridge/intel/i440bx/Makefile.inc +++ b/src/northbridge/intel/i440bx/Makefile.inc @@ -17,8 +17,10 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BX),y) ramstage-y += northbridge.c +ramstage-y += ram_calc.c romstage-y += raminit.c romstage-y += debug.c +romstage-y += ram_calc.c endif diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index dba7880..414ae99 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -67,7 +67,7 @@ ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); - set_late_cbmem_top(tomk * 1024); + // set_late_cbmem_top(tomk * 1024); } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i440bx/ram_calc.c b/src/northbridge/intel/i440bx/ram_calc.c new file mode 100644 index 0000000..5e00545 --- /dev/null +++ b/src/northbridge/intel/i440bx/ram_calc.c @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2012 ChromeOS Authors + * Copyright (C) 2017 Keith Hui <buurin(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <cbmem.h> +#include <cpu/intel/romstage.h> +#include <console/console.h> +#include <cpu/x86/mtrr.h> +#include <commonlib/helpers.h> +#include "i440bx.h" + +unsigned long get_top_of_ram(void); + +unsigned long get_top_of_ram(void) +{ + return pci_read_config8(NB, DRB7) * 8 * MiB; +} + +static unsigned long smm_region_start(void) +{ + /* Base of TSEG is top of usable DRAM */ + /* + * SMRAM - System Management RAM Control Register + * 0x72 + * [7:4] Not relevant to this function. + * [3:3] Global SMRAM Enable (G_SMRAME) + * [2:0] Hardwired to 010. + + * ESMRAMC - Extended System Management RAM Control + * 0x73 + * [7:7] H_SMRAM_EN + * 1 = When G_SMRAME=1, High SMRAM space is enabled at + * 0x100A0000-0x100FFFFF and forwarded to DRAM address + * 0x000A0000-0x000FFFFF. + * 0 = When G_SMRAME=1, Compatible SMRAM space is enabled at + * 0x000A0000-0x000BFFFF. + * [6:3] Not relevant to this function. + * [2:1] TSEG Size (T_SZ) + * Selects the size of the TSEG memory block, if enabled. + * 00 = 128KiB + * 01 = 256KiB + * 10 = 512KiB + * 11 = 1MiB + * [0:0] TSEG_EN + * When SMRAM[G_SMRAME] and this bit are 1, TSEG is enabled to + * appear between DRAM address (TOM-<TSEG Size>) to TOM. + + * Source: 440BX datasheet, pages 3-28 thru 3-29. + */ + unsigned long tom = get_top_of_ram(); + + #if ENV_ROMSTAGE + /* + * In romstage, gtom() above returns 0 if DRB7=0 + * (ie. RAM init isn't done). + * Pass it on. This should not happen in ramstage. + */ + if (tom == 0) + return 0; + #endif + + printk(BIOS_DEBUG, "get_top_of_ram() = %08lx", tom); + + int tseg = pci_read_config8(NB, ESMRAMC) & 0x7; // H_SMRAM_EN and T_SZ + int gsmrame = pci_read_config8(NB, SMRAM) & 0x8; // G_SMRAME + if ((tseg & 0x1) && gsmrame) { + int tseg_size = 128 * KiB * (1 << (tseg >> 1)); + tom -= tseg_size; + } + return tom; +} + +void *cbmem_top(void) +{ + uintptr_t top_of_ram = ALIGN_DOWN(smm_region_start(), 4*MiB); + return (void *) top_of_ram; +} + +#define ROMSTAGE_RAM_STACK_SIZE 0x5000 +/* setup_stack_and_mtrrs() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. */ +void *setup_stack_and_mtrrs(void) +{ + struct postcar_frame pcf; + uintptr_t tom; + + if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache two separate 4 MiB regions below the top of ram, this + * satisfies MTRR alignment requirements. + */ + tom = (uintptr_t)cbmem_top(); + postcar_frame_add_mtrr(&pcf, tom - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, tom - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK); + + /* Save the number of MTRRs to setup. Return the stack location + * pointing to the number of MTRRs. + */ + return postcar_commit_mtrrs(&pcf); +} -- To view, visit https://review.coreboot.org/20977 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I432f145a5343c1bb5f2b0de3b6b88f57124d1bd9 Gerrit-Change-Number: 20977 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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Change in coreboot[master]: nb/amd/amdfam10/debug.c: Fix building with DEBUG_SMBUS
by Raptor Engineering Automated Test Stand (Code Review) 13 Aug '17

13 Aug '17

Raptor Engineering Automated Test Stand has posted comments on this change. ( https://review.coreboot.org/20970 ) Change subject: nb/amd/amdfam10/debug.c: Fix building with DEBUG_SMBUS ...................................................................... Patch Set 4: Verified-1 ASUS KFSN4-DRE: Boot and extended test successful. Boot log: https://testlab.coreboot.org/raptor/1502574201-0-20970,4.log.bz2 QEMU x86_64 Q35: Boot successful. Boot log: https://testlab.coreboot.org/raptor/1502574269-1-20970,4.log.bz2 ASUS KGPE-D16: Test FAILED. Boot log: https://testlab.coreboot.org/raptor/1502577070-3-20970,4.log.bz2 ASUS KGPE-D16: BOOT_FAILURE -- To view, visit https://review.coreboot.org/20970 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iebe8aa1c4c3019414c6a23404cc5dc7f668cd8eb Gerrit-Change-Number: 20970 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 12 Aug 2017 22:31:12 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: cpu/amd/fam10: Reduce headers included in init_cpus.h
by build bot (Jenkins) (Code Review) 12 Aug '17

12 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20976 ) Change subject: cpu/amd/fam10: Reduce headers included in init_cpus.h ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58490/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13892/ : SUCCESS -- To view, visit https://review.coreboot.org/20976 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id91caa7c55367e794802788d9007920817f2d484 Gerrit-Change-Number: 20976 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 12 Aug 2017 21:56:41 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: cpu/amd/fam10: Reduce headers included in init_cpus.h
by Arthur Heymans (Code Review) 12 Aug '17

12 Aug '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/20976 to look at the new patch set (#4). Change subject: cpu/amd/fam10: Reduce headers included in init_cpus.h ...................................................................... cpu/amd/fam10: Reduce headers included in init_cpus.h Somehow this change discovered a broken dependencies in many romstage.c file lacking reset.h Change-Id: Id91caa7c55367e794802788d9007920817f2d484 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/family_10h-family_15h/defaults.h M src/cpu/amd/family_10h-family_15h/fidvid.c M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/cpu/amd/family_10h-family_15h/init_cpus.h M src/include/cpu/amd/multicore.h M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/supermicro/h8dmr/romstage.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/mainboard/tyan/s2912_fam10/romstage.c M src/northbridge/amd/amdmct/amddefs.h 21 files changed, 28 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/20976/4 -- To view, visit https://review.coreboot.org/20976 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id91caa7c55367e794802788d9007920817f2d484 Gerrit-Change-Number: 20976 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: cpu/amd/fam10: Reduce headers included in init_cpus.h
by build bot (Jenkins) (Code Review) 12 Aug '17

12 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20976 ) Change subject: cpu/amd/fam10: Reduce headers included in init_cpus.h ...................................................................... Patch Set 3: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/58489/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/13891/ : SUCCESS -- To view, visit https://review.coreboot.org/20976 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id91caa7c55367e794802788d9007920817f2d484 Gerrit-Change-Number: 20976 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 12 Aug 2017 21:48:55 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: cpu/amd/fam10: Reduce headers included in init_cpus.h
by Arthur Heymans (Code Review) 12 Aug '17

12 Aug '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/20976 to look at the new patch set (#3). Change subject: cpu/amd/fam10: Reduce headers included in init_cpus.h ...................................................................... cpu/amd/fam10: Reduce headers included in init_cpus.h Somehow this change discovered a broken dependencies in many romstage.c file lacking reset.h Change-Id: Id91caa7c55367e794802788d9007920817f2d484 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/family_10h-family_15h/defaults.h M src/cpu/amd/family_10h-family_15h/fidvid.c M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/cpu/amd/family_10h-family_15h/init_cpus.h M src/include/cpu/amd/multicore.h M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/supermicro/h8dmr/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/mainboard/tyan/s2912_fam10/romstage.c M src/northbridge/amd/amdmct/amddefs.h 20 files changed, 27 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/20976/3 -- To view, visit https://review.coreboot.org/20976 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id91caa7c55367e794802788d9007920817f2d484 Gerrit-Change-Number: 20976 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: cpu/amd/fam10: Reduce headers included in init_cpus.h
by Arthur Heymans (Code Review) 12 Aug '17

12 Aug '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/20976 ) Change subject: cpu/amd/fam10: Reduce headers included in init_cpus.h ...................................................................... Patch Set 2: > Build Unstable > > https://qa.coreboot.org/job/coreboot-gerrit/58488/ : UNSTABLE > > https://qa.coreboot.org/job/coreboot-checkpatch/13890/ : SUCCESS This linking mess... -- To view, visit https://review.coreboot.org/20976 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id91caa7c55367e794802788d9007920817f2d484 Gerrit-Change-Number: 20976 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 12 Aug 2017 21:38:47 +0000 Gerrit-HasComments: No

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coreboot-gerrit August 2017