August 2017 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: soc/intel/skylake: Enable UART debug port in bootblock always
by build bot (Jenkins) (Code Review) Aug. 1, 2017

Aug. 1, 2017

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20835 ) Change subject: soc/intel/skylake: Enable UART debug port in bootblock always ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58087/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/13520/ : SUCCESS -- To view, visit https://review.coreboot.org/20835 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic936ac2a787fdc83935103c3ce4ed8f124a97a89 Gerrit-Change-Number: 20835 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Aug 2017 02:16:41 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: drivers/uart: Use baudrate of 115200 by default
by build bot (Jenkins) (Code Review) Aug. 1, 2017

Aug. 1, 2017

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20834 ) Change subject: drivers/uart: Use baudrate of 115200 by default ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58086/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/13519/ : SUCCESS -- To view, visit https://review.coreboot.org/20834 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ida4c7ae77aba5dfd4ec331e22a54ce43a91bde00 Gerrit-Change-Number: 20834 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Aug 2017 02:16:24 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Enable UART debug port in bootblock always
by Furquan Shaikh (Code Review) Aug. 1, 2017

Aug. 1, 2017

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/20835 Change subject: soc/intel/skylake: Enable UART debug port in bootblock always ...................................................................... soc/intel/skylake: Enable UART debug port in bootblock always Irrespective of whether UART_DEBUG is enabled in coreboot or not, always enable UART controller for the debug port. This is required because: UART hardware loses power while the system is suspended. Linux kernel does not re-initialize the UART controller on resume and so when serial console is enabled in kernel, it can result in hangs on resume from S3. On platforms like baytrail, this was handled in a similar way by initializing UART controller on resume(https://chromium-review.googlesource.com/188011). In this change, UART is always initialized in bootblock irrespective of normal or S3 resume flow in order to re-use the UART drivers that are already implemented and avoid redundancy. BUG=b:64030366 TEST=Verified that kernel does not hang with the following sequence: echo 'N' > /sys/module/printk/parameters/console_suspend echo mem > /sys/power/state <Resume from S3> Change-Id: Ic936ac2a787fdc83935103c3ce4ed8f124a97a89 --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/skylake/bootblock/uart.c 4 files changed, 7 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/20835/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 32c2654..dd4de53 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -84,6 +84,9 @@ select ACPI_NHLT select HAVE_FSP_GOP select SOC_INTEL_COMMON_GFX_OPREGION + select DRIVERS_UART + select DRIVERS_UART_8250MEM_32 + select NO_UART_ON_SUPERIO config MAINBOARD_USES_FSP2_0 bool @@ -196,9 +199,6 @@ bool "Enable UART debug port." default n select CONSOLE_SERIAL - select DRIVERS_UART - select DRIVERS_UART_8250MEM_32 - select NO_UART_ON_SUPERIO config SKYLAKE_SOC_PCH_H bool diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 7f618d4..7b8e149 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -14,8 +14,8 @@ bootblock-y += i2c.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c -bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c -bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c +bootblock-y += bootblock/uart.c +bootblock-y += uart_debug.c bootblock-y += gpio.c bootblock-y += gspi.c bootblock-y += pch.c diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index 058cec8..ac87f41 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -30,9 +30,7 @@ bootblock_pch_early_init(); bootblock_cpu_init(); pch_early_iorange_init(); - - if (IS_ENABLED(CONFIG_UART_DEBUG)) - pch_uart_init(); + pch_uart_init(); } void bootblock_soc_init(void) diff --git a/src/soc/intel/skylake/bootblock/uart.c b/src/soc/intel/skylake/bootblock/uart.c index 26b81c0..eedf75c 100644 --- a/src/soc/intel/skylake/bootblock/uart.c +++ b/src/soc/intel/skylake/bootblock/uart.c @@ -53,4 +53,5 @@ PCR_SIO_PCH_LEGACY_UART2); gpio_configure_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); + uart_init(CONFIG_UART_FOR_CONSOLE); } -- To view, visit https://review.coreboot.org/20835 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic936ac2a787fdc83935103c3ce4ed8f124a97a89 Gerrit-Change-Number: 20835 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: drivers/uart: Use baudrate of 115200 by default
by Furquan Shaikh (Code Review) Aug. 1, 2017

Aug. 1, 2017

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/20834 Change subject: drivers/uart: Use baudrate of 115200 by default ...................................................................... drivers/uart: Use baudrate of 115200 by default If TTYS0_BAUD is not configured, then by default use baudrate of 115200. BUG=b:64030366 Change-Id: Ida4c7ae77aba5dfd4ec331e22a54ce43a91bde00 --- M src/drivers/uart/util.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/20834/1 diff --git a/src/drivers/uart/util.c b/src/drivers/uart/util.c index f0f885d..4f31261 100644 --- a/src/drivers/uart/util.c +++ b/src/drivers/uart/util.c @@ -33,7 +33,11 @@ if (b_index < 8) return baud[b_index]; #endif - return CONFIG_TTYS0_BAUD; + /* + * If TTYS0_BAUD is not configured, then by default use 115200 as the + * baud rate. + */ + return CONFIG_TTYS0_BAUD ? CONFIG_TTYS0_BAUD : 115200; } /* Calculate divisor. Do not floor but round to nearest integer. */ -- To view, visit https://review.coreboot.org/20834 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ida4c7ae77aba5dfd4ec331e22a54ce43a91bde00 Gerrit-Change-Number: 20834 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: google/kahlee: Add ChromeOS SMBIOS Board ID
by build bot (Jenkins) (Code Review) Aug. 1, 2017

Aug. 1, 2017

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19837 ) Change subject: google/kahlee: Add ChromeOS SMBIOS Board ID ...................................................................... Patch Set 25: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58085/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13518/ : SUCCESS -- To view, visit https://review.coreboot.org/19837 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia9693db6d6506af7ff40db0b3ce4cc6c1469f6ef Gerrit-Change-Number: 19837 Gerrit-PatchSet: 25 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Aug 2017 02:12:38 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/kahlee: Add Realtek audio codec ASL
by build bot (Jenkins) (Code Review) Aug. 1, 2017

Aug. 1, 2017

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19845 ) Change subject: google/kahlee: Add Realtek audio codec ASL ...................................................................... Patch Set 24: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58083/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13516/ : SUCCESS -- To view, visit https://review.coreboot.org/19845 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I60b256f68372c9d17d67c9cb2accaca616a0b9a5 Gerrit-Change-Number: 19845 Gerrit-PatchSet: 24 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Anonymous Coward #1001696 Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Aug 2017 02:11:18 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/stoneyridge: Use generic gpio prototypes
by build bot (Jenkins) (Code Review) Aug. 1, 2017

Aug. 1, 2017

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20543 ) Change subject: soc/amd/stoneyridge: Use generic gpio prototypes ...................................................................... Patch Set 8: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58084/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13517/ : SUCCESS -- To view, visit https://review.coreboot.org/20543 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2ea562b052401efff3101f736788ca77d21e6de6 Gerrit-Change-Number: 20543 Gerrit-PatchSet: 8 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Aug 2017 02:09:34 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add memory map support
by build bot (Jenkins) (Code Review) Aug. 1, 2017

Aug. 1, 2017

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20533 ) Change subject: soc/intel/cannonlake: Add memory map support ...................................................................... Patch Set 15: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/58082/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/13515/ : SUCCESS -- To view, visit https://review.coreboot.org/20533 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0dcc8f737c5811c9010cc4a20ea0126ab3f90f14 Gerrit-Change-Number: 20533 Gerrit-PatchSet: 15 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Aug 2017 00:05:42 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: fsp driver: Call cbmem_init_top
by build bot (Jenkins) (Code Review) Aug. 1, 2017

Aug. 1, 2017

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20833 ) Change subject: fsp driver: Call cbmem_init_top ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/58081/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/13514/ : SUCCESS -- To view, visit https://review.coreboot.org/20833 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I82ffe35980ee3896bf58867830e128fe6767ab53 Gerrit-Change-Number: 20833 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Aug 2017 00:04:54 +0000 Gerrit-HasComments: No

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