coreboot-gerrit August 2017

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Change in coreboot[master]: AGESA f15 f15tn f16kb: Add extra check for incorrect SPD data
by build bot (Jenkins) (Code Review) 01 Aug '17

01 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20839 ) Change subject: AGESA f15 f15tn f16kb: Add extra check for incorrect SPD data ...................................................................... Patch Set 2: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/58101/ : UNSTABLE -- To view, visit https://review.coreboot.org/20839 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ica92850cc77e1f7cbf3e7e44717de42a03b93bbe Gerrit-Change-Number: 20839 Gerrit-PatchSet: 2 Gerrit-Owner: Aladyshev Konstantin <aladyshev22(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Aug 2017 12:44:38 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: AGESA f15 f15tn f16kb: Add extra check for incorrect SPD data
by build bot (Jenkins) (Code Review) 01 Aug '17

01 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20839 ) Change subject: AGESA f15 f15tn f16kb: Add extra check for incorrect SPD data ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58100/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/13531/ : SUCCESS -- To view, visit https://review.coreboot.org/20839 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ica92850cc77e1f7cbf3e7e44717de42a03b93bbe Gerrit-Change-Number: 20839 Gerrit-PatchSet: 1 Gerrit-Owner: Aladyshev Konstantin <aladyshev22(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Aug 2017 12:39:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: AGESA f15 f15tn f16kb: Add extra check for incorrect SPD data
by Aladyshev Konstantin (Code Review) 01 Aug '17

01 Aug '17

Aladyshev Konstantin has uploaded a new patch set (#2). ( https://review.coreboot.org/20839 ) Change subject: AGESA f15 f15tn f16kb: Add extra check for incorrect SPD data ...................................................................... AGESA f15 f15tn f16kb: Add extra check for incorrect SPD data If memory module is broken and its SPD data is wrong in a way that Data[11] or Data[9]&0xF is equal to zero, division by 0 in DIMM speed calculation could reboot CPU. Add extra check to avoid this issue. Change-Id: Ica92850cc77e1f7cbf3e7e44717de42a03b93bbe Signed-off-by: Konstantin Aladyshev <aladyshev22(a)gmail.com> --- M src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/DMI/mfDMI.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/DMI/mfDMI.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c 3 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/20839/2 -- To view, visit https://review.coreboot.org/20839 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ica92850cc77e1f7cbf3e7e44717de42a03b93bbe Gerrit-Change-Number: 20839 Gerrit-PatchSet: 2 Gerrit-Owner: Aladyshev Konstantin <aladyshev22(a)gmail.com>

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Change in coreboot[master]: AGESA: f15 f15tn f16kb: Add extra check for incorrect SPD data
by Aladyshev Konstantin (Code Review) 01 Aug '17

01 Aug '17

Aladyshev Konstantin has uploaded this change for review. ( https://review.coreboot.org/20839 Change subject: AGESA: f15 f15tn f16kb: Add extra check for incorrect SPD data ...................................................................... AGESA: f15 f15tn f16kb: Add extra check for incorrect SPD data If memory module is broken and its SPD data is wrong in a way that Data[11] or Data[9]&0xF is equal to zero, division by 0 in DIMM speed calculation could reboot CPU. Add extra check to avoid this issue. Change-Id: Ica92850cc77e1f7cbf3e7e44717de42a03b93bbe Signed-off-by: Konstantin Aladyshev <aladyshev22(a)gmail.com> --- M src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/DMI/mfDMI.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/DMI/mfDMI.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c 3 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/20839/1 diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/DMI/mfDMI.c index 3138f3f..b968349 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/DMI/mfDMI.c +++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Feat/DMI/mfDMI.c @@ -228,6 +228,13 @@ DmiTable[DimmIndex].PartNumber[i] = 0x0; } + // If SPD is wrong, division by 0 in DIMM speed calculation could reboot CPU + // So avoid it by this check + if ((SpdDataStructure[DimmIndex].Data[11]==0) || ((SpdDataStructure[DimmIndex].Data[9] & 0xF) == 0)) { + DmiTable[DimmIndex].DimmPresent = 0; + SpdDataStructure[DimmIndex].DimmPresent = 0; + } + if (SpdDataStructure[DimmIndex].DimmPresent) { // Total Width (offset 08h) & Data Width (offset 0Ah) TotalWidth = (UINT16) SpdDataStructure[DimmIndex].Data[8]; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/DMI/mfDMI.c index 6620030..61499f5 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/DMI/mfDMI.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/DMI/mfDMI.c @@ -243,6 +243,13 @@ DmiTable[DimmIndex].PartNumber[i] = 0x0; } + // If SPD is wrong, division by 0 in DIMM speed calculation could reboot CPU + // So avoid it by this check + if ((SpdDataStructure[DimmIndex].Data[11]==0) || ((SpdDataStructure[DimmIndex].Data[9] & 0xF) == 0)) { + DmiTable[DimmIndex].DimmPresent = 0; + SpdDataStructure[DimmIndex].DimmPresent = 0; + } + if (SpdDataStructure[DimmIndex].DimmPresent) { // Total Width (offset 08h) & Data Width (offset 0Ah) TotalWidth = (UINT16) SpdDataStructure[DimmIndex].Data[8]; diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c index 57cc491..edaf9ee 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Feat/DMI/mfDMI.c @@ -293,6 +293,13 @@ DmiPhysicalDimmInfoTable->PartNumber[i] = 0x0; } + // If SPD is wrong, division by 0 in DIMM speed calculation could reboot CPU + // So avoid it by this check + if ((SpdDataStructure[DimmIndex].Data[11]==0) || ((SpdDataStructure[DimmIndex].Data[9] & 0xF) == 0)) { + DmiTable[DimmIndex].DimmPresent = 0; + SpdDataStructure[DimmIndex].DimmPresent = 0; + } + if (SpdDataStructure->DimmPresent) { // Total Width (offset 08h) & Data Width (offset 0Ah) TotalWidth = (UINT16) SpdDataStructure->Data[8]; -- To view, visit https://review.coreboot.org/20839 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ica92850cc77e1f7cbf3e7e44717de42a03b93bbe Gerrit-Change-Number: 20839 Gerrit-PatchSet: 1 Gerrit-Owner: Aladyshev Konstantin <aladyshev22(a)gmail.com>

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Change in coreboot[master]: AGESA f15: Support DMI generation for Opteron 63XX family
by build bot (Jenkins) (Code Review) 01 Aug '17

01 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20838 ) Change subject: AGESA f15: Support DMI generation for Opteron 63XX family ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58099/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13530/ : SUCCESS -- To view, visit https://review.coreboot.org/20838 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8c5d487c0f45f61deb081be50c6701a42fbf9111 Gerrit-Change-Number: 20838 Gerrit-PatchSet: 1 Gerrit-Owner: Aladyshev Konstantin <aladyshev22(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Aug 2017 12:10:15 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: AGESA f15: Support DMI generation for Opteron 63XX family
by Aladyshev Konstantin (Code Review) 01 Aug '17

01 Aug '17

Aladyshev Konstantin has uploaded this change for review. ( https://review.coreboot.org/20838 Change subject: AGESA f15: Support DMI generation for Opteron 63XX family ...................................................................... AGESA f15: Support DMI generation for Opteron 63XX family Add support of DMI tables for AMD Opteron 6300 Series Processors. Correct value for CPU family is taken from SMBIOS reference specification. Change-Id: I8c5d487c0f45f61deb081be50c6701a42fbf9111 Signed-off-by: Konstantin Aladyshev <aladyshev22(a)gmail.com> --- M src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrDmi.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/20838/1 diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrDmi.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrDmi.c index 36824c1..838612a 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrDmi.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/cpuF15OrDmi.c @@ -74,18 +74,21 @@ *---------------------------------------------------------------------------------------- */ CONST CHAR8 ROMDATA str_Opteron_62[] = "AMD Opteron(tm) Processor 62"; +CONST CHAR8 ROMDATA str_Opteron_63[] = "AMD Opteron(tm) Processor 63"; CONST CHAR8 ROMDATA str_Opteron_42[] = "AMD Opteron(tm) Processor 42"; CONST CHAR8 ROMDATA str_Opteron_3[] = "AMD Opteron(tm) Processor 3"; CONST CHAR8 ROMDATA str_FX_AM3[] = "AMD FX(tm)-"; /*--------------------------------------------------------------------------------------- * Processor Family Table * 03Dh = "AMD Opteron(TM) 6200 Processor Family" + * 04Dh = "AMD Opteron(TM) 6300 Processor Family" * 03Eh = "AMD Opteron(TM) 4200 Processor Family" * 03Fh = "AMD FX(TM) Series Processor" *-------------------------------------------------------------------------------------*/ CONST CPU_T4_PROC_FAMILY ROMDATA F15OrG34T4ProcFamily[] = { - {str_Opteron_62, 0x3D} + {str_Opteron_62, 0x3D}, + {str_Opteron_63, 0x4D} }; CONST CPU_T4_PROC_FAMILY ROMDATA F15OrC32T4ProcFamily[] = -- To view, visit https://review.coreboot.org/20838 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8c5d487c0f45f61deb081be50c6701a42fbf9111 Gerrit-Change-Number: 20838 Gerrit-PatchSet: 1 Gerrit-Owner: Aladyshev Konstantin <aladyshev22(a)gmail.com>

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Change in coreboot[master]: AGESA: Correct PCI function number for MEM_GET(SET)REG outputs
by build bot (Jenkins) (Code Review) 01 Aug '17

01 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20837 ) Change subject: AGESA: Correct PCI function number for MEM_GET(SET)REG outputs ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58098/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13529/ : SUCCESS -- To view, visit https://review.coreboot.org/20837 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id41700be0474eecc4d5b5173c4d5686c421735e3 Gerrit-Change-Number: 20837 Gerrit-PatchSet: 1 Gerrit-Owner: Aladyshev Konstantin <aladyshev22(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Aug 2017 11:45:52 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: AGESA: Correct PCI function number for MEM_GET(SET)REG outputs
by Aladyshev Konstantin (Code Review) 01 Aug '17

01 Aug '17

Aladyshev Konstantin has uploaded this change for review. ( https://review.coreboot.org/20837 Change subject: AGESA: Correct PCI function number for MEM_GET(SET)REG outputs ...................................................................... AGESA: Correct PCI function number for MEM_GET(SET)REG outputs PCI function number takes only 3 bits, therefore correct bitmask for it is 0x7. Change-Id: Id41700be0474eecc4d5b5173c4d5686c421735e3 Signed-off-by: Konstantin Aladyshev <aladyshev22(a)gmail.com> --- M src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnregc32.c M src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnregda.c M src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnregdr.c M src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnreghy.c M src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnregln.c M src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnregc32.c M src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnregda.c M src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnregdr.c M src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnreghy.c M src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c M src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.c M src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnregc32.c M src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnregda.c M src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnregdr.c M src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnreghy.c M src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnregor.c M src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnor.c M src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnregtn.c M src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c 19 files changed, 38 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/20837/1 diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnregc32.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnregc32.c index b4335d6..ebf73e0 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnregc32.c +++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/C32/mnregc32.c @@ -209,7 +209,7 @@ LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Value); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); @@ -240,7 +240,7 @@ LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnregda.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnregda.c index 7d5b684..c721618 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnregda.c +++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DA/mnregda.c @@ -194,7 +194,7 @@ LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Value); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); @@ -220,7 +220,7 @@ LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnregdr.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnregdr.c index b84006b..9b871f2 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnregdr.c +++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/DR/mnregdr.c @@ -195,7 +195,7 @@ LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Value); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); @@ -221,7 +221,7 @@ LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnreghy.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnreghy.c index 8f59d4d..61cf26b 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnreghy.c +++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/HY/mnreghy.c @@ -210,7 +210,7 @@ LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Value); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); @@ -241,7 +241,7 @@ LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); diff --git a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnregln.c b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnregln.c index ff6e673..607fce0 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnregln.c +++ b/src/vendorcode/amd/agesa/f12/Proc/Mem/NB/LN/mnregln.c @@ -219,7 +219,7 @@ LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Value); } } else if (Type == DCT_PHY_ACCESS) { if (IsPhyDirectAccess && (NumOfInstances > 1)) { @@ -251,7 +251,7 @@ LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnregc32.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnregc32.c index c7b6dcf..715e072 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnregc32.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/C32/mnregc32.c @@ -211,7 +211,7 @@ LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Value); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); @@ -242,7 +242,7 @@ LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnregda.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnregda.c index 22dcee3..56d3880 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnregda.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DA/mnregda.c @@ -196,7 +196,7 @@ LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Value); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); @@ -222,7 +222,7 @@ LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnregdr.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnregdr.c index b549cba..317cfb7 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnregdr.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/DR/mnregdr.c @@ -197,7 +197,7 @@ LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Value); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); @@ -223,7 +223,7 @@ LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnreghy.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnreghy.c index a8a1170..da6d6fa 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnreghy.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/HY/mnreghy.c @@ -212,7 +212,7 @@ LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Value); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); @@ -243,7 +243,7 @@ LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c index e92dec0..109cd53 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnregon.c @@ -242,7 +242,7 @@ LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Value); } } else if (Type == DCT_PHY_ACCESS) { if (IsPhyDirectAccess && (NumOfInstances > 1)) { @@ -276,7 +276,7 @@ LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); diff --git a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.c b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.c index 7915b84..f9acf5a 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Recovery/Mem/NB/ON/mrnon.c @@ -345,7 +345,7 @@ LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Value); } } else if (Type == DCT_PHY_ACCESS) { if (IsPhyDirectAccess && (NumOfInstances > 1)) { @@ -377,7 +377,7 @@ LibAmdPciWrite (AccessWidth32, PciAddr , &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); } } else if (Type == DCT_PHY_ACCESS) { MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnregc32.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnregc32.c index 17c603f..953dd4c 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnregc32.c +++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/C32/mnregc32.c @@ -210,7 +210,7 @@ LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Value); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); @@ -241,7 +241,7 @@ LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnregda.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnregda.c index 336fb35..f97a550 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnregda.c +++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DA/mnregda.c @@ -195,7 +195,7 @@ LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Value); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); @@ -221,7 +221,7 @@ LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnregdr.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnregdr.c index 5c6207d..d74b75e 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnregdr.c +++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/DR/mnregdr.c @@ -196,7 +196,7 @@ LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Value); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); @@ -222,7 +222,7 @@ LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnreghy.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnreghy.c index 90bb9e4..5177cec 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnreghy.c +++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/HY/mnreghy.c @@ -211,7 +211,7 @@ LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Value); + IDS_HDT_CONSOLE (MEM_GETREG, "~Fn%d_%03x = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Value); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); @@ -242,7 +242,7 @@ LibAmdPciWrite (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctExtraDataReg) && (FieldName != BFDctExtraOffsetReg)) { - IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + IDS_HDT_CONSOLE (MEM_SETREG, "~Fn%d_%03x [%d:%d] = %x\n", (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnregor.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnregor.c index 512ef14..a29093f 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnregor.c +++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/NB/OR/mnregor.c @@ -238,7 +238,7 @@ if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctCfgSel)) { IDS_HDT_CONSOLE (MEM_GETREG, "~Dev%x Dct%d Fn%d_%03x = %x\n", NBPtr->PciAddr.Address.Device, NBPtr->Dct, - (Address >> 12) & 0xF, Address & 0xFFF, Value); + (Address >> 12) & 0x7, Address & 0xFFF, Value); } } else if (Type == DCT_PHY_ACCESS) { if (IsPhyDirectAccess && (NumOfInstances > 1)) { @@ -273,7 +273,7 @@ if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctCfgSel)) { IDS_HDT_CONSOLE (MEM_SETREG, "~Dev%x Dct%d Fn%d_%03x [%d:%d] = %x\n", NBPtr->PciAddr.Address.Device, NBPtr->Dct, - (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); diff --git a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnor.c b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnor.c index 8fcfc96..eb91bac 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnor.c +++ b/src/vendorcode/amd/agesa/f15/Proc/Recovery/Mem/NB/OR/mrnor.c @@ -548,7 +548,7 @@ LibAmdPciRead (AccessWidth32, PciAddr, &Value, &NBPtr->MemPtr->StdHeader); IDS_HDT_CONSOLE (MEM_GETREG, "~Dev%x Dct%d Fn%d_%03x = %x\n", NBPtr->PciAddr.Address.Device, NBPtr->Dct, - (Address >> 12) & 0xF, Address & 0xFFF, Value); + (Address >> 12) & 0x7, Address & 0xFFF, Value); } else if (Type == DCT_PHY_ACCESS) { MemRecNSetBitFieldNb (NBPtr, BFDctAddlOffsetReg, Address); while (MemRecNGetBitFieldNb (NBPtr, BFDctAccessDone) == 0) {} @@ -573,7 +573,7 @@ LibAmdPciWrite (AccessWidth32, PciAddr , &Value, &NBPtr->MemPtr->StdHeader); IDS_HDT_CONSOLE (MEM_SETREG, "~Dev%x Dct%d Fn%d_%03x [%d:%d] = %x\n", NBPtr->PciAddr.Address.Device, NBPtr->Dct, - (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); } else if (Type == DCT_PHY_ACCESS) { MemRecNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); Address |= DCT_ACCESS_WRITE; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnregtn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnregtn.c index ca2afb4..5bf1093 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnregtn.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mnregtn.c @@ -235,7 +235,7 @@ if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctCfgSel)) { IDS_HDT_CONSOLE (MEM_GETREG, "~Dev%x Dct%d Fn%d_%03x = %x\n", NBPtr->PciAddr.Address.Device, NBPtr->Dct, - (Address >> 12) & 0xF, Address & 0xFFF, Value); + (Address >> 12) & 0x7, Address & 0xFFF, Value); } } else if (Type == DCT_PHY_ACCESS) { if (IsPhyDirectAccess && (NumOfInstances > 1)) { @@ -266,7 +266,7 @@ if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctCfgSel)) { IDS_HDT_CONSOLE (MEM_SETREG, "~Dev%x Dct%d Fn%d_%03x [%d:%d] = %x\n", NBPtr->PciAddr.Address.Device, NBPtr->Dct, - (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); } } else if (Type == DCT_PHY_ACCESS) { MemNSetBitFieldNb (NBPtr, BFDctAddlDataReg, Value); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c index df810d0..f8b70b8 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/NB/KB/mnregkb.c @@ -234,7 +234,7 @@ if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctCfgSel)) { IDS_HDT_CONSOLE (MEM_GETREG, "~Dev%x Dct%d Fn%d_%03x = %x\n", NBPtr->PciAddr.Address.Device, NBPtr->Dct, - (Address >> 12) & 0xF, Address & 0xFFF, Value); + (Address >> 12) & 0x7, Address & 0xFFF, Value); } } else if (Type == DCT_PHY_ACCESS) { if (IsPhyDirectAccess && (NumOfInstances > 1)) { @@ -265,7 +265,7 @@ if ((FieldName != BFDctAddlDataReg) && (FieldName != BFDctAddlOffsetReg) && (FieldName != BFDctCfgSel)) { IDS_HDT_CONSOLE (MEM_SETREG, "~Dev%x Dct%d Fn%d_%03x [%d:%d] = %x\n", NBPtr->PciAddr.Address.Device, NBPtr->Dct, - (Address >> 12) & 0xF, Address & 0xFFF, Highbit, Lowbit, Field); + (Address >> 12) & 0x7, Address & 0xFFF, Highbit, Lowbit, Field); } } else if (Type == DCT_PHY_ACCESS) { ASSERT (!NBPtr->IsSupported[ScrubberEn]); // Phy CSR write is not allowed after scrubber is enabled -- To view, visit https://review.coreboot.org/20837 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id41700be0474eecc4d5b5173c4d5686c421735e3 Gerrit-Change-Number: 20837 Gerrit-PatchSet: 1 Gerrit-Owner: Aladyshev Konstantin <aladyshev22(a)gmail.com>

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Change in coreboot[master]: util/cbfstool: Fix build with armv7-eabi cross compiler
by build bot (Jenkins) (Code Review) 01 Aug '17

01 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20836 ) Change subject: util/cbfstool: Fix build with armv7-eabi cross compiler ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58097/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13528/ : SUCCESS -- To view, visit https://review.coreboot.org/20836 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I581e45639ac3e103af7c16793e8effe2e632dec7 Gerrit-Change-Number: 20836 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Aug 2017 09:46:53 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: util/cbfstool: Fix build with armv7-eabi cross compiler
by Patrick Georgi (Code Review) 01 Aug '17

01 Aug '17

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/20836 Change subject: util/cbfstool: Fix build with armv7-eabi cross compiler ...................................................................... util/cbfstool: Fix build with armv7-eabi cross compiler We recently changed all PACKED, __PACKED, __attribute__((packed)) ... to __packed to gain some consistency. In cbfstool we use compiler.h to provide that where necessary. The cross compiler I use doesn't provide __packed by itself, but liblz4 doesn't compensate for that. Therefore include compiler.h, and to avoid adding dependencies to non-liblz4 code, do so through the command line. Change-Id: I581e45639ac3e103af7c16793e8effe2e632dec7 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/cbfstool/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/20836/1 diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index 950092f..8e4d8b6 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -131,7 +131,7 @@ $(objutil)/cbfstool/%.o: $(top)/util/cbfstool/lz4/lib/%.c printf " HOSTCC $(subst $(objutil)/,,$(@))\n" - $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< + $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -include $(top)/util/cbfstool/compiler.h -c -o $@ $< $(objutil)/cbfstool/cbfstool: $(addprefix $(objutil)/cbfstool/,$(cbfsobj)) printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n" -- To view, visit https://review.coreboot.org/20836 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I581e45639ac3e103af7c16793e8effe2e632dec7 Gerrit-Change-Number: 20836 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com>

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coreboot-gerrit August 2017