coreboot-gerrit August 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: drivers/uart: Use baudrate of 115200 by default
by build bot (Jenkins) (Code Review) 01 Aug '17

01 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20834 ) Change subject: drivers/uart: Use baudrate of 115200 by default ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58118/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13548/ : SUCCESS -- To view, visit https://review.coreboot.org/20834 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ida4c7ae77aba5dfd4ec331e22a54ce43a91bde00 Gerrit-Change-Number: 20834 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Aug 2017 19:27:33 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Allow SoC to enable UART resources
by build bot (Jenkins) (Code Review) 01 Aug '17

01 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20851 ) Change subject: soc/intel/common: Allow SoC to enable UART resources ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58122/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/13550/ : ABORTED -- To view, visit https://review.coreboot.org/20851 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id21447b090d8ed8c44b3b464f49ea12de58fbee2 Gerrit-Change-Number: 20851 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Aug 2017 19:23:37 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Add lpss.c to ramstage
by build bot (Jenkins) (Code Review) 01 Aug '17

01 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20850 ) Change subject: soc/intel/common: Add lpss.c to ramstage ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58121/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/13549/ : SUCCESS -- To view, visit https://review.coreboot.org/20850 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e05d65ebb3b6499451242521ffc61fc4c952830 Gerrit-Change-Number: 20850 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Aug 2017 19:23:36 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Allow SoC to enable UART resources
by Furquan Shaikh (Code Review) 01 Aug '17

01 Aug '17

Furquan Shaikh has uploaded a new patch set (#3). ( https://review.coreboot.org/20851 ) Change subject: soc/intel/common: Allow SoC to enable UART resources ...................................................................... soc/intel/common: Allow SoC to enable UART resources This changed provides a callback pch_uart_enable_resources that allows SoC to enable UART controller if necessary. This is required to workaround the issue where Linux kernel hangs on resume if serial console is disabled in coreboot but enabled in kernel. BUG=b:64030366 Change-Id: Id21447b090d8ed8c44b3b464f49ea12de58fbee2 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/uart/uart.c 2 files changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/20851/3 -- To view, visit https://review.coreboot.org/20851 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id21447b090d8ed8c44b3b464f49ea12de58fbee2 Gerrit-Change-Number: 20851 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/common: Add lpss.c to ramstage
by Furquan Shaikh (Code Review) 01 Aug '17

01 Aug '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/20850 to look at the new patch set (#3). Change subject: soc/intel/common: Add lpss.c to ramstage ...................................................................... soc/intel/common: Add lpss.c to ramstage BUG=b:64030366 Change-Id: I7e05d65ebb3b6499451242521ffc61fc4c952830 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/intel/common/block/lpss/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/20850/3 -- To view, visit https://review.coreboot.org/20850 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7e05d65ebb3b6499451242521ffc61fc4c952830 Gerrit-Change-Number: 20850 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/skylake: Enable UART debug port on S3 resume
by build bot (Jenkins) (Code Review) 01 Aug '17

01 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20835 ) Change subject: soc/intel/skylake: Enable UART debug port on S3 resume ...................................................................... Patch Set 5: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58120/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/13547/ : ABORTED -- To view, visit https://review.coreboot.org/20835 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic936ac2a787fdc83935103c3ce4ed8f124a97a89 Gerrit-Change-Number: 20835 Gerrit-PatchSet: 5 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Aug 2017 19:22:52 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Add lpss.c to ramstage
by build bot (Jenkins) (Code Review) 01 Aug '17

01 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20850 ) Change subject: soc/intel/common: Add lpss.c to ramstage ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58119/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/13546/ : SUCCESS -- To view, visit https://review.coreboot.org/20850 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e05d65ebb3b6499451242521ffc61fc4c952830 Gerrit-Change-Number: 20850 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Aug 2017 19:22:52 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Allow SoC to enable UART resources
by Furquan Shaikh (Code Review) 01 Aug '17

01 Aug '17

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/20851 Change subject: soc/intel/common: Allow SoC to enable UART resources ...................................................................... soc/intel/common: Allow SoC to enable UART resources This changed provides a callback pch_uart_enable_resources that allows SoC to enable UART controller if necessary. This is required to workaround the issue where Linux kernel hangs on resume if serial console is disabled in coreboot but enabled in kernel. BUG=b:64030366 Change-Id: Id21447b090d8ed8c44b3b464f49ea12de58fbee2 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/uart/uart.c 2 files changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/20851/1 diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h index b46edd7..133ef75 100644 --- a/src/soc/intel/common/block/include/intelblocks/uart.h +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -23,5 +23,6 @@ uint32_t clk_m_val, uint32_t clk_n_val); void pch_uart_read_resources(struct device *dev); +void pch_uart_enable_resources(struct device *dev); #endif /* SOC_INTEL_COMMON_BLOCK_UART_H */ diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 632fb95..c6e4011 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -43,10 +43,21 @@ pci_dev_read_resources(dev); } +__attribute__((weak)) void pch_uart_enable_resources(struct device *dev) +{ + /* Default weak implementation - does nothing. */ +} + +static void uart_common_enable_resources(struct device *dev) +{ + pci_dev_enable_resources(dev); + pch_uart_enable_resources(dev); +} + static struct device_operations device_ops = { .read_resources = &pch_uart_read_resources, .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, + .enable_resources = &uart_common_enable_resources, }; static const unsigned short pci_device_ids[] = { -- To view, visit https://review.coreboot.org/20851 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id21447b090d8ed8c44b3b464f49ea12de58fbee2 Gerrit-Change-Number: 20851 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/common: Add lpss.c to ramstage
by Furquan Shaikh (Code Review) 01 Aug '17

01 Aug '17

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/20850 Change subject: soc/intel/common: Add lpss.c to ramstage ...................................................................... soc/intel/common: Add lpss.c to ramstage BUG=b:64030366 Change-Id: I7e05d65ebb3b6499451242521ffc61fc4c952830 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/intel/common/block/lpss/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/20850/1 diff --git a/src/soc/intel/common/block/lpss/Makefile.inc b/src/soc/intel/common/block/lpss/Makefile.inc index bb65bfe..50d1c10 100644 --- a/src/soc/intel/common/block/lpss/Makefile.inc +++ b/src/soc/intel/common/block/lpss/Makefile.inc @@ -1,3 +1,4 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c verstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS) += lpss.c -- To view, visit https://review.coreboot.org/20850 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7e05d65ebb3b6499451242521ffc61fc4c952830 Gerrit-Change-Number: 20850 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: libpayload: video: Add support for font scaling with a factor
by build bot (Jenkins) (Code Review) 01 Aug '17

01 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20709 ) Change subject: libpayload: video: Add support for font scaling with a factor ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58117/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13545/ : SUCCESS -- To view, visit https://review.coreboot.org/20709 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idff210617c9ec08c6034aef107cfdb34c7cdf029 Gerrit-Change-Number: 20709 Gerrit-PatchSet: 3 Gerrit-Owner: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Ben Gardner <gardner.ben(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Kocialkowski <contact(a)paulk.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Peter Stuge <peter(a)stuge.se> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 01 Aug 2017 18:55:27 +0000 Gerrit-HasComments: No

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coreboot-gerrit August 2017